CN114023662A

CN114023662A - Fan-out type packaging structure

Info

Publication number: CN114023662A
Application number: CN202111093731.1A
Authority: CN
Inventors: 翁振源; 李铮鸿; 闵繁宇; 刘修吉; 赖仲航
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-09-17
Filing date: 2021-09-17
Publication date: 2022-02-08

Abstract

An embodiment of the present invention provides a fan-out package structure, including: a first electronic component and a second electronic component arranged side by side, the first electronic component comprising: a functional bump array located at the center of the lower surface of the first electronic component; a dummy bump located between the functional bump array and a boundary of the lower surface of the first electronic component; and the circuit layer is positioned below the first electronic element and the second electronic element, the functional bump arrays of the second electronic element and the first electronic element are electrically connected to the circuit layer, and the dummy bumps of the first electronic element are in physical contact with the circuit layer. The invention aims to provide a fan-out type packaging structure to improve the yield of the fan-out type packaging structure.

Description

Fan-out type packaging structure

Technical Field

Embodiments of the present application relate to fan-out package structures.

Background

In a fan-out package structure, particularly a fan-out chip on substrate (FOCOS) package, Coefficient of Thermal Expansion (CTE) mismatch between materials can generate warpage during thermal cycling, and stress generated by warpage cannot be directly released due to an integral structure, so that a crack is easily generated around an electronic component located at a stress concentration point and a circuit layer is directly damaged downwards.

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide a fan-out package structure to improve the yield of the fan-out package structure.

To achieve the above object, an embodiment of the present invention provides a fan-out package structure, including: a first electronic component and a second electronic component arranged side by side, the first electronic component comprising: a functional bump array located at the center of the lower surface of the first electronic component; a dummy bump located between the functional bump array and a boundary of the lower surface of the first electronic component; and the circuit layer is positioned below the first electronic element and the second electronic element, the functional bump arrays of the second electronic element and the first electronic element are electrically connected to the circuit layer, and the dummy bumps of the first electronic element are in physical contact with the circuit layer.

In some embodiments, the dummy bumps abut the boundary.

In some embodiments, the false positive is located at a corner of the lower surface.

In some embodiments, the dummy bumps are located on both sides of a line connecting the center of the lower surface and the corner.

In some embodiments, the false positive is also located on a line connecting the center and the corner of the lower surface.

In some embodiments, the dummy bumps at a single corner have an L-shape.

In some embodiments, the L-shape is parallel to the boundaries at the corners.

In some embodiments, further comprising: and the filling layer coats the first electronic element and the second electronic element.

In some embodiments, the first electronic component and the second electronic component are separated by a fill layer.

In some embodiments, further comprising: and the bonding layer is positioned among the first electronic component, the second electronic component and the circuit layer, and the functional bump array and the dummy bumps of the first electronic component penetrate through the bonding layer.

In some embodiments, the fill layer and the adhesive layer have different coefficients of thermal expansion.

In some embodiments, the lateral dimension of the second electronic element is greater than the lateral dimension of the first semiconductor die.

In some embodiments, the dummy bumps have a first distance from the boundary and the array of functional bumps have a second distance from the boundary, the first distance being less than the second distance.

In some embodiments, the first electronic component is a High Bandwidth Memory (HBM) die.

In some embodiments, the second electronic component is an Application Specific Integrated Circuit (ASIC) chip.

In some embodiments, the dummy bumps of the first electronic component are located between the second electronic component and the array of functional bumps.

In some embodiments, the lower surface of the second electronic component has a second bump, a third distance is provided between the second bump and the dummy bump, a first distance is provided between the dummy bump and the boundary, and a ratio of the first distance to the third distance is in a range of 0 to 0.5.

In some embodiments, the array of functional bumps, the dummy bumps, and the second bumps are located in a same plane.

In some embodiments, the dummy bumps include an under bump metallization on the lower surface and a second solder on the under bump metallization.

In some embodiments, the dummy bumps physically contact the fourth metal layer in the line layer.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1-6 and 20-22 show schematic diagrams of a fan-out package structure and an electronic component according to embodiments of the application.

Fig. 7 to 19 show a process of forming a dummy bump on an electronic component according to an embodiment of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

As the functional and performance requirements of semiconductor chips increase, the degree of integration increases, the number of layers of lines (e.g., redistribution layers (RDLs)) is increased, and the layers of the lines are generally soft and cannot effectively bear the stress concentration phenomenon caused by a multi-chip module (MCM). As the number of layers of the circuit is increased and the number of chips is more densely distributed, the stress at the interface between the chips is increased, so that the underfill cannot withstand deformation and is broken. Multi-chip module systems are complicated and stress buildup problems are severe, which can also lead to underfill cracking. When the chip is heated and heated, the chip is warped due to the complex structure and large expansion amount in the chip and is easily separated from the fan-out line layer.

A High Bandwidth Memory (HBM) tube core is a composite 3D packaging assembly and contains a large amount of high polymer materials, so that the assembly is easily affected by heat to generate deformation and warping, but the internal materials cannot be replaced by non-high polymer materials at present.

Referring to fig. 1, fig. 1 illustrates a partial cross-sectional view of a fan-out package structure provided according to an embodiment of the present invention, including: a first electronic component 10 and a second electronic component 12 arranged side by side; and the circuit layer 14 is positioned below the first electronic element 10 and the second electronic element 12. In some embodiments, further comprising: and the filling layer 16 covers the first electronic element 10 and the second electronic element 12. In some embodiments, the first electronic component 10 and the second electronic component 12 are separated by a filler layer 16. In some embodiments, the filler layer 16 comprises a mold Compound (CPD) or underfill (underfill). in some embodiments, the filler layer 16 is also located between the first electronic component 10, the second electronic component 12, and the wiring layer 14. In some embodiments, further comprising: and an adhesive layer (not shown) between the first electronic component 10, the second electronic component 12, and the wiring layer 14, through which the functional bump array 102 and the dummy bumps 104 of the first electronic component 10 pass. In some embodiments, the fill layer 16 and the adhesive layer have different coefficients of thermal expansion. In some embodiments, the coefficient of thermal expansion of the adhesive layer is greater than the coefficient of thermal expansion of the filler layer 16. In some embodiments, the material of the adhesive layer includes Polyimide (PI). When the package is heated, the side of the wiring layer 14 on which the filler layer 16 and the adhesive layer are located is largely deformed (expanded). The filler layer 16 on the side of the line layer 14 is therefore at risk of cracking. The dummy bumps 104 of the embodiments of the present application increase the connection strength between the first electronic component 10 and the wiring layer 14, reduce deformation of the package, and reduce the risk of cracking of the filling layer 16. In some embodiments, the lateral dimension of the second electronic component 12 is greater than the lateral dimension of the first semiconductor die 10. In some embodiments, a plurality of first electronic components 10 are disposed around the second electronic component 12. In some embodiments, the first electronic element 10 is a High Bandwidth Memory (HBM) die. In some embodiments, the second electronic component 12 is an Application Specific Integrated Circuit (ASIC) chip. In some embodiments, the first electronic component 10 and the second electronic component 12 have different coefficients of thermal expansion.

Referring to fig. 2, fig. 2 shows a bottom view of the first electronic component 10, including: a functional bump array 102 located at the center of the lower surface 101 of the first electronic component 10; and dummy bumps 104 between the functional bump array 102 and a boundary 103 of the lower surface 101 of the first electronic component 10. The second electronic component 12 and the functional bump array 102 of the first electronic component 10 are electrically connected to the wiring layer 14, and the dummy bumps 104 of the first electronic component 10 physically contact the wiring layer 14.

In some embodiments, the dummy bumps 104 and the boundary 103 have a first distance D1 therebetween, the dummy bumps 104 and the functional bump array 102 have a second distance D2 therebetween, and the first distance D1 is less than the second distance D2.

Fig. 3 and 4 show detailed views of fig. 1 according to various embodiments. Referring to fig. 3, in some embodiments, the lower surface of the second electronic component 12 has the second bump 122, the second bump 122 has a third distance D3 from the dummy bump 104, the dummy bump 104 has a first distance D1 from the boundary 103, and a ratio of the first distance D1 to the third distance D3 is in a range from 0 to 0.5. In the embodiment of the present application, the distance between the first electronic component 10 and the second electronic component 12 is enlarged, so that the problem of cracking of the underfill (filling layer 16) caused by stress concentration is reduced. In some embodiments, the dummy bumps 104 of the first electronic component 10 are located between the second electronic component 12 and the functional bump array 102, and the dummy bumps 104 are located on a side close to the second electronic component 12. In some embodiments, the functional bump array 102, the dummy bumps 104, and the second bumps 122 are located in the same plane. In some embodiments, the dummy bumps 104 physically contact the fourth metal layer 141 in the line layer 14.

In the first embodiment, the gap G between the first electronic component 10 and the second electronic component 12 is 50 μm, the distance D4 between the second bump 122 and the boundary 123 of the second electronic component 12 is 250 μm, the first distance D1 between the dummy bump 104 and the boundary 103 is 250 μm, the third distance D3 between the second bump 122 and the dummy bump 104 is D1+ G + D4 is 550 μm, and the ratio of the first distance D1 to the third distance D3 is 0.4545.

In the second embodiment, unlike the first embodiment, the gap G between the first electronic component 10 and the second electronic component 12 is 70 μm, and the ratio of the first distance D1 to the third distance D3 is 0.4386.

In the third embodiment, unlike the first embodiment, the gap G between the first electronic component 10 and the second electronic component 12 is 400 μm, and the ratio of the first distance D1 to the third distance D3 is 0.2777.

In the fourth embodiment, unlike the first embodiment, the first distance D1 between the dummy bump 104 and the boundary 103 is 300 μm, and the ratio of the first distance D1 to the third distance D3 is 0.5.

In the fifth embodiment, unlike the first embodiment, the gap G between the first electronic component 10 and the second electronic component 12 is 400 μm, the first distance D1 between the dummy bump 104 and the boundary 103 is 300 μm, and the ratio of the first distance D1 to the third distance D3 is 0.3158.

Referring to fig. 4, in some embodiments, the dummy bump 104 abuts the boundary 103 and the first distance D1 is 0.

In the sixth embodiment, the gap G between the first electronic component 10 and the second electronic component 12 is 50 μm, the distance D4 between the second bump 122 and the boundary 123 of the second electronic component 12 is 250 μm, the first distance D1 between the dummy bump 104 and the boundary 103 is 0, the third distance D3 between the second bump 122 and the dummy bump 104 is D1+ G + D4 is 300 μm, and the ratio of the first distance D1 to the third distance D3 is 0.

Referring to fig. 5 and 6, in some embodiments, the false positive 104 is located at a corner of the lower surface 101. In some embodiments, the dummy bumps 104 are located on both sides of a line L connecting the center O of the lower surface 101 and the corner a. Referring to fig. 6, in some embodiments, the dummy bumps 104 are also located on a line L connecting the center O of the lower surface 101 and the corner a. Because of the Distance to Neutral Point (DNP) effect (the farther corner from the center Point of the chip, the more severe the stress concentration, the more likely the risk of breaking or separating the bump from the filling layer 16), if the dummy bump is only located on the connection line L, the problem of breaking the dummy bump 104 is likely to occur, and the possibility of hitting other components is likely to occur, so that there are a plurality of dummy bumps 104 on both sides of the connection line L, which can disperse the stress borne by the dummy bumps 104 located on the connection line L, thereby avoiding the problem of breaking or separating.

Fig. 7 to 19 do not show the whole of the first electronic component 10, and only two dummy bumps 1041 are used as an example to show the formation process of the dummy bumps 104 on the surface of the first electronic component 10.

Referring to fig. 7, the first metal layer 70 of the first electronic component 10 is exposed. In some embodiments, the material of the first metal layer 70 includes Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. In some embodiments, the first electronic component 10 includes a first dielectric layer 72 and a connector 74 located in the first dielectric layer 72.

Referring to fig. 8, a first seed layer 80 is formed on the first metal layer 70, and in some embodiments, the material of the first seed layer 80 includes Cu, Au, Ag, Al, Pd, Pt, Ni, an alloy thereof, or a combination thereof, and the first seed layer 80 is formed using a sputtering process.

Referring to fig. 9, a first seed layer 80 is patterned, a first mask 90 is formed beside the patterned first seed layer 80, and a first solder 91 and a second metal layer 92 are formed on the first seed layer 80. In forming the first mask 90, the first mask 90 is first tiled over the patterned first seed layer 80, and then the first mask 90 is patterned using a photolithography process to expose the patterned first seed layer 80. In some embodiments, a protective layer 94 is formed on the second metal layer 92. In some embodiments, the first mask 90 comprises a Photoresist (PR) material. In some embodiments, the materials of the first solder 91 and the second metal layer 92 include Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. The first solder 91 and the second metal layer 92 may be formed using Physical Vapor Deposition (PVD), sputtering, electroplating, electroless plating (E' less), and/or printing, laminating, and/or potting processes. In some embodiments, the material of the protective layer 94 includes organic substances, such as Polyimide (PI), epoxy (epoxy), Polybenzoxazole (PBO), flame retardant grade 4 material (FR4), semi-cured resin (prepreg, PP), Ajinomotobuild-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances, such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), nitrides (e.g., SiNx).

Referring to fig. 10, the first mask 90 is removed and then the protective layer 94 is removed.

Referring to fig. 11, a carrier substrate 110 is provided, and a release layer 112 is formed on the carrier substrate 110. The carrier substrate 110 may be a glass carrier substrate, a ceramic carrier substrate, a wafer, or the like. The release layer 112 may be formed of a polymer-based material that may be removed from the carrier substrate 110 in a subsequent step. In some embodiments, the release layer 112 is an epoxy-based thermal release material that loses its adhesion upon heating, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 112 may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV light. The release layer 112 may be dispensed in liquid form and cured, may be a laminated film laminated on the carrier substrate 110, or may be similar. The structure shown in fig. 10 is placed upside down on the carrier substrate 110 and the release layer 112, and the first seed layer 80, the first solder 91, and the second metal layer 92 are buried in the release layer 112.

Referring to fig. 12, a portion of first dielectric layer 72 is removed to expose connectors 74. in some embodiments, a backside planarization process (e.g., grinding) is performed to remove portions of first dielectric layer 72, and then a dry etching process is performed to expose connectors 74.

Referring to fig. 13, an isolation layer 130 is formed over the first dielectric layer 72 and the exposed connectors 74.

Referring to fig. 14, a Chemical Mechanical Polishing (CMP) process is performed to expose the top surface of the connection 74.

Referring to fig. 15, a sputtering process is performed to form a third metal layer 150. In some embodiments, the material of the third metal layer 150 includes Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof.

Referring to fig. 16, in some embodiments, a second mask 160 is formed overlying the third metal layer 150, and in some embodiments, the second mask 160 comprises a Photoresist (PR) material. The second mask 160 is patterned, and a second solder 162 is formed in the patterned second mask 160. In some embodiments, the material of the second solder 162 includes Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. The second solder 162 may be formed using Physical Vapor Deposition (PVD), sputtering, electroplating, electroless plating (E' less), and/or printing, laminating, and/or potting processes. In some embodiments, the second solder 162 is a Controlled Collapse Chip Connection (C4) bump.

Referring to fig. 17, the second mask 160 is removed and a portion of the third metal layer 150 not covered by the second solder 162 is removed using the second solder 162 as a mask, and the remaining third metal layer 150 constitutes an Under Bump Metallurgy (UBM) 170.

Referring to fig. 18, a reflow process is performed to form the second solder 162 to be flush with the sidewalls of the under bump metallization 170. The combination of the under bump metallization 170 and the second solder 162 forms the dummy bump 104.

Referring to fig. 19, the carrier substrate 110 and the release layer 112 are removed.

Fig. 20 shows a schematic structural diagram of the first electronic component 10 according to an embodiment of the present application. Here, the portion in the dashed line frame E is the functional bump array 102, and the portion in the dashed line frame F is the dummy bump 104.

Fig. 21 and 22 illustrate bottom views of a first electronic component 10 and portions of a cross section of a fan-out package structure according to some embodiments of the present application. Referring to fig. 21 and 22, in some embodiments, the dummy bumps 104 located at a single corner a have an L-shape. In some embodiments, the L-shape is parallel to the boundary 103 at corner a.

The embodiments of the present application expand the distance between the chips (e.g., the first electronic component 10 and the second electronic component 12) and fill the underfill (e.g., the filling layer 16) between the chips, thereby increasing the underfill shrinkage and controlling the chip warpage (less than ± 100 μm). The embodiments of the present disclosure provide the dummy bumps 104 at the corners of the first electronic component 10 (e.g., the HBM), increase the bonding strength between the HBM and the RDL (e.g., the circuit layer 14), reduce the stress concentration at the corners of the HBM, and increase the anti-pulling capability between the edge of the first electronic component 10 and the circuit layer 14 by the dummy bumps 104 when the package is warped by heat. The embodiment of the present application arranges the first electronic component 10 and the second electronic component 12 side by side, increasing the size of the fan-out package structure.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A fan-out package structure, comprising:

a first electronic component and a second electronic component arranged side by side, the first electronic component comprising:

an array of functional bumps located at a center of a lower surface of the first electronic component;

a dummy bump located between the array of functional bumps and a boundary of the lower surface of the first electronic element;

a wiring layer under the first and second electronic components, the second electronic component and the array of functional bumps of the first electronic component being electrically connected to the wiring layer, the dummy bumps of the first electronic component physically contacting the wiring layer.

2. The fan-out package structure of claim 1, wherein the dummy bumps abut the boundary.

3. The fan-out package structure of claim 1, wherein the dummy bumps are located at corners of the lower surface.

4. The fan-out package structure of claim 3, wherein the dummy bumps are located on two sides of a line connecting the center of the lower surface and the corner.

5. The fan-out package structure of claim 4, wherein the dummy bumps are further located on the line connecting the center of the lower surface and the corner.

6. The fan-out package structure of any one of claims 3 to 5, wherein the dummy bumps at a single one of the corners have an L-shape.

7. The fan-out package structure of claim 6, wherein the L-shape is parallel to the boundary at the corner.

8. The fan-out package structure of claim 1, further comprising:

and the filling layer coats the first electronic element and the second electronic element.

9. The fan-out package structure of claim 8, further comprising:

and an adhesive layer between the first electronic component, the second electronic component, and the wiring layer, the functional bump array and the dummy bumps of the first electronic component passing through the adhesive layer.

10. The fan-out package structure of claim 1, wherein the lower surface of the second electronic component has a second bump, the second bump and the dummy bump have a third distance therebetween, the dummy bump and the boundary have a first distance therebetween, and a ratio of the first distance to the third distance is in a range from 0 to 0.5.