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CN114036889B - Layout Design Method for Edge Cells in Standard Cell Library - Google Patents

Layout Design Method for Edge Cells in Standard Cell Library Download PDF

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CN114036889B
CN114036889B CN202111268380.3A CN202111268380A CN114036889B CN 114036889 B CN114036889 B CN 114036889B CN 202111268380 A CN202111268380 A CN 202111268380A CN 114036889 B CN114036889 B CN 114036889B
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well
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edge unit
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CN114036889A (en
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张凯
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

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Abstract

The invention discloses a layout design method of edge units of a standard unit library, which comprises the following steps of firstly determining basic parameters of the edge units according to basic parameters of a corresponding standard unit library and minimum design rules in design rule files provided by flow sheet manufacturers, secondly designing the edge units according to the basic parameters of the edge units and the layout design rules, wherein the six edge units are respectively a first edge unit, a second edge unit, a third edge unit, a fourth edge unit, a fifth edge unit and a sixth edge unit, and thirdly reasonably inserting the edge units into the outer edges of IP modules when the digital rear end performs layout of the designed edge units so as to realize P-well isolation. The invention optimizes the design development flow of the standard cell library, can realize the horizontal splicing of standard cells with different device types, and improves the design efficiency of the rear end of the digital circuit.

Description

Layout design method for standard cell library edge cells
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a layout design method of standard cell library edge cells.
Background
The FDSOI (Fully Depleted-Silicon-On-Insulator) technology is characterized in that in the manufacturing process of an integrated circuit, a Silicon substrate structure mode, an insulating layer and Silicon substrate structure mode are adopted, so that the parasitic capacitance of a device is greatly reduced, and the performance of the device is improved. Under the FDSOI process, the adjustment of the device performance can be realized by changing the P/N well potential. To isolate the P-Well (P-Well), to achieve the potential adjustment of the P-Well, and avoid its failure due to conduction with the substrate, an N-Well (N-Well) Guard Ring (Guard-Ring) 102 needs to be added to the periphery of the IP block 101, as shown in fig. 1. Since the guard ring size is related to the IP block size, the corresponding guard ring needs to be customized for different IP blocks.
Disclosure of Invention
Aiming at the situation, in order to overcome the defects of the prior art, the invention provides a layout design method of standard cell library edge cells.
The invention solves the technical problems by adopting the following technical scheme that the layout design method of the standard cell library edge cells is characterized by comprising the following steps:
step one, determining basic parameters of an edge unit according to basic parameters of a corresponding standard unit library and a minimum design rule in a design rule file provided by a streaming manufacturer;
Designing the edge unit according to the basic parameters of the edge unit and the layout design rule, wherein six edge units are respectively a first edge unit, a second edge unit, a third edge unit, a fourth edge unit, a fifth edge unit and a sixth edge unit;
And thirdly, reasonably inserting the edge unit into the outer edge of the IP module when the digital rear end designs the layout of the edge unit, thereby realizing P well isolation.
Preferably, the basic parameters of the standard cell library comprise a first cell height, a first power bus width, a first ground bus width, a first Poly horizontal wiring interval, a first P/N region dividing line and a first N well side line, and the basic parameters of the edge cells comprise a second cell height, a second power bus width, a second ground bus width, a second Poly horizontal wiring interval, a second P/N region dividing line and a second N well side line.
Preferably, the second cell height is the same as the relative height of all standard cells in the corresponding standard cell library.
Preferably, the second power bus width is the same as the first power bus width of all standard cells in the corresponding standard cell library, and the second ground bus width is the same as the first ground bus width of all cells in the corresponding standard cell library.
Preferably, the second Poly horizontal wiring distance is the center line distance of two adjacent Poly, and is determined by the design rule of the process platform.
Preferably, the second P/N region boundary is a boundary position between the PMOS region and the NMOS region of the edge unit, and the second P/N region boundary is the same as a relative position of all standard cells in the corresponding standard cell library, where the relative position is a position relative to the origin.
Preferably, the second N-well side line is a center line distance between two adjacent N-well side lines.
The invention has the positive progress effects that the design development flow of the standard cell library is optimized, the standard cells of different device types can be horizontally spliced, and the design efficiency of the rear end of the digital circuit is improved.
Drawings
Fig. 1 is a schematic diagram of a structure in which an N-well guard ring is added to the periphery of an IP block according to the prior art.
Fig. 2A to fig. 2F are schematic structural views of six edge units according to the present invention.
FIG. 3 is a schematic layout of an edge cell according to the present invention.
FIG. 4 is a schematic diagram of a layout of a first edge cell according to the present invention.
FIG. 5 is a schematic diagram of a layout of a second edge cell according to the present invention.
Fig. 6 is a schematic layout diagram of a third edge unit in the present invention.
FIG. 7 is a schematic diagram of a fourth edge cell layout according to the present invention.
FIG. 8 is a schematic layout of a fifth edge cell according to the present invention.
FIG. 9 is a schematic layout of a sixth edge cell according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The layout design method of the standard cell library edge cell comprises the following steps:
step one, determining basic parameters of an edge unit according to basic parameters of a corresponding standard unit library and a minimum design rule in a design rule file provided by a streaming manufacturer;
Step two, designing the edge unit according to the basic parameters and layout design rules of the edge unit, wherein six edge units are specifically shown in fig. 2A to 2F, namely a first edge unit 1, a second edge unit 2, a third edge unit 3, a fourth edge unit 4, a fifth edge unit 5 and a sixth edge unit 6;
And step three, reasonably inserting the edge unit into the outer edge of the IP module 101 when the digital rear end designs the layout of the edge unit, thereby realizing P-well isolation, as shown in fig. 3.
The basic parameters of the standard cell library comprise a first cell height, a first power bus width, a first ground bus width, a first Poly horizontal wiring interval, a first P/N region dividing line and a first N well side line, and the basic parameters of the edge cells comprise a second cell height, a second power bus width, a second ground bus width, a second Poly horizontal wiring interval, a second P/N region dividing line and a second N well side line, which are convenient to correspond.
The second cell height is the same as the relative height of all standard cells in the corresponding standard cell library, which is the height relative to the origin.
The width of the second power bus is the same as the width of the first power bus corresponding to all standard units in the standard unit library, and the width of the second ground bus is the same as the width of the first ground bus corresponding to all units in the standard unit library, so that the standard unit library is convenient to use in a matched manner.
The second Poly horizontal wire pitch is the centerline distance of two adjacent Poly (polysilicon) s, as determined by the design rule of the process platform.
The second P/N area boundary is the boundary position of the PMOS area and the NMOS area of the edge unit, the position of the second P/N area boundary is the same as the relative position of all standard units in the corresponding standard unit library, and the relative position is the position relative to the origin.
The second N-well edge is the center line distance between two adjacent N-well edges, and is determined by the design rule (design rule) of the process platform.
As shown in fig. 4, as can be seen from fig. 4, in the layout of the first edge unit in the embodiment of the present invention, deep N-Well covers the entire edge unit, PMOS region is covered by N-Well layer, and NMOS region is covered by P-Well layer. The design rule limit shown in the figure refers to the minimum design rule and one half of the minimum rule (collectively referred to as a total rule D) provided by the wafer foundry, so that the unit layout can be checked through the design rule after automatic splicing. The embodiment is suitable for the upper edge and the lower edge of the IP module, and the inner side can be spliced with NMOS of the P substrate in the vertical direction.
As shown in fig. 5, as can be seen from fig. 5, in the layout of the second edge cell in the embodiment of the present invention, deep N-Well covers the entire edge cell, the NMOS region is covered by the N-Well layer, and the PMOS region is covered by the P-Well layer. The design rule limit shown in the figure is that the unit layout can be checked through the design rule after automatic splicing according to the minimum design rule and one half of the minimum rule provided by the wafer foundry. The embodiment is suitable for the upper edge and the lower edge of the IP module, and the inner side can be spliced with the PMOS of the P substrate in the vertical direction.
As shown in fig. 6, as can be seen from fig. 6, in the layout of the third edge unit in the embodiment of the present invention, deep N-Well covers the entire edge unit, the left half of the PMOS region and the NMOS region are covered by the N-Well layer, and then the right half of the NMOS region is P-Well. The design rule limit shown in the figure is that the unit layout can be checked through the design rule after automatic splicing according to the minimum design rule and one half of the minimum rule provided by the wafer foundry. The embodiment is suitable for the left edge and the right edge of the IP module, the inner side can be spliced with the standard units of the P substrate NMOS and the N substrate PMOS in the horizontal direction, and the standard units can also be used as corner edge units (Corner Boundary Cell).
As shown in fig. 7, as can be seen from fig. 7, in the layout of the fourth edge unit in the embodiment of the present invention, deep N-Well covers the entire edge unit, the left half of the NMOS region and the PMOS region are covered by the N-Well layer, and then the right half of the PMOS region is P-Well. The design rule limit shown in the figure is that the unit layout can be checked through the design rule after automatic splicing according to the minimum design rule and one half of the minimum rule provided by the wafer foundry. The embodiment is suitable for the left edge and the right edge of the IP module, the inner side can be spliced with the standard units of the N-substrate NMOS and the P-substrate PMOS in the horizontal direction, and the standard units can also be used as corner edge units.
As shown in fig. 8, it can be seen from fig. 8 that in the layout of the fifth edge cell in the embodiment of the present invention, deep N-Well covers the entire edge cell, and both the PMOS region and the NMOS region are covered by the N-Well layer. The design rule limit shown in the figure is that the unit layout can be checked through the design rule after automatic splicing according to the minimum design rule and one half of the minimum rule provided by the wafer foundry. The embodiment is suitable for the upper and lower edges of the module, can be spliced with NMOS of an N substrate or PMOS of the N substrate in the vertical direction, is simultaneously suitable for the left and right edges of an IP module, can be spliced with standard units of NMOS of the N substrate and PMOS of the N substrate in the horizontal direction, and can also be used as corner edge units.
As shown in fig. 9, as can be seen from fig. 9, in the layout of the sixth edge unit in the embodiment of the present invention, deep N-Well covers the entire edge unit, and the left half of the PMOS region and the left half of the NMOS region are covered by the N-Well layer, so that the right half of the PMOS region and the right half of the NMOS region are P-wells. The design rule limit shown in the figure is that the unit layout can be checked through the design rule after automatic splicing according to the minimum design rule and one half of the minimum rule provided by the wafer foundry. The embodiment is suitable for the left edge and the right edge of the IP module, and the inner side can be spliced with the standard units of the P substrate NMOS and the P substrate PMOS in the horizontal direction.
By the edge unit layout design method provided by the embodiment, the layout height of the edge unit is consistent with the height of the corresponding standard unit. Through horizontal and vertical mirror images, the inner sides of the edge units can be normally adjacent to corresponding standard units, so that P-well isolation in the whole module is realized, the design development flow of a standard unit library is optimized, and the rear end design efficiency of the digital circuit is improved.
The above embodiments are preferred examples of the present invention, and the present invention is not limited thereto, and any other modifications or equivalent substitutions made without departing from the technical aspects of the present invention are included in the scope of the present invention.

Claims (7)

1.一种标准单元库边缘单元的版图布局设计方法，其特征在于，其包括以下步骤：1. A layout design method for edge cells of a standard cell library, characterized in that it comprises the following steps: 步骤一，根据对应标准单元库的基本参数和流片厂家提供的设计规则文件中最小设计规则，确定边缘单元的基本参数；Step 1: Determine the basic parameters of the edge cell according to the basic parameters of the corresponding standard cell library and the minimum design rules in the design rule file provided by the wafer manufacturer; 步骤二，根据所述边缘单元的基本参数和版图设计规则，设计所述边缘单元，具体有六种边缘单元，分别是第一边缘单元、第二边缘单元、第三边缘单元、第四边缘单元、第五边缘单元、第六边缘单元；Step 2, designing the edge unit according to the basic parameters of the edge unit and the layout design rules, specifically there are six types of edge units, namely a first edge unit, a second edge unit, a third edge unit, a fourth edge unit, a fifth edge unit, and a sixth edge unit; 所述第一边缘单元的版图中，Deep N-Well覆盖整个边缘单元，PMOS区域被N-Well层覆盖，NMOS区域被P-Well层覆盖；In the layout of the first edge unit, the Deep N-Well covers the entire edge unit, the PMOS region is covered by the N-Well layer, and the NMOS region is covered by the P-Well layer; 所述第二边缘单元的版图中，Deep N-Well覆盖整个边缘单元，NMOS区域被N-Well层覆盖，PMOS区域被P-Well层覆盖；In the layout of the second edge unit, the Deep N-Well covers the entire edge unit, the NMOS region is covered by the N-Well layer, and the PMOS region is covered by the P-Well layer; 所述第三边缘单元的版图中，Deep N-Well覆盖整个边缘单元，PMOS区域和NMOS区域的左半部分被N-Well层覆盖，NMOS区域的右半部分为P-Well；In the layout of the third edge unit, the Deep N-Well covers the entire edge unit, the left half of the PMOS region and the NMOS region is covered by the N-Well layer, and the right half of the NMOS region is the P-Well; 所述第四边缘单元的版图中，Deep N-Well覆盖整个边缘单元，NMOS区域和PMOS区域的左半部分被N-Well层覆盖，PMOS区域的右半部分为P-Well；In the layout of the fourth edge unit, the Deep N-Well covers the entire edge unit, the NMOS region and the left half of the PMOS region are covered by the N-Well layer, and the right half of the PMOS region is the P-Well; 所述第五边缘单元的版图中，Deep N-Well覆盖整个边缘单元，PMOS区域和NMOS区域都被N-Well层覆盖；In the layout of the fifth edge unit, the Deep N-Well covers the entire edge unit, and both the PMOS region and the NMOS region are covered by the N-Well layer; 所述第六边缘单元的版图中，Deep N-Well覆盖整个边缘单元，PMOS区域的左半部分和NMOS区域的左半部分被N-Well层覆盖，PMOS区域的右半部分和NMOS区域的右半部分为P-Well；In the layout of the sixth edge unit, Deep N-Well covers the entire edge unit, the left half of the PMOS region and the left half of the NMOS region are covered by the N-Well layer, and the right half of the PMOS region and the right half of the NMOS region are P-Well; 步骤三，数字后端进行设计边缘单元的版图时，合理插入所述边缘单元于IP模块的外沿，从而实现P阱隔离。Step 3: When the digital backend designs the layout of the edge unit, the edge unit is reasonably inserted into the outer edge of the IP module to achieve P-well isolation. 2.如权利要求1所述的标准单元库边缘单元的版图布局设计方法，其特征在于，所述标准单元库的基本参数包括：第一单元高度、第一电源总线宽度、第一地总线宽度、第一Poly水平布线间距、第一P/N区域分界线、第一N阱边线；所述边缘单元的基本参数包括：第二单元高度、第二电源总线宽度、第二地总线宽度、第二Poly水平布线间距、第二P/N区域分界线、第二N阱边线。2. The layout design method of the edge cell of the standard cell library as described in claim 1 is characterized in that the basic parameters of the standard cell library include: a first cell height, a first power bus width, a first ground bus width, a first Poly horizontal wiring spacing, a first P/N region boundary, and a first N well edge; the basic parameters of the edge cell include: a second cell height, a second power bus width, a second ground bus width, a second Poly horizontal wiring spacing, a second P/N region boundary, and a second N well edge. 3.如权利要求2所述的标准单元库边缘单元的版图布局设计方法，其特征在于，所述第二单元高度与对应标准单元库内所有标准单元的相对高度相同。3. The layout design method for the edge cell of the standard cell library according to claim 2, wherein the second cell height is the same as the relative height of all standard cells in the corresponding standard cell library. 4.如权利要求2所述的标准单元库边缘单元的版图布局设计方法，其特征在于，所述第二电源总线宽度与对应标准单元库内所有标准单元的第一电源总线宽度相同，第二地总线宽度与对应标准单元库内所有单元的第一地总线宽度相同。4. The layout design method for the edge cell of the standard cell library as described in claim 2 is characterized in that the second power bus width is the same as the first power bus width of all standard cells in the corresponding standard cell library, and the second ground bus width is the same as the first ground bus width of all cells in the corresponding standard cell library. 5.如权利要求2所述的标准单元库边缘单元的版图布局设计方法，其特征在于，所述第二Poly水平布线间距为相邻两根Poly的中线距离，由工艺平台的设计规则确定。5. The layout design method for the edge cell of the standard cell library as described in claim 2, characterized in that the horizontal wiring spacing of the second Poly is the distance between the center lines of two adjacent Polys, which is determined by the design rules of the process platform. 6.如权利要求2所述的标准单元库边缘单元的版图布局设计方法，其特征在于，所述第二P/N区域分界线是边缘单元的PMOS区域和NMOS区域的分界线位置，第二P/N区域分界线的位置与对应标准单元库内所有标准单元的相对位置相同，所述相对位置为相对于原点的位置。6. The layout design method for the edge cell of the standard cell library as described in claim 2 is characterized in that the second P/N region dividing line is the boundary position of the PMOS region and the NMOS region of the edge cell, and the position of the second P/N region dividing line is the same as the relative position of all standard cells in the corresponding standard cell library, and the relative position is the position relative to the origin. 7.如权利要求2所述的标准单元库边缘单元的版图布局设计方法，其特征在于，所述第二N阱边线为相邻两根N阱边线的中线距离。7 . The layout design method for the edge cell of the standard cell library according to claim 2 , wherein the second N-well edge line is the distance between the center lines of two adjacent N-well edge lines.
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