CN114068584B

CN114068584B - Pixel array substrate

Info

Publication number: CN114068584B
Application number: CN202110745303.6A
Authority: CN
Inventors: 许倩雯; 郑圣谚; 林弘哲; 徐雅玲; 黄俊儒; 何昇儒; 廖乾煌; 锺岳宏; 李珉泽; 郭子维; 侯舜龄; 王奕筑; 陈品妏; 廖烝贤
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2020-08-03
Filing date: 2021-07-01
Publication date: 2024-11-19
Anticipated expiration: 2041-07-01
Also published as: CN119451226A; CN114068584A; CN215183965U

Abstract

A pixel array substrate comprises a plurality of data lines, a plurality of gate lines, a plurality of pixel structures, a plurality of patch cords and a common line. The plurality of data lines are arranged in a first direction. The plurality of gate lines are arranged in a second direction. The plurality of patch cords are electrically connected to the plurality of gate lines and arranged in a first direction. The first data line is provided with a first part which is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure. In a top view of the pixel array substrate, the active element of the first pixel structure has a first side and a second side opposite to each other, the first switching line is disposed on the first side of the active element of the first pixel structure, and the first portion of the first data line and the common line are disposed on the second side of the active element of the first pixel structure.

Description

Pixel array substrate

Technical Field

The invention relates to a pixel array substrate.

Background

With the development of display technologies, demands for display devices are not satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle, and display devices are expected to have elegant appearances. For example, it is also desirable that the bezel of the display device be narrow, even bezel-free.

In general, a display device includes a plurality of pixel structures disposed in a display area, a data driving circuit disposed under the display area, and a gate driving circuit disposed at a left side, a right side, or both sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit may be disposed below the display area. When the gate driving circuit is disposed at the lower side of the display area, the gate lines extending in the horizontal direction should be electrically connected to the gate driving circuit through the patch cord extending in the vertical direction. However, the patch cords are interposed between the pixel structures, and the voltage of the pixel electrode is easily affected by the signal variation of the patch cords, which is not beneficial to the display quality of the display device.

Disclosure of Invention

The invention provides a pixel array substrate with good characteristics.

The invention provides another pixel array substrate with good characteristics.

The pixel array substrate of an embodiment of the invention comprises a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures, a plurality of patch cords and a common line. The plurality of data lines are arranged on the substrate and are arranged in a first direction. The plurality of gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction. The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding grid line. The plurality of patch cords are disposed on the substrate, electrically connected to the plurality of gate lines, and arranged in a first direction. The common line is disposed on the substrate, wherein the plurality of data lines and the common line are arranged in a first direction. The plurality of pixel structures comprise first pixel structures, the plurality of data lines comprise first data lines electrically connected to the first pixel structures, and the plurality of patch cords comprise first patch cords. The first data line is provided with a first part, is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure. Each pixel structure has a first side and a second side opposite to each other. In a top view of the pixel array substrate, the first switching line is disposed on a first side of the active device of the first pixel structure, and the first portion of the first data line and the common line are disposed on a second side of the active device of the first pixel structure.

The pixel array substrate of an embodiment of the invention comprises a base, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of patch cords. The plurality of data lines are arranged on the substrate and are arranged in a first direction. The plurality of gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction. The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding grid line. The plurality of patch cords are disposed on the substrate, electrically connected to the plurality of gate lines, and arranged in a first direction. The plurality of patch cords includes a first patch cord. The plurality of pixel structures comprise a first pixel structure and a second pixel structure which are respectively arranged on two opposite sides of the first switching wire. The plurality of data lines comprise a first data line and a second data line which are respectively and electrically connected to the first pixel structure and the second pixel structure. The first data line is provided with a first part, is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure. The second data line is provided with a second part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure. In a top view of the pixel array substrate, a first portion of the first data line is disposed on a second side of the active device of the first pixel structure, and a first portion of the second data line is disposed on a first side of the active device of the second pixel structure.

In an embodiment of the invention, in a top view of the pixel array substrate, the first portion of the first data line and the first switching line have a first distance in a first direction, the first portion of the first data line and the common line have a second distance in the first direction, and the first distance is greater than the second distance.

In an embodiment of the invention, the plurality of pixel structures further includes a second pixel structure, and the first pixel structure is disposed adjacent to the second pixel structure and arranged in the first direction; the plurality of data lines further comprise second data lines electrically connected to the second pixel structures; the plurality of patch cords further comprises a second patch cord; the second data line is provided with a first part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure; in a top view of the pixel array substrate, the first portions of the common line and the second data line are disposed on a first side of the active element of the second pixel structure, and the second patch cord is disposed on a second side of the active element of the second pixel structure.

In an embodiment of the invention, in a top view of the pixel array substrate, the first portion of the second data line and the common line have a third distance in the first direction, the first portion of the second data line and the second patch line have a fourth distance in the first direction, and the fourth distance is greater than the third distance.

In an embodiment of the invention, the plurality of pixel structures further includes a third pixel structure, and the first pixel structure, the second pixel structure and the third pixel structure are sequentially arranged in the first direction; the plurality of data lines further comprise a third data line electrically connected to the third pixel structure; the plurality of patch cords further includes a third patch cord; the third data line is provided with a first part, is arranged outside the pixel electrode of the third pixel structure and is positioned beside the active element of the third pixel structure. In a top view of the pixel array substrate, the first portions of the second patch cord and the third data cord are arranged on a first side of the active element of the third pixel structure, and the third patch cord is arranged on a second side of the active element of the third pixel structure; or in the top view of the pixel array substrate, the second patch cord is arranged on the first side of the active element of the third pixel structure, and the first part of the third data cord and the third patch cord are arranged on the second side of the active element of the third pixel structure.

In an embodiment of the invention, the third pixel structure is used for displaying blue.

In an embodiment of the invention, the pixel array substrate further includes: a transparent conductive layer, wherein the data line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is arranged between the data line and the pixel electrode of the pixel structure. The transparent conductive layer is provided with a plurality of openings and is overlapped with the pixel electrode of the pixel structure.

The pixel array substrate of an embodiment of the invention comprises a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a transparent conductive layer. The plurality of data lines are arranged on the substrate and are arranged in a first direction. The plurality of gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction. The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding gate line. The data line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is arranged between the data line and the pixel electrode of the pixel structure. The transparent conductive layer is provided with a plurality of openings and is overlapped with the pixel electrode of the pixel structure.

In an embodiment of the invention, in a top view of the pixel array substrate, the plurality of openings of the transparent conductive layer are located at opposite sides of the data line.

In an embodiment of the invention, the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

In an embodiment of the invention, the pixel electrode of the pixel structure has a plurality of slits, and the slits overlap with a plurality of openings of the transparent conductive layer.

In an embodiment of the invention, in a top view of the pixel array substrate, the plurality of slits of the pixel electrode are disposed in a first range, the plurality of openings of the transparent conductive layer are disposed in a second range, the first range and the second range overlap, and an area of the second range is smaller than an area of the first range.

In an embodiment of the invention, the pixel electrode of the pixel structure has a plurality of first branch portions, the plurality of first branch portions are separated from each other to define a plurality of slits, the first branch portions have a first line width, and adjacent two of the plurality of first branch portions have a first pitch; the transparent conductive layer is provided with a plurality of second branch parts, the plurality of second branch parts are separated from each other to define a plurality of openings, the second branch parts are provided with a second line width, and two adjacent second branch parts are provided with a second interval; the sum of the second line width and the second pitch of the transparent conductive layer is greater than the sum of the first line width and the first pitch of the pixel electrode.

In an embodiment of the invention, the transparent conductive layer has a first entity portion overlapping with the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has edges defining a plurality of openings, and the edges of the first solid portion of the transparent conductive layer are located outside the data lines.

In an embodiment of the present invention, the plurality of pixel structures further includes a fourth pixel structure. The first pixel structure and the fourth pixel structure are respectively arranged on two opposite sides of the first switching wire. The plurality of data lines further includes a fourth data line electrically connected to the fourth pixel structure. The fourth data line is provided with a first part, is arranged outside the pixel electrode of the fourth pixel structure and is positioned beside the active element of the fourth pixel structure. In a top view of the pixel array substrate, a first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and a first portion of the fourth data line is disposed on the first side of the active device of the fourth pixel structure.

In an embodiment of the invention, the first pixel structure and the fourth pixel structure are respectively used for displaying red and blue.

In an embodiment of the invention, the plurality of pixel structures further includes a fifth pixel structure and a sixth pixel structure. The fourth pixel structure, the first pixel structure, the fifth pixel structure, and the sixth pixel structure are sequentially arranged in the first direction. The fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are respectively used for displaying blue, red, green and blue. The plurality of data lines further includes a fifth data line electrically connected to the fifth pixel structure. The fifth data line is provided with a first part, is arranged outside the pixel electrode of the fifth pixel structure and is positioned beside the active element of the fifth pixel structure. The plurality of data lines further includes a sixth data line electrically connected to the sixth pixel structure. The sixth data line is provided with a first part, is arranged outside the pixel electrode of the sixth pixel structure and is positioned beside the active element of the sixth pixel structure. In a top view of the pixel array substrate, a first portion of the fifth data line is disposed on the second side of the active device of the fifth pixel structure, and a first portion of the sixth data line is disposed on the first side of the active device of the sixth pixel structure.

In an embodiment of the present invention, the plurality of pixel structures further includes a fifth pixel structure. The fourth pixel structure, the first pixel structure and the fifth pixel structure are sequentially arranged in the first direction. The fourth pixel structure, the first pixel structure and the fifth pixel structure are respectively used for displaying blue, red and green. The plurality of data lines further includes a fifth data line electrically connected to the fifth pixel structure. The fifth data line is provided with a first part, is arranged outside the pixel electrode of the fifth pixel structure and is positioned beside the active element of the sixth pixel structure. In a top view of the pixel array substrate, a first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and a first portion of the fifth data line is disposed on the first side of the active device of the fifth pixel structure.

In an embodiment of the invention, in a top view of the pixel array substrate, an edge of the solid portion of the transparent conductive layer has a minimum distance from an edge of the data line, and the minimum distance is greater than or equal to 5 μm and less than or equal to 8 μm.

In an embodiment of the invention, the plurality of openings of the transparent conductive layer are arranged in a first direction.

In an embodiment of the invention, the plurality of openings of the transparent conductive layer are arranged in the second direction.

In an embodiment of the invention, the plurality of openings of the transparent conductive layer are arranged in a fourth direction, and the first direction, the second direction and the fourth direction are different from each other.

In an embodiment of the invention, the pixel electrode of the pixel structure has a plurality of slits, and the slits overlap with a plurality of openings of the transparent conductive layer; the plurality of slits are arranged in a fifth direction; the fourth direction is substantially the same as the fifth direction.

In an embodiment of the invention, the pixel electrode of the pixel structure has a plurality of slits, and the slits overlap with a plurality of openings of the transparent conductive layer; the plurality of slits are arranged in a fifth direction; the fourth direction and the fifth direction form an angle theta, and 0 DEG < theta is less than or equal to 90 deg.

In an embodiment of the invention, the transparent conductive layer has a plurality of second branch portions, which are interlaced with each other to form a plurality of openings.

Drawings

Fig. 1 is a schematic top view of a display device 10 according to an embodiment of the invention.

Fig. 2 is a schematic top view of an area of the pixel array substrate 100 according to an embodiment of the invention.

Fig. 3 is a schematic top view of an area of the pixel array substrate 100 according to an embodiment of the invention.

Fig. 4 is a schematic top view of an area of the pixel array substrate 100 according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional view of a display device 10 according to an embodiment of the invention.

Fig. 6 is a schematic top view of an area of the pixel array substrate 100A according to an embodiment of the invention.

Fig. 7 is a schematic top view of a region of the pixel array substrate 100B according to an embodiment of the invention.

Fig. 8 is a schematic top view of a region of the pixel array substrate 100B according to an embodiment of the invention.

Fig. 9 is a schematic top view of a region of the pixel array substrate 100B according to an embodiment of the invention.

Fig. 10 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention.

Fig. 11 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention.

Fig. 12 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention.

Fig. 13 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention.

Fig. 14 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention.

Fig. 15 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention.

Fig. 16 is a schematic top view of an area of the pixel array substrate 100E according to an embodiment of the invention.

Fig. 17 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention.

Fig. 18 is a schematic top view of a region of the pixel array substrate 100E according to an embodiment of the invention.

Fig. 19 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention.

Fig. 20 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention.

Fig. 21 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention.

Fig. 22 is a schematic top view of a region of the pixel array substrate 100G according to an embodiment of the invention.

Fig. 23 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention.

Fig. 24 is a schematic top view of a region of the pixel array substrate 100G according to an embodiment of the invention.

Fig. 25 is a schematic top view of a region of a pixel array substrate 100H according to an embodiment of the invention.

Fig. 26 is a schematic top view of a region of the pixel array substrate 100I according to an embodiment of the invention.

Fig. 27 is a schematic top view of a region of a pixel array substrate 100J according to an embodiment of the invention.

Reference numerals illustrate:

10: display device

100. 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J: pixel array substrate

110: Substrate

120: Pixel structure

120-1: First pixel structure

120-2: Second pixel structure

120-3: Third pixel structure

120-4: Fourth pixel structure

120-5: Fifth pixel structure

120-6: Sixth pixel structure

120-7: Seventh pixel structure

120-8: Eighth pixel structure

120-9: Ninth pixel structure

120-10: Tenth pixel structure

120-11: Eleventh pixel structure

120-12: Twelfth pixel structure

121: Active device

121A: source electrode

121B: drain electrode

121C: grid electrode

121D: semiconductor pattern

122: Pixel electrode

122A: a first trunk part

122B: a second trunk part

122C: a first branch part

122S, 122s-1, 122s-2, 122s-3, 122s-4: slit(s)

130. 140, 170: Insulating layer

140A: through hole

150: Transparent conductive layer

151: A first solid part

151E, DLe: edge of the sheet

152. 152-1, 152-2, 152-3, 152-4: An opening

153. 153C-1, 153C-2: a second branch part

160: Color filter pattern layer

200: Opposite substrate

210: Substrate

220: Common electrode

300: Display medium

CL: common line

CL': common electrode

CL' -1: at least one first part

CL' -2: at least one second part

D1: first distance

D2: second distance

D3: third distance

D4: fourth distance

DL: data line

DL1: first data line

DL2: second data line

DL3: third data line

DL4 fourth data line

DL5: fifth data line

DL6: sixth data line

DLa: first part

DLb: second part

D4: fourth direction

D5: in the fifth direction

GL: gate line

Gl: patch cord

Gl1: first transfer line

Gl2: second patch cord

Gl3: third patch cord

L1: first line width

L2: second line width

R: alignment region

S1: first distance of

S2: second distance

RG1: first range

RG2: second range

W: minimum distance

X: first direction

Y: second direction

And z: third direction of

Θ: angle of

I-I': line of cutting

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes both the values and average values within an acceptable deviation of the particular values as determined by one of ordinary skill in the art, taking into account the particular number of measurements and errors associated with the measurements in question (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the values, or within ±30%, ±20%, ±10%, ±5%. Further, as used herein, "about," "approximately," or "substantially" may be used to select a more acceptable range of deviations or standard deviations depending on the optical, etching, or other properties, and may not be used with one standard deviation for all properties.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 3 is a schematic top view of an area of the pixel array substrate 100 according to an embodiment of the invention. Fig. 3 omits the transparent conductive layer 150 of fig. 2.

Fig. 4 is a schematic top view of an area of the pixel array substrate 100 according to an embodiment of the invention. Fig. 4 omits the plurality of pixel electrodes 122 of fig. 2.

Fig. 5 is a schematic cross-sectional view of a display device 10 according to an embodiment of the invention. Fig. 5 corresponds to section line I-I' of fig. 2.

Referring to fig. 1,2 and 5, the display device 10 includes a pixel array substrate 100, an opposite substrate 200 opposite to the pixel array substrate 100, and a display medium 300 disposed between the pixel array substrate 100 and the opposite substrate 200. For example, in the present embodiment, the display medium 300 may be a liquid crystal. However, the present invention is not limited thereto, and in other embodiments, the display medium 300 may be a plurality of organic electroluminescent patterns, a plurality of micro light emitting diode elements, or other applicable materials.

The pixel array substrate 100 includes a base 110. The substrate 110 is used for carrying a plurality of components of the pixel array substrate 100. For example, in the present embodiment, the material of the substrate 110 may be glass. However, the invention is not limited thereto, and the substrate 110 may be made of quartz, organic polymer, or opaque/reflective material (e.g. wafer, ceramic, etc.), or other applicable materials according to other embodiments.

The pixel array substrate 100 includes a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate 110. The plurality of data lines DL are arranged in a first direction x, and the plurality of gate lines GL are arranged in a second direction y, wherein the first direction x is staggered with the second direction y. For example, in the present embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited thereto.

The data line DL and the gate line GL belong to different layers. For example, in the present embodiment, the gate line GL may selectively belong to the first metal layer, and the data line DL may selectively belong to the second metal layer, but the invention is not limited thereto.

In this embodiment, the data line DL and the gate line GL are made of metal materials based on the consideration of conductivity. However, the present invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the data line DL and the gate line GL, such as: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials and other conductive materials.

The pixel array substrate 100 further includes a plurality of pixel structures 120 disposed on the substrate 110. Each pixel structure 120 includes an active device 121 and a pixel electrode 122 electrically connected to the active device 121, and the active device 121 is electrically connected to a corresponding one of the data lines DL and a corresponding one of the gate lines GL.

For example, in the present embodiment, the active device 121 includes a thin film transistor, the thin film transistor includes a source electrode 121a, a drain electrode 121b, a gate electrode 121c and a semiconductor pattern 121d, the insulating layer 130 is sandwiched between the gate electrode 121c and the semiconductor pattern 121d, the source electrode 121a and the drain electrode 121b are respectively electrically connected to different two regions of the semiconductor pattern 121d, the source electrode 121a is electrically connected to a corresponding one of the data lines DL, the gate electrode 121c is electrically connected to a corresponding one of the gate lines GL, and the drain electrode 121b is electrically connected to the pixel electrode 122.

Referring to fig. 2 and 3, in the present embodiment, the pixel electrode 122 may optionally have a plurality of slits 122s to define at least one alignment region R of the pixel structure 120. For example, in the present embodiment, the pixel electrode 122 may optionally include a first trunk portion 122a, a second trunk portion 122b and a plurality of first branch portions 122c; the first trunk portion 122a and the second trunk portion 122b are staggered to divide a plurality of alignment areas R; in the same alignment region R, a plurality of first branch portions 122c extend in the same direction and are spaced apart from each other to define a plurality of slits 122s; however, the invention is not limited thereto.

In this embodiment, a sub-pixel region where the pixel electrode 122 is located may optionally include four alignment regions R. However, the present invention is not limited thereto, and in another embodiment, a sub-pixel region may also have other numbers (e.g., one, two, three or more than five) of alignment regions R. In addition, in another embodiment, the pixel electrode 122 may not have the slit 122s.

Referring to fig. 2 and 5, in the present embodiment, the pixel array substrate 100 further includes a common line CL disposed on the substrate 110, wherein the plurality of data lines DL and the common line CL are arranged in the first direction x. The common line CL may partially overlap the pixel electrode 122 to form a storage capacitor.

In the embodiment, the gate electrode 121c and the gate line GL may selectively belong to a first metal layer, the source electrode 121a, the drain electrode 121b, the data line DL and the common line CL may selectively belong to a second metal layer, the pixel array substrate 100 may further include an insulating layer 140 disposed on the second metal layer, and the pixel electrode 122 may be disposed on the insulating layer 140 and electrically connected to the drain electrode 121b of the thin film transistor through the through hole 140a of the insulating layer 140, but the invention is not limited thereto.

In this embodiment, the pixel electrode 122 is light-transmitting, and the material of the light-transmitting pixel electrode 122 may include metal oxide, for example: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stack of at least two of the foregoing. It should be noted that the pixel electrode 122 is not limited to be transparent in the present invention; in other embodiments, the pixel electrode 122 may also be reflective, or partially reflective and partially transmissive.

Referring to fig. 1 and 2, the pixel array substrate 100 further includes a plurality of patch cords gl disposed on the substrate 110 and arranged in a first direction x. The plurality of switching lines GL arranged in the first direction x are electrically connected to the plurality of gate lines GL arranged in the second direction y, and interposed between the plurality of pixel structures 120.

For example, in the present embodiment, the gate line GL may selectively belong to the first metal layer, and the patch line GL may selectively belong to the second metal layer. However, the invention is not limited thereto, and in other embodiments, the patch cord gl may also include a plurality of portions respectively belonging to the first metal layer and the second metal layer.

Referring to fig. 2, 3 and 4, the plurality of pixel structures 120 includes a first pixel structure 120-1, the plurality of data lines DL includes a first data line DL1 electrically connected to the first pixel structure 120-1, and the plurality of switching lines gl includes a first switching line gl1. The first data line DL1 has a first portion DLa disposed outside the pixel electrode 122 of the first pixel structure 120-1 and beside the active device 121 of the first pixel structure 120-1.

The active element 121 of each pixel structure 120 has opposite first (e.g., without limitation, left) and second (e.g., without limitation, right) sides. It should be noted that, in the top view of the pixel array substrate 100, the active device 121 of the first pixel structure 120-1 has a first side (e.g., without limitation, a left side) and a second side (e.g., without limitation, a right side), the first switching line gl1 is disposed on the first side (e.g., without limitation, the left side) of the active device 121 of the first pixel structure 120-1, and the first portion DLa of the first data line DL1 and the common line CL are disposed on the second side (e.g., without limitation, the right side) of the active device 121 of the first pixel structure 120-1. In other words, when the patch cord gl and the common cord CL are disposed on opposite sides of the pixel structure 120, a portion of the data line DL (i.e. the first portion DLa) bypassing the active device 121 is disposed closer to the common cord CL and further from the patch cord gl. Therefore, the coupling capacitance between the data line DL and the patch cord gl can be reduced, the influence of the signal variation of the patch cord gl on the potential of the pixel electrode 122 can be reduced, and the display quality can be improved.

Referring to fig. 2, in a top view of the pixel array substrate 100, the first portion DLa of the first data line DL1 and the first transfer line gl1 have a first distance D1 along the first direction x, the first portion DLa of the first data line DL1 and the common line CL have a second distance D2 along the first direction x, and the first distance D1 is greater than the second distance D2.

Referring to fig. 2, in the present embodiment, the plurality of pixel structures 120 further includes a second pixel structure 120-2, and the first pixel structure 120-1 and the second pixel structure 120-2 are disposed adjacent to each other and arranged in the first direction x; the plurality of data lines DL further includes a second data line DL2 electrically connected to the second pixel structure 120-2; the plurality of patch cords gl further includes a second patch cord gl2; the second data line DL2 has a first portion DLa disposed outside the pixel electrode 122 of the second pixel structure 120-2 and beside the active device 121 of the second pixel structure 120-2.

In the top view of the pixel array substrate 100, the active element 121 of the second pixel structure 120-2 has opposite first sides (e.g., without limitation: left side) and second sides (e.g., without limitation: right side), the first portions DLa of the common lines CL and the second data lines DL2 are disposed on the first sides (e.g., without limitation: left side) of the active element 121 of the second pixel structure 120-2, and the second patch lines gl2 are disposed on the second sides (e.g., without limitation: right side) of the active element 121 of the second pixel structure 120-2. In other words, when the common line CL and the patch line gl are disposed on opposite sides of the pixel structure 120, a portion of the data line DL (i.e., the first portion DLa) that bypasses the active device 121 is disposed closer to the common line CL and further from the patch line gl. Therefore, the coupling capacitance between the data line DL and the patch cord gl can be reduced, the influence of the signal variation of the patch cord gl on the potential of the pixel electrode 122 can be reduced, and the display quality can be improved.

In a top view of the pixel array substrate 100, the first portion DLa of the second data line DL2 and the common line CL have a third distance D3 in the first direction x, the first portion DLa of the second data line DL2 and the second switching line gl2 have a fourth distance D4 in the first direction x, and the fourth distance D4 is greater than the third distance D3.

Referring to fig. 2, in the present embodiment, the plurality of pixel structures 120 further includes a third pixel structure 120-3, and the first pixel structure 120-1, the second pixel structure 120-2 and the third pixel structure 120-3 are sequentially arranged in the first direction x; no other pixel structures 120 are located between the first pixel structure 120-1, the second pixel structure 120-2, and the third pixel structure 120-3; the plurality of data lines DL further includes a third data line DL3 electrically connected to the third pixel structure 120-3; the plurality of patch cords gl further includes a third patch cord gl3; the third data line DL3 has a first portion DLa disposed outside the pixel electrode 122 of the third pixel structure 120-3 and beside the active device 121 of the third pixel structure 120-3.

In a top view of the pixel array substrate 100, the active element 121 of the third pixel structure 120-3 has a first side (e.g., without limitation, left side) and a second side (e.g., without limitation, right side) opposite to each other, the first portions DLa of the second patch lines gl2 and the third data lines DL3 are disposed on the first side (e.g., without limitation, left side) of the active element 121 of the third pixel structure 120-3, and the third patch line gl3 is disposed on the second side (e.g., without limitation, right side) of the active element 121 of the third pixel structure 120-3. When the patch cords gl are disposed on opposite sides of the pixel structure 120, a portion (i.e., the first portion DLa) of the data line DL that bypasses the active device 121 may be disposed closer to one of the patch cords gl.

In the present embodiment, the third pixel structure 120-3 is used for displaying blue. In other words, the pixel structure 120 having the patch cord gl on two opposite sides is preferable for displaying blue. Therefore, the adverse effect of the patch cord gl on the display quality can be reduced. In addition, in the present embodiment, the first pixel structure 120-1 and the second pixel structure 120-2 are used for displaying red and green, respectively, but the invention is not limited thereto.

Referring to fig. 2,4 and 5, in the present embodiment, the pixel array substrate 100 further includes a transparent conductive layer 150, wherein the data line DL, the transparent conductive layer 150 and the pixel electrode 122 of the pixel structure 120 are stacked in a third direction z perpendicular to the substrate 110, and the transparent conductive layer 150 is disposed between the data line DL and the pixel electrode 122 of the pixel structure 120. In addition, in the present embodiment, the common line CL, the transparent conductive layer 150 and the pixel electrode 122 of the pixel structure 120 are stacked in the third direction z perpendicular to the substrate 110, and the transparent conductive layer 150 is disposed between the common line CL and the pixel electrode 122 of the pixel structure 120.

Briefly, in the present embodiment, the transparent conductive layer 150 is disposed between the film layer to which the pixel electrode 122 belongs and the second metal layer to create a shielding effect on the components (such as, but not limited to, the patch cord gl) of the second metal layer; accordingly, adverse effects of signals of members of the second metal layer (e.g., but not limited to, the transfer line gl) on the pixel electrode 122 can be reduced, thereby improving display quality.

In the present embodiment, the potential of the transparent conductive layer 150 and the potential of the common line CL can be substantially equal. In this embodiment, the opposite substrate 200 may optionally include a common electrode 220 (shown in fig. 5) disposed on the substrate 210 in addition to the substrate 210, the common electrode 220 is overlapped with the pixel electrodes 122 of the pixel structures 120, the display medium 300 is disposed between the common electrode 220 and the pixel electrodes 122, and a potential difference between the common electrode 220 and each pixel electrode 122 can be used to drive the display medium 300, so that the display device 10 can display a picture. In the embodiment, the potential of the transparent conductive layer 150 of the pixel array substrate 100 and the potential of the common electrode 220 of the opposite substrate 200 may be substantially equal, but the invention is not limited thereto.

In this embodiment, the pixel array substrate 100 may optionally further include a color filter pattern layer 160 (shown in fig. 5), wherein the color filter pattern layer 160 is disposed on the insulating layer 140, and the transparent conductive layer 150 is disposed on the color filter pattern layer 160; the pixel array substrate 100 further includes an insulating layer 170, the insulating layer 170 is disposed on the transparent conductive layer 150, and the pixel electrode 122 is disposed on the insulating layer 170.

Referring to fig. 2 and 4, it is noted that in the present embodiment, the transparent conductive layer 150 may have a plurality of openings 152, which overlap the pixel electrode 122 of the pixel structure 120. The plurality of openings 152 of the transparent conductive layer 150 is beneficial to reducing the interference of the transparent conductive layer 150 on the electric field formed by the pixel electrode 122, thereby increasing the liquid crystal efficiency and enhancing the transmittance of the display device 10.

In this embodiment, the transparent conductive layer 150 has a first solid portion 151 overlapping the data line DL; in a top view of the pixel array substrate 100, the first solid portion 151 of the transparent conductive layer 150 has an edge 151e defining a plurality of openings 152, and the edge 151e of the first solid portion 151 of the transparent conductive layer 150 is located outside the data line DL. In other words, although the transparent conductive layer 150 has the plurality of openings 152, the first solid portion 151 of the transparent conductive layer 150 well shields the second portion DLb of the data line DL overlapping the pixel electrode 122.

For example, in the top view of the pixel array substrate 100, the edge 151e of the first solid portion 151 of the transparent conductive layer 150 and the edge DLe of the data line DL have a minimum distance W, and the minimum distance W is greater than or equal to 5 μm and less than or equal to 8 μm, but the invention is not limited thereto.

Referring to fig. 2,3 and 4, in the top view of the pixel array substrate 100, the plurality of slits 122s of the pixel electrode 122 are disposed in the first region RG1, the plurality of openings 152 of the transparent conductive layer 150 are disposed in the second region RG2, the first region RG1 and the second region RG2 overlap, and the area of the second region RG2 is smaller than the area of the first region RG 1.

In the present embodiment, the pixel electrode 122 of the pixel structure 120 has a plurality of first branch portions 122c, the plurality of first branch portions 122c are spaced apart from each other to define a plurality of slits 122S, one first branch portion 122c has a first line width L1, and two adjacent first branch portions 122c have a first spacing S1; the transparent conductive layer 150 has a plurality of second branch portions 153, wherein the plurality of second branch portions 153 are spaced apart from each other to define a plurality of openings 152, one second branch portion 153 has a second line width L2, and two adjacent second branch portions 153 have a second spacing S2; the sum of the second line width L2 and the second space S2 of the transparent conductive layer 150 is greater than the sum of the first line width L1 and the first space S1 of the pixel electrode 122.

In the present embodiment, in a top view of the pixel array substrate 100, the plurality of openings 152 of the transparent conductive layer 150 are located at opposite sides of the data line DL. In the present embodiment, the plurality of slits 122s of the pixel electrode 122 include a plurality of slits 122s-1, a plurality of slits 122s-2, a plurality of slits 122s-3 and a plurality of slits 122s-4, which are respectively disposed in a plurality of alignment areas R defined by the first trunk portion 122a and the second trunk portion 122b of the pixel electrode 122; the plurality of openings 152 of the transparent conductive layer 150 may include a plurality of openings 152-1, a plurality of openings 152-2, a plurality of openings 152-3, and a plurality of openings 152-4, which are respectively overlapped with the plurality of slits 122s-1, the plurality of slits 122s-2, the plurality of slits 122s-3, and the plurality of slits 122s-4 of the pixel electrode 122.

In the present embodiment, the plurality of openings 152-1, 152-2, 152-3 or 152-4 of the transparent conductive layer 150 may be arranged in the first direction x. In the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 may extend in the second direction y. In other words, in the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 may be straight openings. However, the present invention is not limited thereto, and in other embodiments, the plurality of openings 152 may be shaped and/or arranged in other ways, as will be illustrated with reference to the accompanying drawings.

It should be noted that the following embodiments use the element numbers and part of the content of the foregoing embodiments, where the same numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted. Reference is made to the foregoing embodiments for an explanation of omitted parts, which will not be repeated.

The pixel array substrate 100A of fig. 6 is similar to the pixel array substrate 100 of fig. 2, and the difference between them is that: in the embodiment of FIG. 2, the first portion DLa of the third data line DL3 is disposed on a first side (e.g., but not limited to, the left side) of the active device 121 of the third pixel structure 120-3; in the embodiment of fig. 6, however, the first portion DLa of the third data line DL3 is disposed on the second side (e.g., without limitation, the right side) of the active element 121 of the third pixel structure 120-3.

Fig. 8 is a schematic top view of a region of the pixel array substrate 100B according to an embodiment of the invention. Fig. 8 omits the transparent conductive layer 150 of fig. 7.

Fig. 9 is a schematic top view of a region of the pixel array substrate 100B according to an embodiment of the invention. Fig. 9 omits the pixel electrode 122 of fig. 7.

The pixel array substrate 100B of fig. 7 to 9 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference between them is that: the openings 152 of the transparent conductive layers 150 are different.

Referring to fig. 7 to 9, in particular, in the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 are arranged in the second direction y. Each opening 152 of the transparent conductive layer 150 may extend in the first direction x. In other words, in the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 may be a plurality of lateral openings.

Fig. 11 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention. Fig. 11 omits the transparent conductive layer 150 of fig. 10.

Fig. 12 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention. Fig. 12 omits the pixel electrode 122 of fig. 10.

The pixel array substrate 100C of fig. 10 to 12 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference between them is that: the openings 152 of the transparent conductive layers 150 are different.

Referring to fig. 10 to 12, in the embodiment, the transparent conductive layer 150 has a plurality of second branch portions 153C-1 and 153C-2, which are interlaced with each other to form a plurality of openings 152 (shown in fig. 12). Further, in the present embodiment, the plurality of second branch portions 153C-1, 153C-2 may include a plurality of second branch portions 153C-1 and a plurality of second branch portions 153C-2 that are staggered with each other, wherein the plurality of second branch portions 153C-1 may be selectively parallel to the second portion DLb of the data line DL, and the plurality of second branch portions 153C-1 may be selectively perpendicular to the second portion DLb of the data line DL.

Fig. 14 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention. Fig. 14 omits the transparent conductive layer 150 of fig. 13.

Fig. 15 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention. Fig. 15 omits the pixel electrode 122 of fig. 13.

The pixel array substrate 100D of fig. 13 to 15 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference between them is that: the openings 152 of the transparent conductive layers 150 are different.

Referring to fig. 13 to 15, in the embodiment, a plurality of data lines DL are arranged in a first direction x, a plurality of gate lines GL are arranged in a second direction y, a plurality of openings 152 of a transparent conductive layer 150 are arranged in a fourth direction d4, and the first direction x, the second direction y, and the fourth direction d4 are different from each other.

Further, in the present embodiment, the pixel electrode 122 of the pixel structure 120 has a plurality of slits 122s, the plurality of slits 122s of the pixel electrode 122 are overlapped with the plurality of openings 152 of the transparent conductive layer 150, the plurality of slits 122s of the pixel electrode 122 are arranged in the fifth direction d5, the plurality of openings 152 of the transparent conductive layer 150 are arranged in the fourth direction d4, and the fourth direction d4 is substantially the same as the fifth direction d 5.

Fig. 17 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention. Fig. 17 omits the transparent conductive layer 150 of fig. 16.

Fig. 18 is a schematic top view of a region of the pixel array substrate 100E according to an embodiment of the invention. Fig. 18 omits the pixel electrode 122 of fig. 16.

The pixel array substrate 100E of fig. 16 to 18 is similar to the pixel array substrate 100D of fig. 13 to 15, and the main difference between them is that: the openings 152 of the transparent conductive layers 150 are different.

Referring to fig. 16 to 18, in the present embodiment, the plurality of slits 122s of the pixel electrode 122 are arranged in the fifth direction d5, the plurality of openings 152 of the transparent conductive layer 150 are arranged in the fourth direction d4, and the fourth direction d4 and the fifth direction d5 form an angle θ therebetween, and 0 ° < θ+.ltoreq.90°.

Fig. 20 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention. Fig. 20 omits the transparent conductive layer 150 of fig. 19.

Fig. 21 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention. Fig. 21 omits the pixel electrode 122 of fig. 19.

The pixel array substrate 100F of fig. 19 to 21 is similar to the pixel array substrate 100 of fig. 10 to 12, and the main difference between them is that: the openings 152 of the transparent conductive layers 150 are different.

Referring to fig. 19 to 21, similarly, in the present embodiment, the transparent conductive layer 150 has a plurality of second branch portions 153C-1, 153C-2 (labeled in fig. 21) that are interlaced with each other to form a plurality of openings 152; the plurality of second branch portions 153C-1, 153C-2 of the transparent conductive layer 150 may include a plurality of second branch portions 153C-1 and a plurality of second branch portions 153C-2 that are staggered with each other. Unlike the embodiment of fig. 10 to 12, in the present embodiment, the plurality of second branch portions 153C-1 are not parallel nor perpendicular to the second portions DLb of the data lines DL, and the plurality of second branch portions 153C-1 are not parallel nor perpendicular to the second portions DLb of the data lines DL. In short, in the present embodiment, the plurality of second branch portions 153C-1, 153C-2 of the transparent conductive layer 150 may be interwoven into a mesh pattern disposed obliquely.

Fig. 23 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention. Fig. 23 omits the transparent conductive layer 150 of fig. 22.

Fig. 24 is a schematic top view of a region of the pixel array substrate 100G according to an embodiment of the invention. Fig. 24 omits the pixel electrode 122 of fig. 22.

The pixel array substrate 100G of fig. 22 to 24 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference between them is that: the openings 152 of the transparent conductive layers 150 are different.

Referring to fig. 22 to 24, in the present embodiment, the transparent conductive layer 150 does not have the opening 152 of the pixel array substrate 100, and the entity of the transparent conductive layer 150 may overlap the pixel electrode 122.

Fig. 25 is a schematic top view of a region of a pixel array substrate 100H according to an embodiment of the invention. The pixel array substrate 100H of fig. 25 is similar to the pixel array substrate 100 of fig. 2, and the following description is omitted for the major differences, and please refer to the above description for the same or similar points.

Referring to fig. 25, in the present embodiment, the plurality of pixel structures 120 further includes a fourth pixel structure 120-4; the first pixel structure 120-1 and the fourth pixel structure 120-4 are respectively disposed at two opposite sides of the first converting line gl 1; the plurality of data lines DL further includes a fourth data line DL4 electrically connected to the fourth pixel structure 120-4; the fourth data line DL4 has a first portion DLa disposed outside the pixel electrode 122 of the fourth pixel structure 120-4 and beside the active device 121 of the fourth pixel structure 120-4. In particular, in the top view of the pixel array substrate 100H, the first portion DLa of the first data line DL1 is disposed on the second side (e.g., without limitation, right side) of the active device 121 of the first pixel structure 120-1, and the first portion DLa of the fourth data line DL4 is disposed on the first side (e.g., without limitation, right side) of the active device 121 of the fourth pixel structure 120-4. That is, in the present embodiment, two pixel structures 120 are adjacent to the same patch cord gl and are respectively located at two opposite sides of the same patch cord gl, and two first portions DLa of two data lines DL respectively electrically connected to the two pixel structures 120 are respectively disposed at positions far away from the patch cord gl.

Referring to fig. 25, in the present embodiment, the first pixel structure 120-1 and the fourth pixel structure 120-4 are respectively used for displaying red and blue. That is, in the top view of the pixel array substrate 100, a transfer line gl is disposed between the pixel structures 120 for displaying red and blue colors, respectively.

Referring to fig. 25, in the present embodiment, the plurality of pixel structures 120 further includes a fifth pixel structure 120-5 and a sixth pixel structure 120-6, a seventh pixel structure 120-7 and an eighth pixel structure 120-8. The seventh pixel structure 120-7, the eighth pixel structure 120-8, the fourth pixel structure 120-4, the first pixel structure 120-1, the fifth pixel structure 120-5, and the sixth pixel structure 120-6 are sequentially arranged in the first direction x. The seventh pixel structure 120-7, the eighth pixel structure 120-8, the fourth pixel structure 120-4, the first pixel structure 120-1, the fifth pixel structure 120-5 and the sixth pixel structure 120-6 are respectively used for displaying red, green, blue, red, green and blue. The plurality of data lines DL further includes a fifth data line DL5 electrically connected to the fifth pixel structure 120-5. The fifth data line DL5 has a first portion DLa disposed outside the pixel electrode 122 of the fifth pixel structure 120-5 and beside the active device 121 of the fifth pixel structure 120-5. The plurality of data lines DL further includes a sixth data line DL6 electrically connected to the sixth pixel structure 120-6. The sixth data line DL6 has a first portion DLa disposed outside the pixel electrode 122 of the sixth pixel structure 120-6 and beside the active device 121 of the sixth pixel structure 120-6.

In particular, in the top view of the pixel array substrate 100H, the first portion DLa of the fifth data line DL5 is disposed on the second side (e.g., without limitation, the right side) of the active device 121 of the fifth pixel structure 120-5, and the first portion DLa of the sixth data line DL6 is disposed on the first side (e.g., without limitation, the left side) of the active device 121 of the sixth pixel structure 120-6. That is, the two first portions DLa electrically connected to the two data lines DL of the two pixel structures 120 for displaying green and blue are disposed adjacently.

Fig. 26 is a schematic top view of a region of the pixel array substrate 100I according to an embodiment of the invention. The pixel array substrate 100I of fig. 26 is similar to the pixel array substrate 100H of fig. 25, and the difference between them is that: in the top view of the pixel array substrate 100I of fig. 26, the first portion DLa of the first data line DL1 is disposed on the second side (e.g., without limitation, right side) of the active element 121 of the first pixel structure 120-1, and the first portion DLa of the fifth data line DL5 is disposed on the first side (e.g., without limitation, left side) of the active element 121 of the fifth pixel structure 120-5. That is, in the embodiment of fig. 26, two first portions DLa electrically connected to two data lines DL of two pixel structures 120 for displaying red and green are disposed adjacently.

Fig. 27 is a schematic top view of a region of a pixel array substrate 100J according to an embodiment of the invention. The pixel array substrate 100J of fig. 27 is similar to the pixel array substrate 100 of fig. 2, and the following description is omitted for the major differences, and please refer to the above description for the same or similar points.

Referring to fig. 27, in the present embodiment, the first pixel structure 120-1 and the second pixel structure 120-2 are respectively disposed on opposite sides of the first switching line gl 1. The plurality of data lines DL include a first data line DL1 and a second data line DL2 electrically connected to the first pixel structure 120-1 and the second pixel structure 120-2, respectively. The first data line DL1 has a first portion DLa disposed outside the pixel electrode 122 of the first pixel structure 120-1 and beside the active device 121 of the first pixel structure 120-1. The second data line DL2 has a first portion DLa disposed outside the pixel electrode 122 of the second pixel structure 120-2 and beside the active device 121 of the second pixel structure 120-2.

In particular, in the top view of the pixel array substrate 100J, the first transfer line gl1 is disposed on a first side (e.g., without limitation, left side) of the active element 121 of the first pixel structure 120-1, the first portion DLa of the first data line DL1 is disposed on a second side (e.g., without limitation, right side) of the active element 121 of the first pixel structure 120-1, the first transfer line gl1 is disposed on a second side (e.g., without limitation, right side) of the active element 121 of the second pixel structure 120-2, and the first portion DLa of the second data line DL2 is disposed on a first side (e.g., without limitation, left side) of the active element 121 of the second pixel structure 120-2. That is, in the present embodiment, two pixel structures 120 are adjacent to the same patch cord g1 and are respectively located at opposite sides of the same patch cord g1, and two first portions DLa of two data lines DL respectively electrically connected to the two pixel structures 120 are both disposed at positions far from the patch cord gl.

Referring to fig. 27, in the present embodiment, the plurality of pixel structures 120 further includes a ninth pixel structure 120-9, a tenth pixel structure 120-10, an eleventh pixel structure 120-11, and a twelfth pixel structure 120-12. The eleventh pixel structure 120-11, the twelfth pixel structure 120-12, the second pixel structure 120-2, the first pixel structure 120-1, the ninth pixel structure 120-9, and the tenth pixel structure 120-10 are sequentially arranged in the first direction x. The eleventh pixel structure 120-11, the twelfth pixel structure 120-12, the second pixel structure 120-2, the first pixel structure 120-1, the ninth pixel structure 120-9 and the tenth pixel structure 120-10 can be used for displaying red, green, blue, red, green and blue, respectively.

In addition, the pixel array substrate 100J of fig. 27 does not include the common line CL of the pixel array substrate 100 of fig. 2, but includes the common electrode CL'. Referring to fig. 27, in the present embodiment, the common electrode CL 'includes at least one first portion CL' -1, the at least one first portion CL '-1 of the common electrode CL' and the gate line GL are arranged in the second direction y, and the at least one first portion CL '-1 of the common electrode CL' and the pixel electrode 122 are partially overlapped. In this embodiment, the common electrode CL 'further includes at least one second portion CL' -2, the at least one second portion CL '-2 of the common electrode CL' and the data line DL are arranged in the first direction x, and the at least one second portion CL '-2 of the common electrode CL' and the pixel electrode 122 are partially overlapped. Furthermore, the pixel array substrate 100J of fig. 27 may not include the transparent conductive layer 150 of the pixel array substrate 100 of fig. 2.

Claims

1. A pixel array substrate, comprising:

a substrate;

A plurality of data lines arranged on the substrate and arranged in a first direction;

a plurality of gate lines disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction;

The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding grid line;

The plurality of patch cords are arranged on the substrate, are electrically connected to the gate lines and are arranged in the first direction; and

A common line disposed on the substrate, wherein the data lines and the common line are arranged in the first direction;

The pixel structures comprise a first pixel structure, the data lines comprise a first data line electrically connected to the first pixel structure, and the patch cords comprise a first patch cord;

the first data line is provided with a first part which is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure;

Each of the pixel structures has a first side and a second side opposite to each other;

In a top view of the pixel array substrate, the first switching line is disposed on the first side of the active device of the first pixel structure, and the first portion of the first data line and the common line are disposed on the second side of the active device of the first pixel structure.

2. The pixel array substrate of claim 1, wherein in a top view of the pixel array substrate, the first portion of the first data line and the first transfer line have a first distance in the first direction, the first portion of the first data line and the common line have a second distance in the first direction, and the first distance is greater than the second distance.

3. The pixel array substrate of claim 1, wherein the pixel structures further comprise a second pixel structure, the first pixel structure is disposed adjacent to the second pixel structure and aligned in the first direction; the data lines further comprise a second data line electrically connected to the second pixel structure; the patch cords also comprise a second patch cord; the second data line is provided with a first part which is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure; in a top view of the pixel array substrate, the first portions of the common line and the second data line are disposed on the first side of the active device of the second pixel structure, and the second patch cord is disposed on the second side of the active device of the second pixel structure.

4. The pixel array substrate of claim 3, wherein in a top view of the pixel array substrate, the first portion of the second data line and the common line have a third distance in the first direction, the first portion of the second data line and the second patch line have a fourth distance in the first direction, and the fourth distance is greater than the third distance.

5. The pixel array substrate of claim 3, wherein the pixel structures further comprise a third pixel structure, the first pixel structure, the second pixel structure and the third pixel structure are sequentially arranged in the first direction; the data lines further comprise a third data line electrically connected to the third pixel structure; the patch cords also comprise a third patch cord; the third data line is provided with a first part which is arranged outside the pixel electrode of the third pixel structure and is positioned beside the active element of the third pixel structure;

in a top view of the pixel array substrate, the first portions of the second patch cord and the third data cord are disposed on the first side of the active device of the third pixel structure, and the third patch cord is disposed on the second side of the active device of the third pixel structure;

or in the top view of the pixel array substrate, the second patch cord is disposed on the first side of the active device of the third pixel structure, and the first portion of the third data line and the third patch cord are disposed on the second side of the active device of the third pixel structure.

6. The pixel array substrate of claim 1, further comprising:

A transparent conductive layer, wherein a data line, the transparent conductive layer and a pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the data line and the pixel electrode of the pixel structure;

The transparent conductive layer is provided with a plurality of openings and is overlapped with the pixel electrode of the pixel structure.

7. The pixel array substrate of claim 6, wherein the openings of the transparent conductive layer are located at opposite sides of the data line in a top view of the pixel array substrate.

8. The pixel array substrate of claim 6, wherein the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in the third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

9. The pixel array substrate of claim 6, wherein said pixel electrode of said pixel structure has a plurality of slits overlapping said openings of said transparent conductive layer.

10. The pixel array substrate of claim 9, wherein in a top view of the pixel array substrate, the slits of the pixel electrode are disposed in a first range, the openings of the transparent conductive layer are disposed in a second range, the first range and the second range overlap, and an area of the second range is smaller than an area of the first range.

11. The pixel array substrate of claim 9, wherein the pixel electrode of the pixel structure has a plurality of first branch portions, the first branch portions are spaced apart from each other to define the slits, one of the first branch portions has a first line width, and two adjacent first branch portions have a first pitch; the transparent conductive layer is provided with a plurality of second branch parts, the second branch parts are separated from each other to define the openings, one second branch part is provided with a second line width, and two adjacent second branch parts are provided with a second interval; the sum of the second line width and the second pitch of the transparent conductive layer is greater than the sum of the first line width and the first pitch of the pixel electrode.

12. The pixel array substrate of claim 6, wherein said transparent conductive layer has a first solid portion overlapping said data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining the openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line.

13. The pixel array substrate of claim 1, wherein the pixel structures further comprise a fourth pixel structure; the first pixel structure and the fourth pixel structure are respectively arranged on two opposite sides of the first switching wire; the data lines further comprise a fourth data line electrically connected to the fourth pixel structure; the fourth data line is provided with a first part which is arranged outside the pixel electrode of the fourth pixel structure and is positioned beside the active element of the fourth pixel structure; in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fourth data line is disposed on the first side of the active device of the fourth pixel structure.

14. The pixel array substrate of claim 13, wherein the first pixel structure and the fourth pixel structure are respectively used for displaying red and blue.

15. The pixel array substrate of claim 13, wherein the pixel structures further comprise a fifth pixel structure and a sixth pixel structure, the fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure being sequentially arranged in the first direction; the fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are respectively used for displaying blue, red, green and blue; the data lines further comprise a fifth data line electrically connected to the fifth pixel structure; the fifth data line is provided with a first part which is arranged outside the pixel electrode of the fifth pixel structure and is positioned beside the active element of the fifth pixel structure; the data lines further include a sixth data line electrically connected to the sixth pixel structure; the sixth data line is provided with a first part which is arranged outside the pixel electrode of the sixth pixel structure and is positioned beside the active element of the sixth pixel structure; in a top view of the pixel array substrate, the first portion of the fifth data line is disposed on the second side of the active device of the fifth pixel structure, and the first portion of the sixth data line is disposed on the first side of the active device of the sixth pixel structure.

16. The pixel array substrate of claim 13, wherein the pixel structures further comprise a fifth pixel structure, a sixth pixel structure, the fourth pixel structure, the first pixel structure and the fifth pixel structure being sequentially arranged in the first direction; the fourth pixel structure, the first pixel structure and the fifth pixel structure are respectively used for displaying blue, red and green; the data lines further comprise a fifth data line electrically connected to the fifth pixel structure; the fifth data line is provided with a first part which is arranged outside the pixel electrode of the fifth pixel structure and is positioned beside the active element of the sixth pixel structure; in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fifth data line is disposed on the first side of the active device of the fifth pixel structure.

17. A pixel array substrate, comprising:

a substrate;

The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding grid line; and

The plurality of patch cords are arranged on the substrate, are electrically connected to the gate lines and are arranged in the first direction;

The patch cords comprise a first patch cord; the pixel structures comprise a first pixel structure and a second pixel structure which are respectively arranged on two opposite sides of the first switching wire; the data lines comprise a first data line and a second data line which are respectively and electrically connected to the first pixel structure and the second pixel structure; the first data line is provided with a first part which is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure; the second data line is provided with a second part which is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure;

in the top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the second data line is disposed on the first side of the active device of the second pixel structure,

The first side is a side of the second pixel structure away from the first switching line, and the second side is a side of the first pixel structure away from the first switching line.