CN114076881A

CN114076881A - Semiconductor device failure analysis method, apparatus, equipment and storage medium

Info

Publication number: CN114076881A
Application number: CN202010826866.3A
Authority: CN
Inventors: 蔡小龙
Original assignee: ZTE Corp; Xidian University
Current assignee: ZTE Corp; Xidian University
Priority date: 2020-08-17
Filing date: 2020-08-17
Publication date: 2022-02-22

Abstract

According to the semiconductor device failure analysis method, the semiconductor device failure analysis device, the semiconductor device failure analysis equipment and the semiconductor device failure analysis storage medium, target detection parameters of a normal semiconductor device are obtained through physical detection, the target detection parameters comprise detection parameters of failure point areas on the failure semiconductor device corresponding to the normal semiconductor device, and the target detection parameters comprise surface detection parameters of the failure point areas, element concentration detection parameters of the failure point areas and section detection parameters of the failure point areas; and then, the obtained target detection parameters are input as input parameters of a preset simulation algorithm, and the preset simulation algorithm is combined with the predicted failure result, so that the failure reason of the failed semiconductor device is obtained. Namely, the embodiment of the invention realizes the reverse analysis of the failure reason of the failed semiconductor device, takes the real failed semiconductor device as a direct analysis object, and has comprehensive and accurate analysis result.

Description

Semiconductor device failure analysis method, device, equipment and storage medium

Technical Field

The embodiment of the invention relates to the field of semiconductor device failure analysis, in particular to a semiconductor device failure analysis method, a semiconductor device failure analysis device, semiconductor device failure analysis equipment and a storage medium.

Background

As a typical third-generation semiconductor, a GaN material has many advantages such as a large forbidden band width, a high electron mobility, a good thermal conductivity, and a strong radiation resistance. By virtue of good physicochemical characteristics, a semiconductor device (such as a High Electron Mobility Transistor (HEMT)) made of a GaN material has lower on-resistance, higher operating frequency, smaller module size and higher energy density and breakdown voltage, and is widely applied to High-voltage and High-frequency fields such as a transfer switch, radio frequency communication and rapid charging equipment. With the progress of material growth and device preparation process level, the performance of GaN semiconductor devices is continuously improved, but the problem of device failure restricts the further expansion of the commercial application scale. In a high-power and high-frequency application scene, a certain proportion of failure cases are generated in the actual research, development, production and external field stages of the GaN semiconductor device, and the active area of the failure device can be seriously burnt, so that the failure root cause of the device is difficult to determine. In order to improve the reliability of the GaN semiconductor device and prolong the service life of the device, the analysis of a typical failure sample is crucial to determining the failure root cause.

In the related art, failure analysis of a semiconductor device mainly focuses on forward analysis of the device, that is, changes of reliability and performance stability of the device with time are observed through electrical testing means under extreme environments such as high temperature and high pressure, and the testing and analyzing means aiming at the electrical performance cannot be applied to a GaN semiconductor device which is burnt out and fails. Therefore, how to analyze the failure reason of the failed GaN semiconductor device so as to obtain a more accurate analysis result is a technical problem which needs to be solved urgently at present.

Disclosure of Invention

The embodiment of the invention mainly provides a semiconductor device failure analysis method, wherein the semiconductor device is made of gallium nitride materials, and the semiconductor device failure analysis method comprises the following steps:

acquiring target detection parameters of a normal semiconductor device through physical detection, wherein the target detection parameters comprise detection parameters of a failure point area on a failure semiconductor device corresponding to the normal semiconductor device, and the target detection parameters comprise: surface detection parameters of the failure point region, element concentration detection parameters of the failure point region and section detection parameters of the failure point region; the normal semiconductor device and the failure semiconductor device are the same device;

and inputting the target detection parameters as input parameters of a preset simulation algorithm, and combining the preset simulation algorithm with a predicted failure result to obtain the failure reason of the failed semiconductor device.

In order to solve the above technical problem, an embodiment of the present invention further provides a semiconductor device failure analysis apparatus, including:

the acquisition module acquires target detection parameters of a normal semiconductor device through physical detection, wherein the target detection parameters comprise detection parameters of a failure point area on a failure semiconductor device corresponding to the normal semiconductor device, and the acquisition module comprises: surface detection parameters of the failure point region, element concentration detection parameters of the failure point region and section detection parameters of the failure point region; the normal semiconductor device and the failure semiconductor device are the same device;

and the processing module is used for inputting the target detection parameters as input parameters of a preset simulation algorithm, and obtaining the failure reason of the failed semiconductor device by combining the preset simulation algorithm with the predicted failure result.

In order to solve the above technical problem, an embodiment of the present invention further provides a semiconductor device failure analysis apparatus, including a processor, a memory, and a communication bus connecting the processor and the memory;

the memory stores a computer program executable by the processor to implement the steps of the semiconductor device failure analysis method as described above.

To solve the technical problem, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which is executable by a processor to implement the steps of the semiconductor device failure analysis method as described above.

Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a schematic flow chart of a semiconductor device failure analysis method according to an embodiment of the present invention;

fig. 2 is a schematic view of a surface detection parameter obtaining process according to an embodiment of the present invention;

FIG. 3 is a schematic view of a light-emitting point according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a failure point region of a semiconductor device according to a first embodiment of the present invention;

fig. 5 is a schematic view illustrating a process of obtaining an element concentration detection parameter according to an embodiment of the present invention;

fig. 6 is a schematic view illustrating a process of acquiring profile inspection parameters according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a layer structure provided in the first embodiment of the present invention;

fig. 8 is a schematic view of another cross-sectional inspection parameter obtaining process according to an embodiment of the present invention;

FIG. 9 is a schematic view of a sample detection parameter obtaining process according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a semiconductor device failure analysis apparatus according to a second embodiment of the present invention;

fig. 11 is a schematic flow chart of a semiconductor device failure analysis method according to a second embodiment of the present invention;

FIG. 12 is a schematic flow chart of a sample process for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 13 is a schematic diagram of a layer structure provided in the second embodiment of the present invention;

fig. 14 is a schematic structural diagram of a semiconductor device failure analysis apparatus according to a third embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The first embodiment is as follows:

the following detailed description of specific embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The method aims at the problem that the failure analysis of the semiconductor device in the related technology is mainly focused on the forward analysis of the device and cannot be applied to the burning out of the failed GaN semiconductor device. The embodiment provides a new semiconductor device failure analysis method, which includes the steps that target detection parameters of a normal semiconductor device are obtained through physical detection, wherein the target detection parameters comprise detection parameters of failure point areas on the failure semiconductor device corresponding to the normal semiconductor device; and then, the obtained target detection parameters are input as input parameters of a preset simulation algorithm, and the preset simulation algorithm is combined with the predicted failure result, so that the failure reason of the failed semiconductor device is obtained. Namely, the embodiment of the invention realizes the reverse analysis of the failure reason of the failed semiconductor device, takes the real failed semiconductor device as a direct analysis object, and has comprehensive and accurate analysis result.

It should be understood that the method for analyzing the failure of the semiconductor device provided by the present embodiment is applicable to various semiconductor devices made based on gallium nitride materials, such as, but not limited to, high electron mobility transistors HEMTs made of GaN materials.

For ease of understanding, the present embodiment will now exemplarily describe a semiconductor device failure analysis method.

Referring to fig. 1, the semiconductor device failure analysis method includes, but is not limited to:

s101: and acquiring target detection parameters of the normal semiconductor device through physical detection.

In this embodiment, the normal semiconductor device refers to a semiconductor device which can normally operate without failure. In the embodiment, the target detection parameters of the normal semiconductor device can be directly obtained by physical detection, the implementation mode is simple and efficient, and the detected data is more accurate and reliable.

In this embodiment, the target detection parameters of the normal semiconductor device may include various detection parameters that can be used to analyze the failure cause of the failed semiconductor device, and may include, but are not limited to, detection parameters of a failure point region on the failed semiconductor device corresponding to the normal semiconductor device, which may include, but are not limited to: and the normal semiconductor device corresponds to the surface detection parameters, the element concentration detection parameters and the section detection parameters of the failure point area on the failure semiconductor device. In this embodiment, the normal semiconductor device and the failed semiconductor device are the same device, that is, the material, specification, and structure of the normal semiconductor device and the failed semiconductor device are completely the same.

S102: and inputting the obtained target detection parameters as input parameters of a preset simulation algorithm, and combining the preset simulation algorithm with the predicted failure result to obtain the failure reason of the failed semiconductor device.

The predicted failure result in this embodiment may include, but is not limited to, a failure result obtained by analyzing a typical failure sample, and may also be a failure result obtained by analyzing and predicting an evaluation detection parameter based on a failure point region on a failure semiconductor device. In one example, evaluating detection parameters may include, but is not limited to: and at least one of a surface detection parameter of the failure point region and a profile detection parameter of the failure point region on the failed semiconductor device.

In this embodiment, the target detection parameter may be input as an input parameter of a preset simulation algorithm to perform simulation, the simulation result is matched with each predicted failure result, and the successfully matched predicted failure result is used as the true failure result of the failed semiconductor device, so as to obtain the failure cause of the failed semiconductor device by reverse inference. Because the failure semiconductor device is directly used as an analysis object, the failure reason is obtained through reverse reasoning, the analysis is closer to the actual use scene of the device, and the result is more accurate and comprehensive.

It should be understood that, in this embodiment, the surface detection parameters, the element concentration detection parameters, and the profile detection parameters of the normal semiconductor device corresponding to the failure point region on the failed semiconductor device may also be set according to a specific application scenario, and the physical detection mode of each parameter may also be flexibly selected. For convenience of understanding, the content and the obtaining manner included in each parameter are described below in the present embodiment by way of example.

In one example of the present embodiment, the surface detection parameters of the failure point region may include, but are not limited to: at least one of the shape of the failure point region, the size of the failure point region, the structure of the failure point region and the color of the failure point region;

the process of obtaining the surface inspection parameters of the failure point region on the normal semiconductor device is shown in fig. 2, which may include but is not limited to:

s201: and unsealing the failed semiconductor device and the normal semiconductor device to expose the area to be detected.

For example, in some application scenarios, corresponding to the semiconductor device to be unsealed (e.g., a failed semiconductor device and a normal semiconductor device), the external package of the semiconductor device may be first observed to check whether the external package is intact. The packaged semiconductor device is placed on a high-temperature base station, heating stripping operation is carried out under an optical microscope, gold wires are removed by using tweezers or other tools, germanium tin is added around the semiconductor device, and the germanium tin melts at the bottom of the semiconductor device when heated, so that a layer of molten germanium tin is generated on the bottom of the semiconductor device and the surface of the package, and the semiconductor device is conveniently stripped from the package.

In some application scenarios, the uncapped failed semiconductor device can be observed under an optical microscope, the microscopic composition, structure and state of the surface of the failed region of the device can be observed, and the failure position, failure area, surface contamination (in some examples, the surface contamination condition may not be recorded) and other conditions can be recorded.

S202: and positioning a failure point in a to-be-detected region of the failed semiconductor device, and taking a region corresponding to the position of the failure point on the normal semiconductor device as a failure point region.

For example, in some application scenarios, the exact failure point region may be determined by, but not limited to, analysis by an Emission Microscope (EMMI). The test fixture can be customized for the semiconductor device prior to analysis. And designing the size of a clamp slot according to the size of the sample device, and manufacturing a proper external matching circuit according to the corresponding parameters and test requirements of the device.

The micro-light microscope analysis adopts a comparative analysis mode of a normal semiconductor device and a failure semiconductor device, and aims to quickly locate a failure point of the device through the position of a light-emitting point observed under the micro-light microscope. As shown in fig. 3. In the testing process, different grid and drain voltages on the failure semiconductor device and the normal semiconductor device are set through an external source meter, photons emitted by the devices under different voltage states are collected by using a microscope objective, the collected photons are detected by a photoelectric detector, and finally, signals are transmitted to a computer for displaying and analyzing; the difference of the light emitting points 301 of the failed semiconductor device and the normal semiconductor device is recorded as the position of the failure point, wherein the light emitting point exists on the failed semiconductor device but does not exist on the normal semiconductor device, so that the failure point can be positioned in the area to be detected of the failed semiconductor device, and the area corresponding to the position of the failure point on the normal semiconductor device is used as the area of the failure point.

S203: and acquiring surface detection parameters of the failure point area on the normal semiconductor device through a scanning electron microscope.

For example, at least one of the shape of the fail point region, the size of the fail point region, the structure of the fail point region, and the color of the fail point region on the normal semiconductor device can be observed and recorded by a Scanning Electron Microscope (SEM).

Optionally, at least one of the shape of the failure point region, the size of the failure point region, the structure of the failure point region, and the color of the failure point region on the failed semiconductor device may also be observed by a scanning electron microscope as an evaluation detection parameter for use as a basis for analyzing and predicting a failure result, where these parameters are also: surface inspection parameters of a failure point region on a failed semiconductor device, and a failure result can be predicted based on these evaluation inspection parameters.

For example, in an application scenario, a scanning electron microscope method may be used to characterize the surface micro-topography of a semiconductor device, where the scanning electron microscope bombards the surface of the semiconductor device (a normal semiconductor device or a failed normal semiconductor device) with a focused electron beam, converts the surface topography of the device into an electrical signal by secondary electrons, backscattered electrons, etc. generated by the interaction between the electrons and the semiconductor device, and then converts the electrical signal into an image to be displayed on a display device. As shown in fig. 4, by observing the failure point region 401 of the semiconductor device through a scanning electron microscope, it is obtained whether there are cracks, pits, stains, and the like near the failure point of the semiconductor device, and information such as the position, size, color, and the like of the failure point is recorded.

In an example of the present embodiment, the element concentration detection parameters of the failure point region on the normal semiconductor device may include, but are not limited to: and at least one of aluminum element, gallium element and nitrogen element changes with the depth of the device. An example of obtaining the element concentration detection parameters of the failure point region is shown in fig. 5, which may include but is not limited to:

s501: the ion beam bombards the failure point area on the normal semiconductor device, and the atoms on the surface are sputtered out to become charged ions.

For example, in an application scenario, a failure point region on a normal semiconductor device may be analyzed by, but not limited to, Secondary Ion Mass Spectroscopy (SIMS), and information such as a change in concentration of different elements with depth may be recorded and output. Secondary ion mass spectrometry techniques learn surface composition information by bombarding a surface (e.g., a failure point region on a normal semiconductor device) with an ion beam, sputtering atoms from the failure point region on the normal semiconductor device into charged ions, and then analyzing the charge/mass ratio of the ions by, but not limited to, time-of-flight or magnetic deflection mass spectrometry. For example, in the application scenario, in this case, the secondary ion mass spectrometry technology is used to obtain the information of the change of the concentration of elements such as Al, Ga, and N from top to bottom along with the depth of the device.

S502: and obtaining element concentration detection parameters by analyzing the charge/mass ratio of the charged ions.

In an example of the present embodiment, the profile inspection parameters of the fail point region on the normal semiconductor device may include, but are not limited to: at least one of profile structure, profile shape, profile thickness, profile depth, profile color, and level of failure point. Fig. 6 shows a process for obtaining profile inspection parameters of a failure point region, which may include, but is not limited to:

s601: and cutting the failure point region on the normal semiconductor device by using a focused ion beam technology to expose a corresponding section.

S602: and observing the section through a scanning electron microscope to obtain the section detection parameters.

For example, in one application scenario, a Focused Ion Beam (FIB) may be used to cut a failure point region on a normal semiconductor device, and the Focused Ion Beam FIB may bombard the failure point region on the normal semiconductor device with an Ion Beam to precisely cut a desired cutting position. Focused ion beam FIB cutting needs to pay attention to the size and the depth of a cutting position, and the grid electrode, the source electrode, the drain electrode, the field plate and the buffer layer structure of a normal semiconductor device can be clearly observed. Scanning electron microscope observation is performed on the cut position, and at least one of the cross-sectional structure, the cross-sectional shape, the cross-sectional thickness, the cross-sectional depth, the cross-sectional color, and the layer where the failure point is located, for example, shape information of the gate electrode, the source electrode, the drain electrode, the field plate, the passivation layer, and the buffer layer, etc. can be recorded, as shown in fig. 7.

Naturally, the same method can also be adopted to cut the failure point region on the failure semiconductor device, the cut position is observed by a scanning electron microscope, and at least one of the section structure, the section shape, the section thickness, the section depth, the section color and the layer where the failure point is located on the failure semiconductor device is recorded as an evaluation detection parameter, namely, the section detection parameter of the failure point region on the failure semiconductor device; failure results can be predicted based on these evaluated test parameters.

In an example of the present embodiment, the element concentration detection parameters of the failure point region on the normal semiconductor device may further include, but are not limited to: the element composition parameters of the section comprise at least one of element composition parameters, element distribution parameters and element migration parameters; one of the processes for obtaining the elemental composition parameters of the cross-section is shown in fig. 8, which includes but is not limited to:

s801: and cutting the failure point region on the normal semiconductor device by using a focused ion beam technology to expose a corresponding section. The cutting method can be seen from the above description, and is not described herein again.

S802: elemental composition parameters were obtained by elemental composition analysis of the cross-section by Electrostatic Discharge (ESD) spectrometer.

Since various elements have different X-ray characteristic wavelengths, the X-ray spectroscopy EDS performs a composition analysis by monitoring the different element X-ray characteristic wavelengths. The EDS can observe a section obtained by cutting the failure point region, obtain the failure point region, carry out element analysis on the device defect and each structure of the device, and output at least one of element composition parameters, element distribution parameters and element migration parameters. Similarly, the same method can be adopted to cut the failure point region on the failure semiconductor device, and the cut section is analyzed by an electrostatic discharge energy spectrometer to obtain at least one of section element composition parameters, element distribution parameters and element migration parameters on the failure semiconductor device as an evaluation detection parameter, namely, a part of the section detection parameters of the failure point region on the failure semiconductor device; according to the evaluation detection parameters, the accuracy of the failure prediction result can be further improved.

Optionally, in some examples of this embodiment, the target detection parameters of the normal semiconductor device further include: and detecting the sample detection parameters obtained by detecting the sample obtained by cutting the corresponding failure point region of the normal semiconductor device, wherein the thickness of the sample is less than or equal to 100 nanometers. For example, the sample detection parameter can include, but is not limited to, at least one of sample structure, sample shape, sample size, sample depth, sample color, sample texture, and level of failure point on the sample; in an application example, please refer to fig. 9 for obtaining the sample detection parameters, which may include but is not limited to:

s901: and cutting the corresponding failure point region of the normal semiconductor device by a focused ion beam technology to obtain a sample.

S902: the sample detection parameters were obtained by observing a cross section of the sample with a Transmission Electron Microscope (TEM).

For example, in an application scenario, a sample after sample preparation is subjected to field emission Transmission Electron Microscope (TEM) analysis, so that structural features of the device are observed more clearly, and structures (i.e., sample structures) such as a passivation layer, a gate metal layer, a seed layer, an epitaxial layer and the like of a normal semiconductor device, and information (i.e., sample size), composition (i.e., sample structure) and the like of each layer can be represented.

The embodiment of the invention realizes the reverse analysis of the failure reason of the failed semiconductor device, takes the real failed semiconductor device as a direct analysis object, and has comprehensive and accurate analysis result. In some application scenarios, the method can reasonably combine the optical lens, the EMMI, the SEM, the FIB, the TEM, the EDS and the SIMS with simulation (for example, but not limited to Silvaco simulation) aiming at the reverse failure analysis method of the burnt GaN HEMT device, is complete, accurate and effective, and fills the blank of failure reason analysis of invalid GaN HEMTs.

Example two:

for easy understanding, the present embodiment further provides a semiconductor device failure analysis apparatus based on the above embodiments, as shown in fig. 10, which includes but is not limited to:

the obtaining module 1001 obtains target detection parameters of a normal semiconductor device through physical detection, where the target detection parameters include detection parameters of a failure point region on a failure semiconductor device corresponding to the normal semiconductor device, and the target detection parameters include: surface detection parameters of the failure point region, element concentration detection parameters of the failure point region and section detection parameters of the failure point region; the normal semiconductor device and the failure semiconductor device are the same device; for a specific obtaining process, reference may be made to, but is not limited to, the above embodiments, and details are not described herein.

The processing module 1002 is configured to input the target detection parameter as an input parameter of a preset simulation algorithm, and obtain a failure reason of the failed semiconductor device by combining the preset simulation algorithm with the predicted failure result. The specific processing procedure can be seen in, but not limited to, the above embodiments, and is not described herein again.

The functions of the obtaining module 1001 and the processing module 1002 in this embodiment may be implemented by, but are not limited to, a processor in the corresponding semiconductor device failure analysis apparatus.

For ease of understanding, the present embodiment will be described below by taking a semiconductor device as an example of a HEMT made of a GaN-based material. An exemplary analysis process is shown in fig. 11, which includes:

s1101: uncapping and optical microscope analysis.

First, the external package of the GaN HEMT is observed to check whether the external package is intact. Placing the packaged GaN HEMT on a high-temperature base table, performing heating stripping operation under an optical microscope, removing gold wires by using tweezers, adding germanium tin around the GaN HEMT, melting the germanium tin at the bottom of the device when the germanium tin is heated, and generating a layer of molten germanium tin between the bottom of the GaN HEMT and the surface of the package, which is beneficial to stripping the GaN HEMT from the package by using the tweezers.

Observing the uncapped failure GaN HEMT under an optical microscope, observing the microcosmic composition, structure and state of the surface of a failure region of the failure GaN HEMT, recording failure positions, failure areas, surface contamination and the like, and generating a failure document.

S1102: fixture fabrication and EMMI analysis.

On the basis of S1101, accurate failure points can be quickly determined by EMMI analysis based on recorded failure positions, failure areas and areas indicated by surface contamination.

The GaN HEMT needs to be custom-made with a test fixture before performing the micro-light microscope EMMI analysis. And designing the size of a clamp slot of the clamp according to the size of the GaN HEMT, and manufacturing a proper external matching circuit according to corresponding parameters and test requirements of the device.

The low-light-level microscope EMMI analysis adopts a comparison analysis mode of a normal GaN HEMT and a failure GaN HEMT, and aims to quickly locate the failure point of the failure GaN HEMT through the position of a light emitting point observed under the low-light-level microscope EMMI. In the testing process, different grid and drain voltages on the GaN HEMT are set through an external source meter, photons emitted by the device under different voltage states are collected by using a microscope objective, the collected photons are detected by a photoelectric detector, and finally, signals are transmitted to a computer for displaying and analyzing. The difference in the light emission points of the failed GaN HEMT and the normal GaN HEMT is compared, and the light emission point that is present on the failed GaN HEMT but not present on the normal GaN HEMT is taken as the failure point.

S1103: and performing SEM and SIMS analysis on the failure point region on the failure GaN HEMT and the corresponding failure point region on the normal GaN HEMT.

The surface micro-morphology of the device is represented by a scanning electron microscope SEM method, the scanning electron microscope SEM bombards the surface of a sample (namely a failure point area on a failure GaN HEMT and a normal GaN HEMT) by focused electron beams, the surface morphology of the device is converted into an electric signal by secondary electrons, back scattering electrons and the like generated by the interaction of electrons and the sample, and then the electric signal is converted into an image to be displayed on a display device. By observing the failure point of the device through a scanning electron microscope SEM, whether the failure point of the failure GaN HEMT has cracks, craters, contamination and other phenomena is known, and information such as the position, the size, the color and the like of the failure point is recorded, so that the method can be used for evaluating a prediction result. Meanwhile, relevant information of a corresponding region on the normal GaN HEMT is observed and recorded to be used as an input parameter of subsequent simulation.

The SIMS technique uses ion beam bombardment of the surface to sputter atoms from the failure point region on a normal GaN HEMT into charged ions, which are then analyzed by, but not limited to, time-of-flight or magnetic deflection mass spectrometer for their charge/mass ratio to learn the surface composition information. In the present application example, SIMS technology can be used to obtain information on the variation of the concentration of Al, Ga, N, etc. elements from top to bottom with the depth of the device.

S1104: EDS analysis is performed on the failure point area section on the failure GaN HEMT and the normal GaN HEMT.

And cutting the failure point areas on the failure GaN HEMT and the normal GaN HEMT by using the focused ion beam FIB, wherein the focused ion beam FIB can be used for accurately cutting the positions to be cut by bombarding the failure point areas on the failure GaN HEMT and the normal GaN HEMT by ion beams. Focused ion beam FIB cutting needs to pay attention to the size and the depth of a cutting position, and the grid electrode, the source electrode, the drain electrode, the field plate and the buffer layer structure of the device can be clearly observed. And performing SEM observation on the cut position, and recording section detection parameters of the failure point region, such as the shape information of the grid electrode, the source electrode, the drain electrode, the field plate, the passivation layer and the buffer layer.

In addition, since various elements have different X-ray characteristic wavelengths, the X-ray spectral analysis EDS performs a composition analysis by monitoring the different element X-ray characteristic wavelengths. The EDS can perform elemental analysis on observed failure points, device defects and various structures of the device. The method aims to output information such as element composition, element distribution, element migration and the like of a failure point area section of a failure GaN HEMT and observe whether element permeation occurs or not; and outputting information such as the element composition, the element distribution, the element migration and the like of the section of the failure point region on the normal GaN HEMT as input parameters of subsequent simulation.

And S1105, carrying out TEM analysis on the section of the failure point region on the normal GaN HEMT.

Before field emission Transmission Electron Microscope (TEM) observation is carried out on the normal GaN HEMT, the Focused Ion Beam (FIB) can be used for sampling the normal GaN HEMT. Referring to fig. 12:

s1201: firstly, plating a layer of platinum (Pt) on a sample preparation area of a device (namely a normal GaN HEMT);

s1202: then, carrying out focused ion beam FIB cutting on two sides of the sample preparation area by using large current;

and S1203, after cutting, inclining the device to an angle, and carrying out FIB cutting on the device from the side surface by using U-shaped focused ion beams. Subsequently, the probe is placed on the upper cut on the side where the device is completely cut.

And S1204, carrying out focused ion beam FIB cutting on the copper mesh, and cutting a groove above the copper mesh by using the focused ion beam FIB, wherein the groove is used for enabling the device to be horizontally placed on the copper mesh, and the groove can also enable residues generated in the cutting process to fall into the groove.

S1205: and then transferring the device to a groove of a copper mesh through a probe, fixing the device by using platinization, separating the probe from the device after the device is fixed, and cutting off the probe by using a focused ion beam FIB to achieve the purpose of separation.

S1206: finally, I need to thin the device, and repeatedly cut the device on both sides by a low-current focused ion beam FIB, so that the thickness of the device is finally reduced to below 100 nm, which can be set to below 90 nm, below 50 nm or below 40 nm, for example.

And performing field emission Transmission Electron Microscope (TEM) analysis on the sample after sample preparation, so that the structural characteristics of the normal GaN HEMT can be observed more clearly, and the information of the size, the structure, the composition and the like of the structures such as the passivation layer, the gate metal layer, the seed layer, the epitaxial layer and the like of the normal GaN HEMT can be represented.

S1106: simulation of Silvaco.

Inputting the target parameters (i.e. the surface detection parameters of the failure point region, the element concentration detection parameters of the failure point region, and the profile detection parameters of the failure point region, for example, as shown in fig. 13, including but not limited to the epitaxial layer thickness, the element composition, the gate metal structure, etc.) of the normal GaN HEMT obtained by the physical analysis means into the silverco device simulation software, performing simulation on the distribution of parameters which may cause failure, such as the electric field, the temperature, and the carrier concentration, in the device, and finally deducing the failure cause of the device, for example, the failure cause may be but not limited to:

when the temperature of a certain point of an epitaxial layer of the failed GaN HEMT is higher than 980 ℃, the GaN material can be thermally decomposed, so that the device is failed at high temperature;

the electric field intensity of a certain point of an epitaxial layer of the failed GaN HEMT is higher than 3.39MV/cm, and the GaN material reaches the critical field intensity of the GaN material, so that the device is failed at high voltage.

In the analysis method of the failed GaN HEMT, the optical lens, the EMMI, the SEM, the FIB, the TEM, the EDS, the SIMS and the Silvaco simulation are reasonably combined together aiming at the fact that the burned GaN HEMT device can be subjected to reverse failure analysis, and the method is complete, accurate and effective; compared with the forward analysis in the related technology, the accuracy of the analysis can be further improved.

Example three:

the present embodiment also provides a semiconductor device failure analysis apparatus, as shown in fig. 14, including a processor 1401, a memory 1402, and a communication bus 1403 connecting the processor 1401 and the memory 1402;

the memory 1402 stores a computer program that can be executed by the processor 1401 to implement the steps of the semiconductor device failure analysis method as shown in the above embodiments.

The present embodiment also provides a computer-readable storage medium storing a computer program executable by a processor to implement the steps in the semiconductor device failure analysis method as shown in the above embodiments.

The computer-readable storage media in this embodiment include volatile or nonvolatile, removable or non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, computer program modules or other data. Computer-readable storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash Memory or other Memory technology, CD-ROM (Compact disk Read-Only Memory), Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer.

The present embodiment also provides a computer program (or computer software), which can be distributed on a computer readable medium and executed by a computing device to implement the steps in the semiconductor device failure analysis method as described above; and in some cases at least one of the steps shown or described may be performed in an order different than that described in the embodiments above.

The present embodiments also provide a computer program product comprising a computer readable means on which any of the computer programs as set out above is stored. The computer readable means in this embodiment may include a computer readable storage medium as shown above.

It will be apparent to those skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software (which may be implemented in computer program code executable by a computing device), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

In addition, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to one of ordinary skill in the art. Thus, the present invention is not limited to any specific combination of hardware and software.

The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A semiconductor device failure analysis method, the semiconductor device is a semiconductor device made based on a gallium nitride material, and the semiconductor device failure analysis method comprises:

The target detection parameters of the normal semiconductor device are obtained through physical detection, and the target detection parameters include detection parameters of the normal semiconductor device corresponding to the failure point area on the failed semiconductor device, including: surface detection parameters of the failure point area, failure point area The element concentration detection parameters and the profile detection parameters of the failure point area; the normal semiconductor device and the failure semiconductor device are the same device;

The target detection parameter is input as the input parameter of the preset simulation algorithm, and the failure cause of the failed semiconductor device is obtained by combining the preset simulation algorithm with the predicted failure result.

2 . The failure analysis method of a semiconductor device according to claim 1 , wherein the surface detection parameters of the failure point area include: the shape of the failure point area, the size of the failure point area, the structure of the failure point area, and the color of the failure point area. 3 . at least one of;

Obtaining the surface detection parameters of the failure point area includes:

Unpacking the failed semiconductor device and the normal semiconductor device to expose the area to be detected;

Locate the failure point in the to-be-detected area of the failed semiconductor device, and use the region on the normal semiconductor device corresponding to the position of the failure point as the failure point region;

The surface detection parameters of the failure point region on the normal semiconductor device are obtained by scanning electron microscopy.

3 . The failure analysis method of a semiconductor device according to claim 1 , wherein the element concentration detection parameter in the failure point region comprises: concentration change information of at least one of aluminum element, gallium element, and nitrogen element with the depth of the device. 4 . ;

Obtaining the element concentration detection parameters of the failure point area includes:

By bombarding the failure point area on the normal semiconductor device with an ion beam, the atoms on the surface are sputtered to become charged ions;

The element concentration detection parameters are obtained by analyzing the charge/mass ratio of the charged ions.

4. The semiconductor device failure analysis method according to claim 1, wherein the section detection parameters of the failure point area include: section structure, section shape, section thickness, section depth, section color, and the level at which the failure point is located at least one of;

Obtaining the profile detection parameters of the failure point area includes:

Cutting the failure point region on the normal semiconductor device by the focused ion beam technology to expose the corresponding section;

The profile detection parameters are obtained by observing the profile through a scanning electron microscope.

5 . The failure analysis method of a semiconductor device according to claim 1 , wherein the section detection parameters of the failure point area include: element composition parameters of the section, and the element composition parameters include element composition parameters, element distribution parameters, at least one of the element migration parameters;

Obtaining the element composition parameters of the profile includes:

The elemental composition parameters are obtained by performing elemental composition analysis on the profile by an electrostatic discharge energy spectrometer.

6. The failure analysis method for a semiconductor device according to any one of claims 1 to 5, wherein the target detection parameter further comprises: a sample obtained by cutting the normal semiconductor device corresponding to the failure point region to perform The obtained sample detection parameters are detected, and the thickness of the sample is less than or equal to 100 nanometers.

7. The method for failure analysis of a semiconductor device according to claim 6, wherein the sample detection parameters include sample structure, sample shape, sample size, sample depth, sample color, sample structure, and level of failure points on the sample at least one of;

Obtaining the sample detection parameters includes:

A sample prepared by cutting the normal semiconductor device corresponding to the failure point region by the focused ion beam technology;

The sample detection parameters are obtained by observing the cross section of the sample through a transmission electron microscope.

8. The failure analysis method for a semiconductor device according to any one of claims 1 to 5, characterized in that, in the process of obtaining target detection parameters of a normal semiconductor device through physical detection, further comprising obtaining the failed semiconductor device Evaluation and detection parameters of the failure point region on the failed semiconductor device, the evaluation and detection parameters include at least one of surface detection parameters of the failure point region on the failed semiconductor device, and cross-section detection parameters of the failure point region;

The predicted failure result is predicted and obtained according to the evaluation detection parameter.

9. A semiconductor device failure analysis device, characterized in that, comprising:

The acquisition module obtains the target detection parameters of the normal semiconductor device through physical detection, the target detection parameters include the detection parameters of the normal semiconductor device corresponding to the failure point area on the failed semiconductor device, including: the surface detection parameters of the failure point area, the failure point area Element concentration detection parameters in the point area, profile detection parameters in the failure point area; the normal semiconductor device and the failure semiconductor device are the same device;

The processing module is configured to input the target detection parameters as input parameters of the preset simulation algorithm, and obtain the failure cause of the failed semiconductor device by combining the preset simulation algorithm with the predicted failure result.

10. A semiconductor device failure analysis device, comprising a processor, a memory, and a communication bus connecting the processor and the memory;

The memory stores a computer program executable by the processor to implement the steps of the semiconductor device failure analysis method according to any one of claims 1-8.

11. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, and the computer program can be executed by a processor to implement the method according to any one of claims 1-8. Steps of a semiconductor device failure analysis method.