CN114089157B - Chip testing method and system - Google Patents
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- CN114089157B CN114089157B CN202111287314.0A CN202111287314A CN114089157B CN 114089157 B CN114089157 B CN 114089157B CN 202111287314 A CN202111287314 A CN 202111287314A CN 114089157 B CN114089157 B CN 114089157B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application relates to a chip testing method and a system. There is provided a chip test system including a tester and a chip to be tested, wherein the chip to be tested includes: a VDD pin through which the chip to be tested receives a power supply signal from the tester and generates an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; SWD pins, through which the chip to be tested performs single-wire communication with the tester in a test mode; and a single-wire OWM module configured to monitor the SWD pin for a predetermined time after the chip under test is reset to determine whether the chip under test enters the test mode, and to program the trim bits using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester in response to the chip under test entering the test mode.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a method and system for testing a chip.
Background
A chip usually needs to place some trim bits (trim bits) at design time, and the purpose of the trim bits is to calibrate analog circuits, such as Bandgap/Vref/ROSC, during chip ATE test; on the other hand, in order to provide some customized options, internal functions are set, so that certain flexibility is realized. The traditional trim approach is to program one-time programmable (OTP) memory in the chip using several electrical test points (Probe PADs) to achieve a logic 0 or 1 selection. Probe PAD increases the area of the chip, resulting in increased chip cost.
Disclosure of Invention
In order to solve the above problems, the present application proposes a single-wire test mechanism, which can implement programming of trim bits inside a chip by functionally multiplexing chip pins without adding an additional Probe PAD.
Specifically, according to one embodiment of the present application, there is provided a chip test system including a tester and a chip under test, wherein the chip under test includes: a VDD pin through which the chip to be tested receives a power supply signal from the tester and generates an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; SWD pins, through which the chip to be tested performs single-wire communication with the tester in a test mode; and a single-wire OWM module configured to monitor the SWD pin for a predetermined time after the chip under test is reset to determine whether the chip under test enters the test mode, and to program the trim bits using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester in response to the chip under test entering the test mode.
According to another embodiment of the present application, there is provided a chip testing method including the steps of: receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; monitoring an SWD pin of the chip to be tested in a preset time after the chip to be tested is reset through a single-wire OWM module in the chip to be tested to determine whether the chip to be tested enters a test mode, and responding to the chip to be tested entering the test mode, programming the trim bit by using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester.
According to yet another embodiment of the present application, there is provided a computer readable storage medium having stored thereon program instructions which, when executed by a processor, cause the processor to perform the method of: receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; monitoring an SWD pin of the chip to be tested in a preset time after the chip to be tested is reset through a single-wire OWM module in the chip to be tested to determine whether the chip to be tested enters a test mode, and responding to the chip to be tested entering the test mode, programming the trim bit by using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester.
Depending on the embodiment, one or more effects may be achieved. These advantages, various additional objects, features, and benefits of the present application will be fully understood with reference to the following detailed description and accompanying drawings.
Drawings
FIG. 1 is a schematic diagram illustrating a single wire test system according to the present application;
FIG. 2 shows functional modules of a chip under test according to the present application;
FIG. 3 is a flow chart showing whether a detection chip enters a test mode according to the present application;
FIG. 4 is a timing diagram showing whether a chip enters a test mode or not according to the present application;
fig. 5 shows an example of a bit period of bit data according to the present application;
fig. 6 shows an example of a signal waveform representing bit data of 1 according to the present application;
fig. 7 shows an example of a signal waveform representing bit data of 0 according to the present application;
fig. 8 shows an example of waveforms of a test start signal issued by the tester;
FIG. 9 shows an example of waveforms of a test stop signal issued by a tester;
fig. 10 shows an example of a data transmission format used for the test method of the present application; and
fig. 11 is a flow chart illustrating a test method according to the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below. The following description covers numerous specific details in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely to provide a clearer understanding of the technical solutions of the present application by showing examples of the present application. The present application is in no way limited to any particular configuration set forth below, but rather covers any adaptations, alternatives, and improvements of relevant features, structures, operations, etc. without departing from the spirit of the application.
Fig. 1 is a schematic diagram illustrating a single wire test system according to the present application. As shown in fig. 1, SWD is a test multiplexing pin of a chip to be tested, and is used for single-wire communication with a tester during testing; VDD is the power pin of the chip under test through which power is supplied to the chip under test by the tester during testing.
Fig. 2 shows a chip functional module to be tested according to the present application. As shown in FIG. 2, the chip contains basic analog circuits such as Bandgap/LDO/VREF/ROSC, all with calibration bits, calibrated by trim bits. A power-on reset (POR) module in the chip generates an internal reset signal reset of the chip; the ROSC is an RC oscillator that generates the internal operating clock signal clk of the chip. Trim bit module is a one-time programmable memory, i.e., OTP, that stores configuration parameters. The Normal Function (Normal Function) module is responsible for running the main Function logic of the chip to be tested; a single Wire Module (OWM) is used to program trim bits inside the chip under test in test mode. The chip can work in two states of a Normal Mode and a Test Mode. In the normal mode, SWD is a normal function pin, and the function is defined according to the actual requirement of the chip; in test mode, the SWD is multiplexed as test pins.
Fig. 3 shows a flow of detecting whether the chip enters the test mode and fig. 4 shows a timing chart of detecting whether the chip enters the test mode. As shown in fig. 3, after the chip is powered on, the internal POR module releases the reset signal to reset the chip to be tested; t of OWM module after resetting chip to be tested wait The SWD pins are monitored over time to determine whether the chip under test enters a test mode. Specifically, if the OWM module monitors that the SWD pin has a predetermined pattern, the chip under test enters a test mode, so as to turn on a single-wire communication function to communicate with the tester, otherwise, the chip under test is in T wait After which time the normal operation mode is entered. According to one embodiment of the present application, T wait The value may be set, for example4ms-200ms.
The tester controls the power-on time sequence of the chip to be tested and powers on T wait During which a test entry pattern (which may be a set of special waveforms) is continuously sent to ensure that the chip under test can enter the test pattern, as shown in fig. 4.
The test method according to the present application will be described in detail below with reference to fig. 5 to 10.
After the chip is powered on and reset, the OWM module starts the single wire communication function of the SWD after detecting that the SWD pin has a predetermined mode (i.e., test entry mode). It should be noted here that, since the ROSC inside the chip to be tested has not yet passed through the trim, a large error occurs between the initial frequency and the design frequency, typically with an error of 30% -50%. Therefore, it is necessary to design a communication method insensitive to the clock frequency deviation inside the chip. For this purpose, the present application presets a Time Unit (TU) whose value may be equal to, for example, one ideal clock period of the on-chip ROSC.
According to the set unit time, the bit period of the bit data received from the tester through the SWD pin is set to, for example, 40TU, as shown in fig. 5. The tester transmits each bit of data strictly according to the high-low level duty ratio of 30TU/10TU or 10TU/30 TU. It should be noted here that, although the bit period is set to 40TU in the present application, bit periods of other lengths may be set according to specific needs. In addition, although the present application shows that the tester transmits each bit data according to the high-low level duty ratio of 30TU/10TU or 10TU/30TU, other duty ratios may be set according to specific needs.
The receiving logic of the OWM module of the chip to be tested counts the high-low level width between two continuous rising edges of each bit data received, and the count values are CntHigh and CntLow respectively. If the count value of the high level is greater than the count value of the low level, i.e., cntvigh > CntLow, it is determined that the received bit data is 1, as shown in fig. 6; otherwise, the received bit data is determined to be 0, as shown in fig. 7. In other words, due to the deviation of the internal ROSC frequency of the chip to be tested, the OWM module does not need to determine whether the bit data is 1 or 0 according to the absolute length of the width of the high level and the low level of the bit data, but determines according to the relative size of the high level and the low level of the bit data.
After the chip under test enters the test mode, the tester sends a test start signal to the chip under test by pulling down the SWD pin of the chip under test (i.e., swd=0) and holding for a time greater than a predetermined number of units of time, such as 160 TU. The OWM module of the chip under test detects the level of the SWD pin, counts the internal clock of the chip under test for swd=0, and when the counted value exceeds a predetermined threshold, for example 60, the chip under test starts to prepare to receive a frame of data from the tester, as shown in fig. 8.
After the tester has sent the programming bit data to the chip under test, it first sends a test stop signal to the chip under test by pulling up the level of the SWD pin (i.e., swd=1) and holding for a time greater than a predetermined number of units of time (e.g., 200 TU). The OWM module of the chip under test detects the level of the SWD pin, counts the internal clock of the chip under test in swd=1 time, and resets the communication logic once when the counted value exceeds a predetermined threshold, for example 100, as shown in fig. 9.
Specifically, according to one embodiment of the present application, a data frame having a predetermined data transmission format may be used to send programming bit data to the chip under test to program an OTP (e.g., a 64-bit OTP) inside the chip under test.
According to one embodiment of the present application, the data frame having the predetermined data transmission format includes a frame header data section for distinguishing the data frame type, an address data section for indicating which location of the OTP is programmed, and a check data section for checking the data frame to determine whether it is a correct programmed data frame.
Fig. 10 illustrates a data transmission format of a data frame sent by a tester for programming an OTP of a chip under test according to an embodiment of the application. As shown in fig. 10, the tester may send a data frame having a data transmission format as shown:
Satrt_1010_B11B10B9B8B7B6_B5B4B3B2B1B0_Stop，
wherein the data frame has 16 bits (i.e., bn-B0, where n=15), the first 4 bits of data 1010 (B15-B12) are used as a frame header to distinguish the data frame types, the middle 6 bits of data (B11-B6) are OTP addresses, which indicate programming the position of the OTP to which the bit data points, and the last 6 bits of data (B5-B0) are the inverse of the middle 6 bits of data (B11-B6).
In operation, the OWM module of the chip under test checks if the first 4 bits of data of the data frame is 1010, and if not, ignores the data frame.
Further, the OWM module of the chip to be tested checks whether the middle 6-bit data and the last 6-bit data representing the OTP address in the data frame satisfy the inverse relation, and if not, ignores the data frame.
Further, if the OWN module of the chip under test detects that the first 4 bits of data of the data frame is 1010 and the middle 6 bits of data and the last 6 bits of data representing the OTP address satisfy the inverse relationship, it starts to program the trim bits inside the chip under test in the test mode.
Although in the present application it is described that the data frame of the predetermined data transmission format is used for programming the OTP inside the chip to be tested, it will be appreciated that other data transmission formats may be designed according to the specific situation, for example, a data frame with more or less bit data may be used according to the actual situation, other frame header data may be set, and other verification methods are used to determine whether the data frame is a correctly programmed data frame.
Fig. 11 shows a flow chart of a test method according to the present application. As shown in fig. 11, the method includes: step S1102, receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; step S1104, monitoring SWD pins of the chip to be tested in a preset time after the chip to be tested is reset through a single-wire OWM module in the chip to be tested to determine whether the chip to be tested enters a test mode; and step S1106, in response to the chip under test entering the test mode, programming the trim bits using programming bit data received from the tester based on single wire communication between the SWD pins and the tester.
In some embodiments of the present application, the OWM module is configured to determine that the chip under test enters the test mode when a predetermined test entry mode is monitored to occur on the SWD pin within a predetermined time after the chip under test is reset.
In some embodiments of the present application, the OWM module is configured to determine whether the program bit data is "1" or "0" based on counting a high-low level width between consecutive two rising edges of the program bit data received from the tester within a predetermined bit period.
In some embodiments of the present application, if a count value of a high level width between consecutive two rising edges of program bit data received from the tester is greater than a count value of a low level width within the predetermined bit period, the program bit data is determined to be "1", and conversely, the program bit data is determined to be "0".
In some embodiments of the present application, the tester transmits a test start signal to the chip under test by setting the SWD pin to a low level for a first predetermined number of the bit periods, the chip under test counts the low level width of the SWD, and starts to prepare to receive program bit data from the tester when the count value of the low level width of the SWD is greater than a predetermined threshold.
In some embodiments of the present application, the tester sends a test stop signal to the chip under test by setting the SWD pin high for a second predetermined number of the bit periods, the chip under test counts the high level width of the SWD, and resets its communication logic when the count value of the high level width of the SWD is greater than a predetermined threshold.
In some embodiments of the present application, the tester sends programming bit data to the chip under test using a data frame having a predetermined data transmission format, the data frame having the predetermined data transmission format including frame header data, address data, and check data.
In some embodiments of the present application, the OWM module is configured to check whether the frame header data of the data frame received from the tester is predetermined frame header data, and if not, ignore the data frame.
In some embodiments of the present application, the OWM module is configured to check whether the address data and the check data of the data frame received from the tester satisfy a predetermined relationship, and if not, to ignore the data frame.
Although specific embodiments of the present application have been described, those skilled in the art will appreciate that there are other embodiments equivalent to the described embodiments. Therefore, it is to be understood that the present application is not to be limited to the specific illustrated embodiments, but only by the scope of the appended claims.
Claims (17)
1. A chip test system comprises a tester and a chip to be tested,
wherein, the chip to be tested includes:
a VDD pin through which the chip to be tested receives a power supply signal from the tester and generates an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested;
SWD pins, through which the chip to be tested performs single-wire communication with the tester in a test mode; and
a single-wire OWM module configured to monitor the SWD pin for a predetermined time after the chip under test is reset to determine whether the chip under test enters the test mode, and in response to the chip under test entering the test mode, program a trim bit using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester,
the single-wire OWM module is configured to determine that the chip to be tested enters the test mode when a preset test entry mode appears on the SWD pin within a preset time after the chip to be tested is reset, wherein the preset test entry mode is a set of preset waveforms sent by the tester, and otherwise, the chip to be tested enters a normal operation mode after the preset time.
2. The test system of claim 1, wherein the single-wire OWM module is configured to determine whether the programming bit data is "1" or "0" based on counting a high-low level width between consecutive two rising edges of the programming bit data received from the tester within a predetermined bit period.
3. The test system of claim 2, wherein if a count value of a high level width between consecutive two rising edges of programming bit data received from the tester is greater than a count value of a low level width within the predetermined bit period, the programming bit data is determined to be "1", and conversely, the programming bit data is determined to be "0".
4. The test system of claim 1, wherein the tester sends a test start signal to the chip under test by setting the SWD pin to a low level for a first predetermined number of bit periods, the chip under test counts the low level width of the SWD pin, and begins to prepare to receive programming bit data from the tester when the count value of the low level width of the SWD pin is greater than a predetermined threshold.
5. The test system of claim 1, wherein the tester sends a test stop signal to the chip under test by setting the SWD pin high for a second predetermined number of bit periods, the chip under test counting the high width of the SWD pin and resetting its communication logic when the count value of the high width of the SWD pin is greater than a predetermined threshold.
6. The test system of claim 1, wherein the tester sends programming bit data to the chip under test using a data frame having a predetermined data transmission format, the data frame having the predetermined data transmission format including frame header data, address data, and verification data.
7. A test system as in claim 6, wherein the single-wire OWM module is configured to check whether the frame header data of the data frame received from the tester is predetermined frame header data, and if not, ignore the data frame.
8. A test system as in claim 6, wherein the single-wire OWM module is configured to check whether the address data and the check data of the data frame received from the tester satisfy a predetermined relationship, and if not, ignore the data frame.
9. A method of chip testing, comprising the steps of:
receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested;
monitoring SWD pins of the chip to be tested in a preset time after the chip to be tested is reset through a single-wire OWM module in the chip to be tested to determine whether the chip to be tested enters a test mode or not, and
in response to the chip under test entering the test mode, programming trim bits using programming bit data received from the tester based on single wire communications between the SWD pins and the tester,
the single-wire OWM module is configured to determine that the chip to be tested enters the test mode when a preset test entry mode appears on the SWD pin within a preset time after the chip to be tested is reset, wherein the preset test entry mode is a set of preset waveforms sent by the tester, and otherwise, the chip to be tested enters a normal operation mode after the preset time.
10. The method of claim 9, wherein the single-wire OWM module is configured to determine whether the programming bit data is "1" or "0" based on counting a high-low level width between consecutive two rising edges of the programming bit data received from the tester within a predetermined bit period.
11. The method of claim 10, wherein if a count value of a high level width between consecutive two rising edges of programming bit data received from the tester is greater than a count value of a low level width within the predetermined bit period, the programming bit data is determined to be "1", and conversely, the programming bit data is determined to be "0".
12. The method of claim 9, wherein the tester sends a test start signal to the chip under test by setting the SWD pin to a low level for a first predetermined number of bit periods, the chip under test counts the low level width of the SWD pin, and begins to prepare to receive programming bit data from the tester when the count value of the low level width of the SWD pin is greater than a predetermined threshold.
13. The method of claim 9, wherein the tester sends a test stop signal to the chip under test by setting the SWD pin high for a second predetermined number of bit periods, the chip under test counting the high width of the SWD pin and resetting its communication logic when the count value of the high width of the SWD pin is greater than a predetermined threshold.
14. The method of claim 9, wherein the tester transmits programming bit data to the chip under test using a data frame having a predetermined data transmission format, the data frame having the predetermined data transmission format including frame header data, address data, and check data.
15. A method as in claim 14, wherein the single-wire OWM module is configured to check whether the frame header data of the data frame received from the tester is predetermined frame header data, and if not, ignore the data frame.
16. A method as claimed in claim 14, wherein the single-wire OWM module is configured to check whether the address data and the check data of the data frame received from the tester satisfy a predetermined relationship, and if not, to ignore the data frame.
17. A computer readable storage medium having stored thereon program instructions which, when executed by a processor, cause the processor to perform the method according to any of claims 9-16.
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| CN202111287314.0A CN114089157B (en) | 2021-11-02 | 2021-11-02 | Chip testing method and system |
| TW110147998A TWI787006B (en) | 2021-11-02 | 2021-12-21 | Wafer testing method and system |
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| CN202111287314.0A CN114089157B (en) | 2021-11-02 | 2021-11-02 | Chip testing method and system |
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| CN114994512B (en) * | 2022-07-01 | 2025-09-09 | 浙江地芯引力科技有限公司 | Chip detection method, device, equipment and storage medium |
| CN117434428B (en) * | 2023-12-18 | 2024-03-26 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
| CN118259141B (en) * | 2024-05-24 | 2024-09-10 | 西安诺瓦星云科技股份有限公司 | Receiving card testing method, testing tool, system and readable storage medium |
| CN120652267A (en) * | 2025-08-08 | 2025-09-16 | 深圳市微源半导体股份有限公司 | Test mode control circuit, method and chip |
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|---|---|
| TWI787006B (en) | 2022-12-11 |
| TW202319768A (en) | 2023-05-16 |
| CN114089157A (en) | 2022-02-25 |
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