CN114094013A - Embedded inductor structure and manufacturing method thereof - Google Patents
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Abstract
本发明公开了一种嵌入式电感结构及其制作方法，电感结构包括具有一定深度的沟渠的衬底，在沟渠底部上依次设有沿沟渠的深度方向多层间隔的线圈结构，线圈结构包括金属层以及依次包裹在金属层侧壁的第一介电层和粘附层，线圈结构通过粘附层附着在沟渠的侧壁上，粘附层还包覆在金属层和第一介电层的底面，相邻间隔的两个线圈结构通过金属连接柱相连，多个线圈结构通过金属连接柱相连形成嵌入在衬底内的电感结构。采用DRIE与深度终点探测工艺形成具有垂直侧壁的沟渠，线圈结构的圈数可以根据需求进行调整，并实现电感值的可变控制，最终达到优化效能的目标。
The invention discloses an embedded inductance structure and a manufacturing method thereof. The inductance structure includes a substrate with a trench with a certain depth, and on the bottom of the trench are sequentially arranged coil structures spaced in multiple layers along the depth direction of the trench, and the coil structure includes metal layer, and the first dielectric layer and the adhesive layer sequentially wrapped around the sidewall of the metal layer, the coil structure is attached to the sidewall of the trench through the adhesive layer, and the adhesive layer is also wrapped around the metal layer and the first dielectric layer. On the bottom surface, two adjacently spaced coil structures are connected by metal connection posts, and a plurality of coil structures are connected by metal connection posts to form an inductance structure embedded in the substrate. The trenches with vertical sidewalls are formed by DRIE and deep end point detection processes. The number of turns of the coil structure can be adjusted according to requirements, and the variable control of the inductance value can be realized, and finally the goal of optimizing the performance is achieved.
Description
Technical Field
The invention relates to the field of inductors, in particular to an embedded inductor structure and a manufacturing method thereof.
Background
With the development of science and technology, technologies such as 5G wireless communication and GPS appear, and the technical requirements on high-performance radio frequency circuits, passive devices (IPDs) and the like are gradually increased. The inductor is used as a common electronic device in the fields of high-performance radio frequency circuits, passive devices and the like, and has an important position in the manufacture of semiconductor circuits.
The inductance value of the inductor is a main factor determining the target frequency of the filter, and the magnitude of the inductance value is determined by the thickness of the dielectric layer and the number of coils. The current 3D coil technology is a vertical inductor formed by winding through a twv (through Wafer via) process based on the thickness of the Wafer. One turn of the inductor is formed between two etching holes in the wafer, and if the number of the coils is increased, more groups of etching holes need to be expanded in space to form more turns of the coils. Therefore, the vertical inductor has low space utilization rate, the metal wire has low utilization rate, the integration is not facilitated, and the inductance value is not easy to control.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides an embedded inductor structure and a manufacturing method thereof.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the utility model provides an embedded inductance structure, is including the substrate of the irrigation canals and ditches that have certain degree of depth be equipped with the edge in proper order on the irrigation canals and ditches bottom the depth direction multilayer spaced coil structure of irrigation canals and ditches, the metal layer and first dielectric layer and adhesion layer around the metal layer, first dielectric layer and adhesion layer wrap up in proper order the lateral wall of metal layer, coil structure passes through the adhesion layer is attached to on the lateral wall of irrigation canals and ditches, and the adhesion layer still covers the metal layer with the bottom surface of first dielectric layer, adjacent spaced two coil structure passes through the metal connecting post and links to each other.
In an optional embodiment, a second dielectric layer or an air cavity is arranged between two adjacent spaced coil structures, the thickness of the second dielectric layer or the height of the air cavity is 1-10 μm, and the second dielectric layer is made of SiO2、Si3N4Or a polyimide.
In an alternative embodiment, the adhesion layer is Si or a seed layer, and the material of the seed layer includes TiW/Au or Ti/Cu.
In an alternative embodiment, the thickness of the first dielectric layer is 100nm to 2000nm, and the material of the first dielectric layer comprises SiO2Or Si3N4。
In an alternative embodiment, the depth of the trench is 10 μm to 100 μm, and the included angle between the sidewall of the trench and the bottom of the trench is 88 ° to 92 °.
In an optional embodiment, the thickness of the metal layer is 1-5 μm, and the material of the metal layer comprises at least one of Au, Cu, Pt, Ag, Ni, Co, or an alloy or a compound containing at least one of the foregoing metals.
In an alternative embodiment, the projected pattern of the trench on the substrate is a ring shape with an opening, and the metal layer extends from the opening of the ring shape and is provided with a lead connected with the metal connecting column.
A manufacturing method of an embedded inductor comprises the following steps:
1) etching a trench with a certain depth on a substrate by using DRIE combined with a depth endpoint detection technology;
2) forming an adhesion layer and a first dielectric layer on the side wall and the bottom of the trench by adopting an atomic layer deposition process;
3) removing the first dielectric layer at the bottom and exposing the adhesion layer;
4) manufacturing a metal layer on the adhesion layer to form a first layer of coil;
5) removing the adhesion layer and the first dielectric layer on the side wall of the trench above the metal layer;
6) depositing a second dielectric layer on the metal layer;
7) etching a contact hole in a preset area on the second dielectric layer;
8) and (5) repeating the steps 2-7, and manufacturing a multilayer coil to form an inductance structure.
In an optional embodiment, the thickness of the second dielectric layer is 1-10 μm, and the material of the second dielectric layer is SiO2、Si3N4Polyimide or sacrificial material; when the second dielectric layer is a sacrificial material, step 8 further includes: and forming an air cavity between the adjacent spaced upper and lower coils by opening the hole and removing the sacrificial material after the fabrication of the upper coil is completed.
In an optional embodiment, the adhesion layer is Si or a seed layer, when the adhesion layer is the seed layer, the material of the seed layer includes TiW/Au or Ti/Cu, and the metal layer is manufactured by using an electroplating process in the step 4; and when the adhesion layer is Si, the metal layer is manufactured by adopting a self-aligned silicide process in the step 4.
Compared with the prior art, the invention has the following beneficial effects:
(1) the embedded inductor structure of the invention adopts the embedded design in the chip, integrates the multilayer coil on the ditch of the chip and is arranged along the depth direction of the ditch, can effectively utilize the depth of the thickness of the chip, increases the number of turns of the coil and only adjusts in the depth of the ditch, does not influence the area of the inductor, and can effectively reduce the area of the inductor structure when the inductor is applied in a circuit.
(2) The number of turns of the coils in the inductance structure and the thickness of the dielectric layer among the multiple layers of coils can be elastically adjusted according to the requirements of the device, the diversity of device design and the variable control of inductance value are realized, and the goal of performance optimization is achieved.
(3) The embedded inductance structure of the invention can ensure the verticality of the side wall of the ditch by adopting the DRIE process, and can measure the etching depth of the substrate by matching with a depth end point detection technology to accurately control the depth of the ditch.
Drawings
Fig. 1 is a schematic diagram of an embedded inductor structure according to a first embodiment and a second embodiment of the present invention;
fig. 2 is a perspective view of a trench of an embedded inductor structure on a substrate according to an embodiment of the present invention;
fig. 3a to 3f are schematic diagrams illustrating a manufacturing process of an embedded inductor structure according to a first embodiment of the invention;
fig. 4 is a schematic diagram of the embedded inductor structures of the third and fourth embodiments of the present invention.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The definitions of the top and bottom relationships of the relative elements and the front and back sides of the figures described herein are understood by those skilled in the art to refer to the relative positions of the components and thus all of the components may be flipped to present the same components and still fall within the scope of the present disclosure.
Example one
Referring to fig. 1, an embedded inductor structure proposed by an embodiment of the present application includes a substrate 1, a coil structure 2, and a second dielectric layer 3. Wherein a trench 11 having a certain depth is formed on the substrate 1, and a plurality of coil structures 2 and a second dielectric layer are stacked in the trench 11 to form an embedded inductor. Wherein the thickness of the substrate 1 is 625-665 μm, and the material of the substrate 1 comprises Si or GaAs. The depth of the trench 11 is 10-100 μm, and the sidewall of the trench 11 has a certain verticality in the substrate 1. Specifically, the included angle between the side wall of the trench 11 and the bottom of the trench 11 is 88-92 °. The coil structures 2 are arranged at intervals from the bottom of the ditch 11 along the depth direction of the ditch 11 to form a multilayer coil, a second dielectric layer 3 is arranged between every two adjacent coil structures 2, and the material of the second dielectric layer 3 comprises SiO2、Si3N4Or polyimide with a thickness of 1 to 10 μm. The coil structure 2 comprises a metal layer 21 in the middle, and an adhesion layer 22 and a first dielectric layer 23 around the metal layer 21, when viewed from a partial cross section of one of the coils, the side wall of the metal layer 21 is sequentially wrapped by the first dielectric layer 23 and the adhesion layer 22, and the coil structure 2 is attached to the side wall of the trench 11 through the adhesion layer 22. Specifically, the adhesion layer 22 is disposed on the sidewall of the trench 11 and at the bottom of the metal layer 21, the first dielectric layer 23 is disposed on the sidewall of the trench 11 and between the adhesion layer 22 for isolation, the side of the metal layer 21 is covered with the first dielectric layer 23, and the metal layer 21, the bottom of the first dielectric layer 23 and the side of the first dielectric layer 23 are both covered with the adhesion layer 22. In each coil structure, the metal layer 21 is in the same plane as the tops of the adhesion layer 22 and the first dielectric layer 23 on the trench sidewalls. The thickness of the first dielectric layer 23 is 100 nm-2000 nm, and the material of the first dielectric layer 23 comprises SiO2Or Si3N4. The adhesion layer 22 is a seed layer, the seed layer comprises TiW/Au or Ti/Cu, and the thickness is 100 nm-2000 nm. As the material of the metal layer 21, Au, Cu, Pt, Ag, Ni, Cu, Ag, Ni, Cu, Ag, Cu, Ag, Ni, Cu, Ag, Cu, Ni, Cu, Ni, Cu, Ni, Cu, Ni, Cu, and Ni, or Cu, or Ag, or one or,At least one of Co, or an alloy or compound containing at least one of the above metals, and the thickness of the metal layer 21 is 1 to 5 μm. Specifically, when the seed layer is TiW/Au, the metal layer 21 is Au; when the seed layer is Ti/Cu, the metal layer 21 is Cu.
Referring to fig. 2, the projected pattern of the trench 11 on the substrate is in the shape of a ring with an opening, and two adjacent spaced coil structures 2 are connected by a metal connecting column 4 to form a multi-layer coil structure. In a specific embodiment, the metal layer is provided with a lead connected with the metal connection column in an extending manner from the annular opening, and preferably, the lead connected with the metal layer 21 and the metal connection column 4 is provided in the annular opening in an extending manner along the horizontal direction, so that the lead can extend outwards or inwards, the metal connection column 4 is prevented from being filled with materials such as seed layers in the manufacturing process, the processing is convenient, and the manufacturing and performance of the inductor structure are not affected.
Referring to the flow diagrams shown in fig. 3a-3f, the above structure is prepared by the following method:
1) referring to FIG. 3a, a first photoresist is coated on a substrate 1, and the photoresist with a coil-shaped pattern is obtained through exposure and development, the coil-shaped pattern comprises a ring shape with an opening, a trench 11 with a depth of 10 μm-100 μm is etched by using DRIE combined with a depth endpoint detection technology, and then oxygen plasma (O) is used2plasma) and solvent cleaning to complete the removal of the photoresist. The thickness of the substrate 1 is 625-665 μm, the material of the substrate 1 comprises Si or GaAs, the Deep Reactive Ion Etching (DRIE) process can etch the vertical and smooth side wall of the hole, the depth end point detection technology can measure the etching depth, a Bosch process of the DRIE and the depth end point detection technology are used for etching a trench with a certain depth and a vertical side wall, and the perpendicularity of the trench 11 can be ensured by combining the two technologies. Specifically, the included angle between the side wall of the trench 11 and the bottom of the trench 11 is 88-92 °.
2) Referring to fig. 3b, an adhesion layer 22 having a thickness of 100nm to 2000nm and a first dielectric layer 23 having a thickness of 100nm to 2000nm are formed on the sidewall and the bottom of the trench 11 using an Atomic Layer Deposition (ALD) processThe process belongs to an atomic layer level covering method, so that a uniform structural surface can be obtained. Wherein the material of the first dielectric layer 23 comprises SiO2Or Si3N4The adhesion layer 22 is a seed layer, and the seed layer comprises TiW/Au or Ti/Cu.
3) Referring to fig. 3c, ICP or RIE is used to remove the bottom first dielectric layer 23 and expose the seed layer 22, the ICP or RIE has high directionality, wherein the ICP process is performed at a low pressure of 1 to 5mTorr, and the etching product is removed by solvent cleaning after etching the bottom first dielectric layer 23 of the trench 11, so that the seed layer below is exposed.
4) And (3 d) coating a second photoresist, exposing and developing to form a photoresist with an electroplating pattern, manufacturing a metal layer 21 with the thickness of 1-5 mu m on the seed layer in an electroplating mode, and forming a first layer coil by taking the metal layer 21 as a main body of the inductance coil. When the seed layer is TiW/Au, the metal layer 21 is Au; when the seed layer is Ti/Cu, the metal layer 21 is Cu. And after the electroplating is finished, removing the photoresist by adopting a solvent cleaning mode.
5) Referring to fig. 3e, the seed layer and the first dielectric layer 23 on the sidewall of the trench 11 above the metal layer 21 are removed by wet etching or plasma, and at this time, the metal layer 21 and the top of the seed layer and the first dielectric layer 23 on the sidewall of the trench are on the same plane.
6) Referring to fig. 3f, depositing a second dielectric layer 3 with a thickness of 1-10 μm by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, coating a third photoresist, exposing and developing to obtain a photoresist covering the seed layer on the metal layer 21 and the trench sidewall and the second dielectric layer 3 above the top of the first dielectric layer 23, etching and removing the excess second dielectric layer 3, and then using oxygen plasma (O)2plasma) and solvent cleaning to complete the removal of the photoresist. Finally depositing a second dielectric layer 3 on the metal layer 21 and the surface of the seed layer on the side wall of the trench and the top of the first dielectric layer 23, wherein the material of the second dielectric layer is SiO2、Si3N4Or a polyimide.
7) Applying a fourth lightPhotoresist etching, exposing, developing to define a contact hole (not shown), etching the contact hole in a preset region on the substrate 1 by dry etching process, wherein the contact hole has a structure with a wide top and a narrow bottom, and oxygen plasma (O)2plasma) and solvent cleaning to remove the photoresist, and finally obtaining a contact hole for connecting the upper coil and the lower coil. The contact hole is arranged at the annular opening of the metal layer 21 and extends along the horizontal direction, and can extend outwards or inwards, so that the materials such as seed layers are prevented from being filled in the manufacturing process, the processing is convenient, and the manufacturing and the performance of the inductance structure are not influenced.
8) Repeating the steps 2-7, and along with the fabrication of the metal layer 21 in the previous layer of coil, filling metal into the contact holes, thereby forming metal connection posts, and finally fabricating a multilayer coil to form the inductor structure shown in fig. 1.
The embedded inductor structure can be obtained by the manufacturing method, the depth of the thickness of the wafer is effectively utilized to obtain the ditch, the number of turns of the inductor can be adjusted flexibly in the ditch as required, the shape of the inductor can be designed and changed as required, the area of the inductor is effectively reduced, the adjustable control of the inductance value is realized, and the performance of the product is further optimized.
Example two
Referring to fig. 1, another embedded inductor structure is different from the first embodiment in that the adhesion layer is Si, and a Salicide (Salicide) process is used to fabricate the metal layer in step 4. Therefore, in the case where the adhesion layer is Si, the metal layer is deposited on the surface of the Si layer, and the metal layer is in contact with the surface of the Si layer. And performing thermal process treatment to form a silicide layer on the contact metal layer and the surface of the silicon layer. In step 5, the first dielectric layer and the Si layer on the trench sidewall above the silicide layer are removed, wherein the metal layer can be selected.
EXAMPLE III
Referring to fig. 4, another embedded inductor structure, which is different from the first embodiment, is an air cavity 5 between two adjacent spaced coil structures. Specifically, in step 6, a sacrificial material is filled between two adjacent spaced coil structures, and the second dielectric layer is set as a sacrificial layer. In the manufacturing method, step 8 further comprises: after the fabrication of the upper layer of coils is completed, an air cavity 5 is formed between the adjacent spaced upper and lower layers of coils by opening holes and removing the sacrificial layer. The sacrificial material may be selected to be SOG.
Example four
Referring to fig. 4, another embedded inductor structure differs from the first embodiment in that the adhesion layer is Si, and an air cavity 5 is formed between two adjacent spaced coil structures. First, since the adhesion layer is Si, a Salicide (Salicide) process is used to fabricate the metal layer in step 4. The metal layer is deposited on the surface of the Si layer and is in contact with the surface of the Si layer. And performing thermal process treatment to form a silicide layer on the contact metal layer and the surface of the silicon layer. In step 5, the first dielectric layer and the Si layer on the trench sidewall above the silicide layer are removed, wherein the metal layer can be one of Ti, Co, and Ni.
And 6, filling a sacrificial material between two adjacent and spaced coil structures, and setting the second dielectric layer as a sacrificial layer. In the manufacturing method, step 8 further comprises: after the fabrication of the upper layer of coils is completed, an air cavity 5 is formed between the adjacent spaced upper and lower layers of coils by opening holes and removing the sacrificial layer. The sacrificial material may be selected to be SOG.
The above embodiments are only used to further illustrate the embedded inductor structure and the manufacturing method thereof, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.
Claims (10)
1. The utility model provides an embedded inductance structure, its characterized in that, including the substrate of the irrigation canals and ditches that have certain degree of depth be equipped with the edge in proper order on the irrigation canals and ditches bottom the depth direction multilayer spaced coil structure of irrigation canals and ditches, coil structure include the metal level and first dielectric layer and adhesion layer around the metal level, first dielectric layer and adhesion layer wrap up in proper order the lateral wall of metal level, coil structure passes through the adhesion layer is attached to on the lateral wall of irrigation canals and ditches, the adhesion layer is still cladding in the metal level with the bottom surface of first dielectric layer, adjacent spaced two coil structure passes through the metal connecting post and links to each other.
2. The embedded inductor structure of claim 1, wherein a second dielectric layer or an air cavity is disposed between two adjacent spaced coil structures, the thickness of the second dielectric layer or the height of the air cavity is 1-10 μm, and the material of the second dielectric layer is SiO2、Si3N4Or a polyimide.
3. The embedded inductor structure of claim 1, wherein the adhesion layer is Si or a seed layer, and the material of the seed layer comprises TiW/Au or Ti/Cu.
4. The embedded inductor structure of claim 1, wherein the thickness of the first dielectric layer is 100nm to 2000nm, and the material of the first dielectric layer comprises SiO2Or Si3N4。
5. The embedded inductor structure of claim 1, wherein the depth of the trench is 10 μm to 100 μm, and an angle between the sidewall of the trench and the bottom of the trench is 88 ° to 92 °.
6. The embedded inductor structure of claim 1, wherein the metal layer has a thickness of 1-5 μm, and the material of the metal layer comprises at least one of Au, Cu, Pt, Ag, Ni, Co, or an alloy or compound containing at least one of the above metals.
7. The embedded inductor structure of claim 1, wherein a projected pattern of the trench on the substrate is a ring shape having an opening, and the metal layer extends from the opening of the ring shape and is provided with a lead connected to the metal connection stud.
8. A manufacturing method of an embedded inductor structure is characterized by comprising the following steps:
1) etching a trench with a certain depth on a substrate by using DRIE combined with a depth endpoint detection technology;
2) forming an adhesion layer and a first dielectric layer on the side wall and the bottom of the trench by adopting an atomic layer deposition process;
3) removing the first dielectric layer at the bottom and exposing the adhesion layer;
4) manufacturing a metal layer on the adhesion layer to form a first layer of coil;
5) removing the adhesion layer and the first dielectric layer on the side wall of the trench above the metal layer;
6) depositing a second dielectric layer on the metal layer;
7) etching a contact hole in a preset area on the substrate;
8) and (5) repeating the steps 2-7, and manufacturing a multilayer coil to form an inductance structure.
9. The method for manufacturing the embedded inductor structure of claim 8, wherein the thickness of the second dielectric layer is 1-10 μm, and the second dielectric layer is made of SiO2、Si3N4Polyimide or sacrificial material; when the second dielectric layer is a sacrificial material, step 8 further includes: and forming an air cavity between the adjacent spaced upper and lower coils by opening the hole and removing the sacrificial material after the fabrication of the upper coil is completed.
10. The method for manufacturing the embedded inductor structure according to claim 8, wherein the adhesion layer is Si or a seed layer, and when the adhesion layer is the seed layer, the material of the seed layer includes TiW/Au or Ti/Cu, and the metal layer is manufactured by using an electroplating process in the step 4; and when the adhesion layer is Si, the metal layer is manufactured by adopting a self-aligned silicide process in the step 4.
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| US6362012B1 (en) * | 2001-03-05 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications |
| CN105470152A (en) * | 2014-09-12 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Method for improving RF performance of integrated passive high-impedance substrate copper inductor |
| CN106783019A (en) * | 2016-12-02 | 2017-05-31 | 南通沃特光电科技有限公司 | A kind of low interference induction structure |
| US20190057942A1 (en) * | 2017-08-16 | 2019-02-21 | Texas Instruments Incorporated | Integrated circuit with an embedded inductor or transformer |
| CN216435933U (en) * | 2021-10-27 | 2022-05-03 | 泉州市三安集成电路有限公司 | Embedded inductance structure |
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2021
- 2021-10-27 CN CN202111256531.3A patent/CN114094013B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362012B1 (en) * | 2001-03-05 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications |
| CN105470152A (en) * | 2014-09-12 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Method for improving RF performance of integrated passive high-impedance substrate copper inductor |
| CN106783019A (en) * | 2016-12-02 | 2017-05-31 | 南通沃特光电科技有限公司 | A kind of low interference induction structure |
| US20190057942A1 (en) * | 2017-08-16 | 2019-02-21 | Texas Instruments Incorporated | Integrated circuit with an embedded inductor or transformer |
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