CN114093405A

CN114093405A - Memory data erasing method, memory device and memory system

Info

Publication number: CN114093405A
Application number: CN202111239854.1A
Authority: CN
Inventors: 张祎; 李博
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2022-02-25

Abstract

The embodiment of the application discloses a memory data erasing method, a memory device and a memory system. The method comprises the following steps: acquiring the number N of erasing pulses for erasing data of a target storage block; wherein N is an integer greater than or equal to 1; sequentially applying erasing pulses to the storage blocks according to the number N of the erasing pulses; and releasing the erasing charges of the memory block after applying the Nth erasing pulse.

Description

Memory data erasing method, memory device and memory system

Technical Field

The embodiment of the application relates to the field of memories, and relates to, but is not limited to, a memory data erasing method, a memory device and a memory system.

Background

The erasing process of the memory data comprises the steps of applying erasing pulses to erase the data of the memory, erasing and discharging electrons in the channel after erasing, erasing and verifying after erasing and discharging, and if the erasing and verifying succeeds, the erasing operation is proved to be completed. If the erase verification is unsuccessful, the erase flow is required to be continued until the erase verification is successful.

A successful erase operation often requires multiple passes through the erase procedure described above, resulting in an excessively long erase time.

Disclosure of Invention

In view of the above, embodiments of the present application provide a method for erasing memory data, a memory device and a memory system.

In a first aspect, an embodiment of the present application provides a method for erasing memory data, where the method includes:

acquiring the number N of erasing pulses for erasing data of a target storage block; wherein N is an integer greater than or equal to 1;

sequentially applying erasing pulses to the target storage block according to the number N of the erasing pulses;

and releasing the erasing charge of the target storage block after applying the Nth erasing pulse.

In some embodiments, the method further comprises:

applying a verify pulse to the target memory block after releasing the erase charge;

and determining whether the data of the target storage block is successfully erased or not according to a verification result corresponding to the verification pulse. In some embodiments, the sequentially applying the erase pulse to the target memory blocks according to the erase pulse N includes:

applying an ith erase pulse to the target memory block; wherein i is an integer greater than or equal to 1 and less than or equal to N;

if the i is smaller than N, applying an i +1 th erasing pulse to the target storage block, wherein the i +1 is smaller than or equal to N; the voltage value of the (i +1) th erasing pulse is larger than that of the ith erasing pulse;

if i is equal to N, application of the erase pulse is stopped.

In some embodiments, the applying the i-th erase pulse to the target memory block includes:

and if the ith erasing pulse is the first erasing pulse, boosting the voltage to the voltage amplitude of the first erasing pulse in a step boosting mode.

and if the ith erasing pulse is not the first erasing pulse, boosting the voltage to the voltage amplitude of the ith erasing pulse on the basis of the voltage amplitude of the (i-1) th erasing pulse.

In some embodiments, the releasing the erase charge of the target memory block includes:

and releasing the erasing charges in each memory cell of the target memory block by turning on the bit line of the target memory block.

In some embodiments, the method further comprises:

and determining the number N of the erasing pulses by performing an erasing test on the memory.

In some embodiments, said determining the number of erase pulses N by performing an erase test on said memory comprises:

sequentially applying k times of erasing pulses to the specified test memory block; wherein k is an integer greater than or equal to 1;

releasing the erase charge of the test memory block;

applying a verification pulse to the test storage block to obtain a verification result;

and in response to the verification result being successful in erasing, determining the value of k as the number N of erasing pulses.

In some embodiments, the determining the number N of erase pulses by performing an erase test on the memory further comprises:

and in response to the verification result being an erase failure, sequentially applying the erase pulses k +1 times again for the test memory block.

In some embodiments, the erase pulse is generated by a pulse generation module and is for application to a substrate of a memory block.

In a second aspect, an embodiment of the present application provides a storage apparatus, including:

a memory cell array including a plurality of memory cells;

a peripheral circuit configured to:

In a third aspect, an embodiment of the present application provides a storage system, including: a controller and a storage device;

the peripheral circuitry of the memory device is configured to perform the method of any of the embodiments described above.

According to the technical scheme of the embodiment of the application, in the process of erasing the data of the memory, the number of erasing pulses is obtained, then N times of erasing pulses are continuously and sequentially applied to the target memory block of the memory, and erasing discharge is carried out after the N times of erasing pulses. Therefore, compared with the process of performing discharging and verifying once when each sequential erasing pulse is applied, the data erasing time of the memory is effectively reduced, and the performance of the memory is improved.

Drawings

Fig. 1 is a flowchart of a method for erasing memory data according to an embodiment of the present disclosure;

FIG. 2 is a flowchart of another method for erasing data in a memory according to an embodiment of the present disclosure;

FIG. 3 is a flowchart of another method for erasing data in a memory according to an embodiment of the present disclosure;

FIG. 4 is a diagram of the components of a control module according to an embodiment of the present application;

FIG. 5 is a flow chart of a method for erasing memory data;

FIG. 6 is a waveform diagram of an erase process of an erase method of memory data;

FIG. 7 is a waveform diagram illustrating an erasing process of an erasing method of memory data according to an embodiment of the present disclosure;

FIG. 8 is a block diagram illustrating an erase verification process for erasing data in a memory according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a memory device according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a memory system according to an embodiment of the present application.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

An embodiment of the present application provides a method for erasing memory data, as shown in fig. 1, the method includes:

s101, acquiring the number N of erasing pulses for erasing data of a target storage block; wherein N is an integer greater than or equal to 1;

step S102, sequentially applying erasing pulses to the target storage block according to the number N of the erasing pulses;

and step S103, releasing the erasing charges of the target storage block after the Nth erasing pulse is applied.

The Memory in the embodiment of the present application may be a NAND Flash Memory (NAND Flash Memory), a NOR Flash Memory (NOR Flash Memory), a Dynamic Random Access Memory (DRAM), and the like, where the NAND Flash Memory is taken as an example, and a block is a minimum erase unit of the NAND. The erase method is performed for a target memory block of the memory. The target memory block is a memory block in which data to be erased is stored, and includes a plurality of memory cells.

Here, the number of erase pulses N, i.e., the number of pulses by which data can be successfully erased after applying N erase pulses, may have different amplitudes each, for example, the voltage amplitude is sequentially increased. The charges stored in the floating gate layer or the CT (Charge Trap) layer of each memory cell in the memory are gradually shifted out under the action of multiple erase pulses, thereby implementing the erasure of data.

In the embodiment of the present application, the number N of erase pulses for erasing data in the target memory block may be pre-stored in the memory. The number of erase pulses N may be different for different products, as the number of erase pulses N is affected by the product process, materials and performance. Therefore, the number of erase pulses can be determined by factory test of the memory before factory shipment, and is taken as a fixed attribute of the memory.

Therefore, in the embodiment of the present application, before erasing data of the target memory block, the number N of erase pulses may be obtained. Then, N erase pulses are applied to the target memory block according to the number N of erase pulses. Since the number of erase pulses N is preset in advance, it is not necessary to perform charge discharging and erase verification after each erase pulse, but the data erase is completed after N erase pulses are consecutively applied. Of course, after completing the N times of erase pulses, operations such as charge release and verification can still be performed to confirm whether the erase was successful.

Compared with the erasing mode of a cycle of erasing pulse erasing-discharging-verifying every time, the method reduces the block erasing time, improves the performance of the product and further improves the competitiveness of the product.

In some embodiments, as shown in fig. 2, the method further comprises:

step S201, after the erasing charges are released, a verification pulse is applied to the target storage block;

step S202, determining whether the data of the target storage block is successfully erased according to the verification result corresponding to the verification pulse.

After each application of the erase pulse, a portion of the charge moves from the floating gate layer or CT into the channel. After the nth erasing pulse is applied, electrons in the channel can be released through erasing discharge, so that subsequent erasing verification is facilitated.

The erase verification is performed by applying a verification voltage to the control gate for verifying whether the charges stored in the floating gate layer or the CT are successfully removed after the nth erase. If the verification voltage is larger than the current actual threshold voltage of the memory cell, the memory cell is conducted; if the verification voltage is less than the current actual threshold voltage of the memory cell, the memory cell is in a cut-off state.

For example, when the first verify voltage Vr1 is applied to the word line WL of the target memory block, the target memory block in the erase state E may be turned on while the target memory block in the first program state P1 or other program state is turned off. When the target memory block is applied with the first verification voltage, the target memory block is conducted, and current can flow through the target memory block, which indicates that the target memory block is successfully erased; if the target memory block is not conducted, no current flows through the target memory block, which indicates that the target memory block is not successfully erased and needs to be erased continuously.

It should be noted that in the embodiment of the present application, the erase operation of most memory cells can be completed by N erase pulses applied successively. However, since the characteristics of the device may not be uniform, there may still be some memory cells that are not successfully erased after N erase pulses. Therefore, after erasing, a discharge and verification process can be adopted to determine whether the erasing is successful, and if the data of the memory cells are not successfully erased, one or more times of erasing pulses can be applied again for erasing, namely, an erasing pulse-discharge-verification pulse circulating operation.

In some embodiments, the sequentially applying the erase pulse to the target memory blocks according to the erase pulse N includes:

if i is equal to N, application of the erase pulse is stopped.

The analog module for generating the erase pulse may count the number of erase pulses generated by the analog module using a counter every time an erase pulse is generated. Illustratively, the initial count value is 0, the count value is increased by 1 after the erase pulse is applied to the PN well, and the count value is i after the ith erase pulse is applied to the PN well.

Before applying an erase pulse to the PN well of a target erase block, the number of erase pulses i to which the target erase block has been applied may be compared with the value N of the number of target erase pulses.

When the count value i is less than the target erase count value N, the analog module may continue to apply the (i +1) th erase pulse to the target erase block.

The voltage value of the (i +1) th erase pulse is greater than that of the (i) th erase pulse, and in the case of being applied to the PN well in the (i) th erase operation, if there is a memory cell on which the erase operation has not been normally performed, Vera (i) may be raised to Vera (i +1) to perform the erase operation again.

The voltage value of the erase pulse passing through the (i +1) th erase pulse is larger than that of the ith erase pulse, so that the voltage difference between the control gate and the PN well region is gradually increased, and finally the charges stored in the floating gate layer or the CT are shifted out.

When the count value i is equal to the target erase count value N, the analog module stops applying erase pulses to the target erase block.

In this way, the erase pulses can be sequentially applied in a counting manner until the erase pulses are continuously applied for N times, and the erase pulse voltage which is gradually increased for N times is applied to the target erase block, so that the charges stored in the floating gate layer or the CT can be shifted out, and the target erase block can be erased.

if the ith erase pulse is the first erase pulse, the voltage may be boosted to the voltage amplitude of the first erase pulse from a lower voltage, for example, 5V, by a step-up method before the first erase pulse.

The voltage value of the Erase Pulse may be generated by an initial voltage VL and an Incremental Step Pulse (ISPE) Erase, wherein the initial voltage VL is a voltage applied to the PN well by the first Erase Pulse and is generated by a charge pump in the analog module.

When the ith erase pulse is the first erase pulse, the erase pulse reaches an initial voltage VL, for example 15V. The voltage is boosted to the voltage value of the first erase pulse as the initial voltage VL by means of step boosting of the charge pump from a lower voltage, for example, 5V. The magnitude of the increased voltage per step boost may be different, e.g., the magnitude of the initial increase is larger, and the magnitude of the increase is smaller as the target magnitude is reached; it is also possible to make the magnitude of the voltage increase equal for each step boost, i.e. the magnitude of each increase is the same.

In this way, by boosting the first erase pulse in a stepwise manner, rather than directly boosting the first erase pulse in a square wave manner, it is possible to reduce the occurrence of an over-erase phenomenon in which the threshold voltage Vt of the target memory block shifts in the positive direction.

When the ith erase pulse is not the first erase pulse, it is not necessary to perform step boosting from a lower voltage, for example, 5V, as in the first erase pulse. But boosting to the ith erasing voltage amplitude in a one-step boosting mode on the basis of the voltage amplitude of the (i-1) th erasing pulse. Wherein, when the ith erase pulse is not the first erase pulse, the magnitude of each step boosting increase may be the same. The incremental magnitude of the incremental step pulse erase is the i-th erase voltage value Vera (i) minus the i-1 th erase voltage value Vera (i-1).

Thus, when the ith erasing pulse is not the first erasing pulse, the erasing pulse voltage can be boosted to the ith erasing pulse value by one incremental step pulse erasing boosting on the basis of the (i-1) th erasing pulse, and the voltage does not need to be boosted to the ith erasing pulse value by multiple incremental step pulse erasing boosting from 5V. Therefore, the boosting time of the ith erasing pulse can be saved, and the erasing time of the storage block is further saved.

Since charges move from the floating gate layer or CT into the channel during one erase, a large amount of charges are accumulated in the channel after N erase pulses are performed on the target memory block, resulting in an increase in the threshold voltage between the source and drain. After the erase pulse is completed, an erase discharge operation is performed to discharge the substrate and gate to a target voltage level to allow a subsequent read or verify operation.

In some embodiments, as shown in fig. 3, the method further comprises:

step S301, determining the number N of erase pulses by performing an erase test on the memory.

The number of erase pulses N may be different for different products, as the number of erase pulses N is affected by the product process, materials and performance. Therefore, the number of erase pulses can be determined by factory test of the memory before factory shipment, and is taken as a fixed attribute of the memory.

The test method of acquiring the number of erase pulses may employ a silicon test.

For example, N is an integer of 1,2, and 3 …, that is, 1 erase pulse-discharge, 2 erase pulse-discharge cycles, 3 erase pulse-discharge cycles, and the like are respectively applied to the sample memory until the erase is successful, and the number of erase pulses required for erasing the data in the sample memory is verified.

In practical application, an erase command can be applied to the test erase block, a result of whether the erase was successful or not can be returned after a specified number of erase pulses are continuously applied, when a first signal of successful erase is returned, the number of currently used erase pulses is checked, and the number of erase pulses is defined as N. If the verification result of the erase failure is returned after the erase pulse is continuously applied for the specified times, the test erase block can be programmed again, and the erase process is performed after the specified times are updated until an erase success signal is returned.

Therefore, the required number N of the erasing pulses can be determined in advance by a testing method and pre-stored in the memory, and the determined number N of the erasing pulses can be directly obtained in the using process of the memory, so that the erasing can be directly performed by adopting the method in the embodiment.

releasing the erase charge of the memory block;

The test method for acquiring the number of erase pulses may further be that erase pulses are sequentially applied k times to a specified test memory block, then verification is performed, if verification is successful, the number of erase pulses N may be determined, and if verification fails, testing needs to be performed again.

For example, k is first taken to be 1, that is, an erase verification is performed after 1 erase pulse is applied to the test memory block, and the verification result obtained at this time is an erase failure. Then, taking k as 2 again, continuously applying 2 erasing pulses to the test storage block again, and performing erasing verification again; and if the obtained verification result is that the erasing fails, taking k as 3 again, continuously applying 3 erasing pulses to the tested storage block again, performing erasing verification again, and so on until the verification result is that the erasing is successful, and defining the corresponding k value as the number N of erasing pulses of the storage block.

It should be noted that, in the verification process, each time a new k value is taken for erase verification, different test memory blocks in the same memory may be selected, but the test memory blocks should have the same manufacturing process parameters and materials. Optionally, the same test block may be tested repeatedly, but it should be noted that the test block may be reprogrammed with data after each erase, so that the process conditions for each erase verify are comparable.

Therefore, the value of N can be determined only through a few simple erasing and verifying processes, so that the number of erasing pulses of the memory can be directly called in the subsequent use.

In the process of erasing and verifying the test storage block, if the verification result is that erasing fails, the current k value cannot be used as the final number N of erasing pulses, and the k value needs to be updated and verified again.

For example, if k is 1, the erase verification is performed after 1 erase pulse is applied, and the obtained verification result is an erase failure, in this case, the value of k needs to be updated, and the verification is performed again by taking k +1, that is, k 2. At this time, the erase pulse is continuously applied to the test memory block 2 times again, erase verification is performed, and if the obtained verification result is that erase has failed, the value k is updated again, and k is taken to be k + 1.

And when the value of k reaches k being 5, continuously applying the erasing pulse for 5 times again, and then verifying, wherein the verification result is that the erasing is successful, and the k value does not need to be updated. The value of k at this time is the number of pulses that can be successfully erased, and therefore, k can be determined to be the final number of erase pulses at this time.

By using the method for updating the k value to verify, the multiple erasing verification processes of the test storage block can be quickly realized by using simple cycle operation, and the final N value is obtained. The method is easy to implement and can be applied to precise verification of each memory or each batch of memories in mass production due to the convenience of programming operation.

The erasing pulses used in the erasing process can be generated by a pulse generating module. The pulse generation module includes two parts, one is a regulator (regulator) that provides a regulated voltage, and one is a Charge Pump (Charge Pump) that provides an incrementally stepped pulse boost. The pulse generation module is a part of the control module, and the control module further comprises a core module, a pulse generation module and a logic module. As shown in fig. 4, the control module comprises a core module 401, a pulse generation module 402 and a logic module 403, wherein the pulse generation module 402 may include a regulator, a charge pump, and the like. The mutual action among the core module, the pulse generation module and the logic module controls the erasing process, and the action and the mutual relation among the core module, the pulse generation module and the logic module are as follows:

the core module generates control signals of other voltage sources, such as word line control signals in the direction X and bit line control signals in the direction Y of the three-dimensional memory.

The pulse generation module is used for generating bias voltages such as a conduction voltage and an erasing voltage, and mainly generates different voltage sources in an erasing process. The regulator can be used in a charge pump to generate an erase voltage boosted by incremental step pulses to act on the PN well for a period of time.

The logic module is used for generating a digital control signal, and the digital control signal acts on the core module.

The core module is a medium for connecting the logic module and the pulse generation module, and the core module can conduct a digital control signal generated by the logic module to the pulse generation module to control whether to allow the voltage in the pulse generation module to be applied to the memory block, the process of discharging, the allowable on-time of each signal, where to allow the application, where to disallow the application, and the like.

The logic module controls whether the control signal of the core module can be used on the pulse generation module. The erase pulse generated by the erase module is applied to the substrate of the memory device to make the substrate have a high voltage relative to the control gate, and charges gradually move from the floating gate layer or the CT to the channel under the erase pulse of multiple increments, so that data is erased.

The embodiments of the present application also provide the following examples:

in one embodiment, as shown in FIG. 5, the erase flow for a memory block is:

s501: applying an erase pulse to the memory block;

s502: erasing and discharging the memory block;

s503: applying an erasing verification pulse to the storage block to perform erasing verification;

and repeating the above processes until the erasing verification is successful, and finishing the erasing process.

The waveform diagram of the erase process is shown in fig. 6. In order to prevent the over-erase phenomenon from affecting the device performance, the erase voltage applied for the first time in the erase process should not be too large, and as shown in fig. 6, the erase voltage should be increased slowly from the first erase voltage, and the second to nth erasing should be performed until the erase is successful.

However, since the first applied erase voltage is not too large, the first several erase verification results are often failed, but multiple post-erase discharges and erase verification processes are performed, which affects the block erase time.

In order to solve the above problem, the embodiment of the present application provides the following erasing method:

the waveform diagram of the erase process is shown in fig. 7. Erasing of the block data is achieved by sequentially applying a plurality of successive erase pulses of 1,2,3, etc. to the block. After applying multiple erase pulses, one erase discharge may be performed and a verify pulse may be applied for verification to determine that the data erase of the current memory block is successful.

Therefore, compared with a mode of erasing discharge and verification after each erasing pulse is applied, the method in the embodiment of the application can effectively save erasing time and improve the performance of the memory.

In the embodiment of the present application, the number N of erase pulses obtained can be verified as follows:

as shown in FIG. 8, erase is first performed using discrete erase pulses, each followed by a verify until the erase is successful. In this process, the number of consecutive erase pulses is N equal to 0, and the current erase time is recorded.

And then, adopting continuous erasing pulse number N to be 2, continuously applying discontinuous erasing pulses after the verification is unsuccessful until the erasing is successful, and recording the current erasing time.

And circulating the steps until all the erasing pulse numbers are continuously applied, for example, the continuous erasing pulse number is N-5, at the moment, the erasing verification is successful, and the current erasing time is recorded.

Thus, the following test results were obtained:

the minimum number of erase pulses of the test memory block was obtained by the silicon test to be 5, i.e., N is 5.

Improved block erase times were obtained for the 5 erase pulses removing the middle 1-4 erase discharges and erase verify processes, and as a result, it can be seen that the test erase block required the least block erase time when all 4 erase discharges and erase verify processes in the 5 erase pulses were removed, as shown in table 1 below.

TABLE 1

The 4 erase discharges and erase verify processes involved in the 5 erase pulses can be removed in practical applications, which saves more block erase time. By using the target block erasing method of the embodiment of the application, the block erasing time can be reduced, and other performances of the storage block cannot be influenced.

As shown in fig. 9, an embodiment of the present application provides a storage apparatus 900, where the apparatus 900 includes:

a memory cell array 910 including a plurality of memory cells 911;

peripheral circuitry 920 configured to:

In some embodiments, the storage device may be a non-volatile memory product such as a NAND chip.

As shown in fig. 10, an embodiment of the present application provides a storage system 1000, where the storage system 1000 includes: a controller 1001 and a storage device 1002;

In some embodiments, the storage system may be an SSD (Solid State Disk) or other product, and may also be an electronic device including a storage device, such as a computer device.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of erasing memory data, the method comprising:

2. The method of claim 1, further comprising:

and determining whether the data of the target storage block is successfully erased or not according to a verification result corresponding to the verification pulse.

3. The method of claim 1, wherein the sequentially applying erase pulses to the target memory blocks according to the erase pulse N comprises:

if i is equal to N, application of the erase pulse is stopped.

4. The method of claim 3, wherein applying the i-th erase pulse to the target memory block comprises:

5. The method of claim 3, wherein applying the i-th erase pulse to the target memory block comprises:

6. The method of claim 1, wherein the releasing the erase charge of the target memory block comprises:

7. The method of claim 1, further comprising:

8. The method of claim 7, wherein said determining the number of erase pulses, N, by performing an erase test on the memory comprises:

releasing the erase charge of the test memory block;

9. The method of claim 8, wherein said determining the number N of erase pulses by performing an erase test on said memory further comprises:

10. A storage device, the device comprising:

a memory cell array including a plurality of memory cells;

a peripheral circuit configured to:

11. A storage system, comprising: a controller and a storage device;

peripheral circuitry of the memory device is configured to perform the method of any of claims 1 to 9.