CN114115412A

CN114115412A - System-on-chip, dynamic voltage frequency adjusting circuit and adjusting method

Info

Publication number: CN114115412A
Application number: CN202111340044.5A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Bi Ren Technology Co ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-03-01
Anticipated expiration: 2041-11-12
Also published as: CN114115412B

Abstract

A system-on-chip, a dynamic voltage frequency adjustment circuit, and a dynamic voltage frequency adjustment method, the system-on-chip comprising: at least one dynamic voltage frequency adjustment circuit, wherein the system-on-chip includes at least two power domains, the at least one dynamic voltage frequency adjustment circuit configured to enable dynamic adjustment of an operating voltage and a clock frequency of each of the at least two power domains. The system-level chip can meet the power requirements of different power domains in time when the system-level chip operates, and reduces the energy consumption of the system-level chip on the premise of meeting the performance of the system-level chip.

Description

System-on-chip, dynamic voltage frequency adjusting circuit and adjusting method

Technical Field

Embodiments of the present disclosure relate to a system-on-chip, a dynamic voltage frequency adjustment circuit, and a dynamic voltage frequency adjustment method.

Background

As the demand for Computing power of chips increases, such as High Performance Computing (HPC) chips or artificial intelligence accelerator (AI architecture) chips, the power consumption of these types of High Performance chips also increases. However, for example, in a usage scenario where peak performance is required, the operating power of the chip may exceed the peak limit (peak limit) of the system design or chip design, which may cause system shutdown (shut down), handling core operation abnormality, and even chip damage. Alternatively, unnecessary power consumption may occur, for example, in low performance use scenarios, because the operating power of the chip cannot be immediately turned down. Therefore, how to dynamically adjust the operating voltage and the operating frequency of the chip in real time is one of the currently important issues in the field. However, in a scenario where higher power or lower power is required, the conventional chip only meets the current power requirement by setting a fixed voltage and a fixed frequency, but lacks flexibility in adjustment and has a drawback of too slow response speed. Therefore, the conventional chip often suffers performance loss or power waste during the voltage and frequency adjustment process.

Disclosure of Invention

Some embodiments of the present disclosure provide a system-on-chip, including: at least one dynamic voltage frequency adjustment circuit, wherein the system-on-chip includes at least two power domains, the at least one dynamic voltage frequency adjustment circuit configured to enable dynamic adjustment of an operating voltage and a clock frequency of each of the at least two power domains.

For example, some embodiments of the present disclosure provide a system-on-chip wherein the at least one dynamic voltage frequency adjustment circuit comprises a first dynamic voltage frequency adjustment circuit configured to enable dynamic adjustment of operating voltages and clock frequencies of a plurality of the at least two power domains.

For example, in a system-on-chip provided in some embodiments of the present disclosure, the first dynamic voltage frequency adjustment circuit includes: a frequency dividing circuit configured to receive a first clock signal and output a plurality of second clock signals having a plurality of clock frequencies; a multiple-input multiple-output switch circuit configured to receive the plurality of second clock signals and output a plurality of third clock signals for the plurality of power domains, wherein the plurality of third clock signals are in one-to-one correspondence with the plurality of power domains; and a control circuit coupled to the frequency divider circuit, the multiple-input multiple-output switch circuit and the voltage regulator circuit; wherein the control circuit is configured to output a voltage management signal to the voltage regulation circuit and output a selection signal to the multiple input multiple output switch circuit when the system-on-chip performs a voltage frequency regulation operation, the voltage regulation circuit is configured to regulate the operating voltages provided to the plurality of power domains according to the voltage management signal when the system-on-chip performs a voltage frequency regulation operation, and the multiple input multiple output switch circuit is configured to output the plurality of third clock signals to the plurality of power domains according to the selection signal.

For example, some embodiments of the present disclosure provide a system-on-chip wherein the at least one dynamic voltage frequency adjustment circuit includes a second dynamic voltage frequency adjustment circuit configured to dynamically adjust an operating voltage and a clock frequency of one of the at least two power domains.

For example, some embodiments of the present disclosure provide a system-on-chip, wherein the at least one dynamic voltage and frequency adjustment circuit is configured to transmit a signal to each of the at least two power domains through a level shifting circuit, and each of the at least two power domains is configured to output a signal through a level shifting circuit having a clamping function.

Some embodiments of the present disclosure provide a dynamic voltage frequency adjustment circuit applied to a system-on-chip including a plurality of power domains, wherein the dynamic voltage frequency adjustment circuit includes: a frequency dividing circuit configured to receive a first clock signal and output a plurality of second clock signals having a plurality of clock frequencies; a multiple-input multiple-output switch circuit configured to receive the plurality of second clock signals and output a plurality of third clock signals for the plurality of power domains, wherein the plurality of third clock signals are in one-to-one correspondence with the plurality of power domains; and a control circuit coupled to the frequency divider circuit, the multiple-input multiple-output switch circuit and the voltage regulator circuit; wherein the control circuit is configured to output a voltage management signal to the voltage regulation circuit and output a selection signal to the multiple input multiple output switch circuit when the system-on-chip performs a voltage frequency regulation operation, the voltage regulation circuit is configured to regulate the operating voltages provided to the plurality of power domains according to the voltage management signal when the system-on-chip performs a voltage frequency regulation operation, and the multiple input multiple output switch circuit is configured to output the plurality of third clock signals to the plurality of power domains according to the selection signal.

For example, in a dynamic voltage frequency adjustment circuit provided in some embodiments of the present disclosure, in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment operation corresponding to at least one power domain of the plurality of power domains, the control circuit first outputs the voltage management signal to the voltage adjustment circuit, so that the voltage adjustment circuit adjusts the operating voltage of the at least one power domain according to the voltage management signal, and when the operating voltage of the at least one power domain is adjusted to be stable, the control circuit then outputs the selection signal to the multiple input multiple output switch circuit, so that the multiple input multiple output switch circuit adjusts the clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal.

For example, in a dynamic voltage frequency adjustment circuit provided in some embodiments of the present disclosure, in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment operation corresponding to at least one power domain of the plurality of power domains, the voltage adjustment circuit first performs a step-up operation on an operating voltage of the at least one power domain, and when the operating voltage of the at least one power domain is adjusted to be stable, the mimo switch circuit performs a step-up operation on a clock frequency of the at least one third clock signal output to the at least one power domain in a low clock frequency to high clock frequency and switching in multiple stages.

For example, in a dynamic voltage frequency adjustment circuit provided in some embodiments of the present disclosure, in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, the control circuit first outputs the selection signal to the multiple input multiple output switch circuit, so that the multiple input multiple output switch circuit adjusts down a clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal, and when the clock frequency of the at least one third clock signal of the at least one power domain is adjusted down to be stable, the control circuit outputs the voltage management signal to the voltage adjustment circuit, so that the voltage adjustment circuit adjusts down an operating voltage of the at least one power domain according to the voltage management signal.

For example, in a dynamic voltage frequency adjustment circuit provided in some embodiments of the present disclosure, in a case where the voltage frequency adjustment operation includes a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, the mimo switch circuit first gradually adjusts down a clock frequency of the at least one third clock signal output to the at least one power domain in a high clock frequency to low clock frequency and in a multi-stage switching manner, and when the clock frequency of the at least one third clock signal of the at least one power domain is adjusted down to be stable, the voltage adjustment circuit then gradually adjusts down an operating voltage of the at least one power domain.

For example, in some embodiments of the present disclosure, a dynamic voltage and frequency adjustment circuit is provided, where the control circuit includes: the state machine circuit is coupled with the frequency division circuit and the MIMO switch circuit; and register circuitry coupled to the state machine circuitry; the register circuit is configured to output a control signal to the state machine circuit when the system-on-chip performs the voltage frequency adjustment operation, and the state machine circuit is configured to output the voltage management signal to the voltage adjustment circuit and output the selection signal to the multiple-input multiple-output switch circuit according to the control signal when the system-on-chip performs the voltage frequency adjustment operation.

For example, in a dynamic voltage frequency adjustment circuit provided in some embodiments of the present disclosure, the voltage management signal includes a voltage regulation trigger signal and regulation target voltage information, and the voltage regulation circuit is configured to regulate an operating voltage of at least one of the plurality of power domains to a target voltage according to the voltage regulation trigger signal regulation and the regulation target voltage information when the system-on-chip performs a voltage frequency regulation operation.

For example, in some embodiments of the present disclosure, the state machine circuit is further configured to output a frequency division signal to the frequency division circuit according to the control signal when the system-on-chip performs the voltage frequency adjustment operation, so that the frequency division circuit outputs the plurality of second clock signals according to the frequency division signal.

For example, in some embodiments of the present disclosure, the multiple-input multiple-output switch includes a plurality of multiplexers corresponding to the plurality of power domains one to one, and each of the plurality of multiplexers is configured to receive at least a portion of the plurality of second clock signals and output a third clock signal for the power domain corresponding to the each multiplexer.

For example, in some embodiments of the present disclosure, the control circuit is configured to receive an interrupt signal output by the voltage regulating circuit, and determine whether to generate the voltage management signal and the selection signal according to the interrupt signal.

For example, in a dynamic voltage frequency adjustment circuit provided in some embodiments of the present disclosure, the control circuit is configured to generate the voltage management signal and the selection signal according to a voltage identification table and current voltage information of the voltage regulation circuit.

Some embodiments of the present disclosure provide a dynamic voltage frequency adjustment method applied to a system-on-chip including a plurality of power domains, wherein the dynamic voltage frequency adjustment method includes: receiving the first clock signal through a frequency dividing circuit and outputting a plurality of second clock signals with a plurality of clock frequencies; receiving the plurality of second clock signals through a multiple-input multiple-output (MIMO) switch circuit, and outputting a plurality of third clock signals for the plurality of power domains, wherein the plurality of third clock signals correspond to the plurality of power domains one to one; when the system-on-chip performs voltage frequency adjustment operation, a control circuit outputs a voltage management signal to a voltage adjusting circuit and outputs a selection signal to the multiple-input multiple-output switch circuit, the voltage adjusting circuit adjusts the working voltage provided to the plurality of power domains according to the voltage management signal, and the multiple-input multiple-output switch circuit outputs the plurality of third clock signals to the plurality of power domains according to the selection signal.

For example, in a dynamic voltage frequency adjustment method provided in some embodiments of the present disclosure, in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment operation corresponding to at least one power domain of the plurality of power domains, the voltage management signal is first output to the voltage adjustment circuit by the control circuit, so that the voltage adjustment circuit adjusts the operating voltage of the at least one power domain according to the voltage management signal, and when the operating voltage of the at least one power domain is adjusted to be stable, the selection signal is output to the mimo switch circuit by the control circuit, so that the mimo switch circuit adjusts the clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal.

For example, in a dynamic voltage frequency adjustment method provided in some embodiments of the present disclosure, the causing the voltage regulation circuit to regulate the operating voltage of the at least one power domain according to the voltage management signal includes: enabling the voltage regulating circuit to slowly step up the working voltage of the at least one power domain; causing the mimo switching circuit to ramp up a clock frequency of at least one third clock signal output to the at least one power domain in accordance with the selection signal, comprising: and gradually increasing the clock frequency of the at least one third clock signal output to the at least one power domain by the MIMO switch circuit in a low-clock frequency to high-clock frequency and multi-stage switching manner.

For example, in a dynamic voltage frequency adjustment method provided by some embodiments of the present disclosure, in a case where the voltage frequency adjustment operation includes a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, the selection signal is output to the multiple-input multiple-output switch circuit through the control circuit, so that the mimo switching circuit down-regulates a clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal, when the clock frequency of the at least one third clock signal of the at least one power domain is scaled down to be stable, then the voltage management signal is output to the voltage regulating circuit through the control circuit, so that the voltage regulating circuit can regulate and reduce the working voltage of the at least one power domain according to the voltage management signal.

For example, in a dynamic voltage frequency adjustment method provided in some embodiments of the present disclosure, enabling the mimo switch circuit to down-regulate a clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal includes: gradually reducing the clock frequency of the at least one third clock signal output to the at least one power domain by the multiple-input multiple-output switch in a high-clock-frequency to low-clock-frequency and multi-stage switching manner; causing the voltage regulation circuit to regulate down the operating voltage of the at least one power domain in accordance with the voltage management signal, comprising: and enabling the voltage regulating circuit to slowly step down the working voltage of the at least one power domain.

For example, in a dynamic voltage frequency adjustment method provided in some embodiments of the present disclosure, the control circuit includes: the state machine circuit is coupled with the frequency division circuit and the MIMO switch circuit; and register circuitry coupled to the state machine circuitry; when the system-on-chip performs the voltage frequency adjustment operation, the control circuit outputs the voltage management signal to the voltage adjustment circuit and outputs the selection signal to the multiple-input multiple-output switch circuit, including: enabling the register circuit to output a control signal to the state machine circuit; and enabling the state machine circuit to output the voltage management signal to the voltage regulating circuit according to the control signal and output the selection signal to the multiple-input multiple-output switch circuit.

For example, in a dynamic voltage frequency adjustment method provided in some embodiments of the present disclosure, the voltage management signal includes a voltage regulation trigger signal and regulation target voltage information, and when the system-on-chip performs a voltage frequency regulation operation, the voltage regulation circuit regulates the operating voltages provided to the plurality of power domains according to the voltage management signal, including: causing the voltage regulation circuit to regulate an operating voltage of at least one of the plurality of power domains to a target voltage in accordance with the voltage regulation trigger signal regulation and the regulation target voltage information.

For example, some embodiments of the present disclosure provide a dynamic voltage frequency adjustment method further including: when the system-on-chip performs the voltage frequency adjustment operation, the state machine circuit is enabled to output a frequency division signal to the frequency division circuit according to the control signal, so that the frequency division circuit outputs the plurality of second clock signals according to the frequency division signal.

For example, in a dynamic voltage frequency adjustment method provided in some embodiments of the present disclosure, the method for adjusting a voltage of a power supply includes: receiving at least a portion of the plurality of second clock signals through each of the plurality of multiplexers, outputting a third clock signal for a power domain corresponding to the each multiplexer.

For example, some embodiments of the present disclosure provide a dynamic voltage frequency adjustment method further including: and receiving an interrupt signal output by the voltage regulating circuit through the control circuit, and determining whether to generate the voltage management signal and the selection signal according to the interrupt signal.

For example, in some embodiments of the present disclosure, a method for adjusting a dynamic voltage frequency by outputting the voltage management signal to the voltage regulating circuit and outputting the selection signal to the mimo switch circuit through the control circuit includes: and enabling the control circuit to generate the voltage management signal and the selection signal according to a voltage identification table and the current voltage information of the voltage regulating circuit.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic diagram of power regulation of a system-on-chip;

FIG. 2 is a schematic diagram of a dynamic voltage frequency adjustment circuit;

FIG. 3 is a schematic diagram of a system-on-chip provided by some embodiments of the present disclosure;

fig. 4 is a schematic diagram of a level shifting circuit provided by some embodiments of the present disclosure;

fig. 5 is a schematic diagram of a clamp level shifting circuit provided by some embodiments of the present disclosure;

FIG. 6 is a schematic diagram of a dynamic voltage frequency adjustment circuit provided by some embodiments of the present disclosure;

fig. 7 is a flow chart of a dynamic voltage frequency adjustment method provided by some embodiments of the present disclosure;

fig. 8A is a schematic diagram of a system-on-chip provided by some embodiments of the present disclosure;

FIG. 8B is a schematic diagram of another system-on-chip provided by some embodiments of the present disclosure;

FIG. 9 is a schematic diagram of a dynamic voltage frequency adjustment circuit provided by some embodiments of the present disclosure;

FIG. 10 is a schematic diagram of a shared dynamic voltage frequency adjustment circuit according to some embodiments of the present disclosure;

FIG. 11 is a schematic diagram of a dedicated dynamic voltage frequency adjustment circuit provided by some embodiments of the present disclosure;

fig. 12 is a schematic diagram of a level shifting circuit provided by some embodiments of the present disclosure;

fig. 13 is a schematic diagram of a level shifting circuit provided by some embodiments of the present disclosure;

FIG. 14 is a schematic diagram of the clock signal and the ramp up of the operating voltage for some embodiments of the present disclosure; and

fig. 15 is a schematic diagram of clock signals and regulation of operating voltage drops for some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated by the following specific examples. A detailed description of known functions and known parts (elements) may be omitted in order to keep the following description of the embodiments of the present disclosure clear and concise. When any element of an embodiment of the present disclosure appears in more than one drawing, that element is identified in each drawing by the same or similar reference numeral.

In System on a Chip (SoC) design, a balance control level of power and performance is an important index of the SoC, and power control of the SoC is an important work for research and design thereof. FIG. 1 is a schematic diagram of power regulation of a system-on-chip. As shown in fig. 1, when the system-on-chip is idle or lightly loaded, the system-on-chip needs lower power, and only needs to send an interrupt signal 20 to the on-chip detector of the voltage regulator, which sets the power supply of the system-on-chip to a lower voltage and frequency via the voltage frequency signal 10 to meet the lower performance/power level. In order for the soc to satisfy the Process, Voltage and Temperature (PVT) conditions of the task load in all cases, the Voltage and frequency of the soc must be set to satisfy the PVT conditions in the worst case. For example, requiring the system-on-chip to send an interrupt signal 20 to the on-chip detector of the voltage regulator, the voltage regulator fixedly sets the system-on-chip supply power to a higher voltage and frequency via the voltage frequency signal 10 to meet the higher performance/power level. Therefore, setting the power supply power of the system-on-chip to be fixed sometimes causes a performance loss and sometimes causes a power waste. Compared with the fast response requirement of a higher performance/power level, the fixed power control of the system-on-chip cannot respond in time, and the lower performance/power level and the higher performance/power level cannot be switched in time.

Dynamic voltage frequency regulation may be used to address the problem that a fixed setting of the power supply of the system-on-chip sometimes results in performance loss and sometimes in power waste. Dynamic Voltage Frequency Scaling (DVFS) may dynamically adjust Voltage and Frequency according to the computational requirements of the application program being run by the chip. For example, when high performance is not required, the voltage and frequency are reduced to reduce power consumption; when high performance is required, the voltage and the frequency are increased to improve the performance of the system-level chip, so that the aims of giving consideration to the performance and saving energy are fulfilled.

The strategy for supporting frequency modulation and voltage regulation by dynamic voltage and frequency regulation mainly comprises the following strategies:

an On demand (On demand) strategy, wherein when the load of the system level chip is small, the system level chip operates at low frequency and low voltage, and when the load of the system level chip is increased, the frequency and the voltage are increased according to the demand;

a conservative (conservative) strategy, similar to the on-demand strategy, except that the frequency and voltage are increased progressively as they are increased;

a high performance (performance) strategy, where the system-on-chip operates at the highest frequency and voltage supported;

a power save (power save) strategy, where the system-on-chip operates at the lowest supported frequency and voltage;

user space (user space) strategy, system-on-chip allows to operate at the frequency and voltage set by the user himself.

The dynamic voltage frequency adjustment circuit having the DVFS function described above can be implemented according to the DVFS principle described above. The dynamic voltage frequency adjusting circuit can be applied to the SoC shown in fig. 1, and cooperates with the system-on-chip power supply power adjusting system shown in fig. 1 to adjust the system-on-chip power supply power in a DVFS manner. Fig. 2 is a schematic diagram of a dynamic voltage frequency adjustment circuit. As shown in fig. 2, a Dynamic Voltage Frequency Scaling (DVFS) circuit 100 includes a controller 110, a Frequency divider (clock divider)120, and a multiplexer (multiplexer) 130. The controller 110 is coupled to the frequency divider 120 and the multiplexer 130. The frequency divider 120 is coupled to the multiplexer 130. The dynamic voltage frequency adjustment circuit 100 may be disposed in a System-on-a-chip (SoC, also referred to as "SoC") 201, and provides a clock signal to a processing core (core) of the SoC 201. The system-on-chip 201 may be a High Performance Computing (HPC) chip, an artificial intelligence accelerator (AI accelerator) chip, or the like, and the processing core may be a Microprocessor (MPU), which is not limited in the present disclosure. The controller 110 is further coupled to a Voltage Regulator (VR) 202, and the controller 110 can control the Voltage Regulator 202 to dynamically adjust the operating Voltage VDD. The voltage regulator 202 may be disposed inside or outside the system-on-a-chip 201, and the disclosure is not limited thereto. The system-on-chip 201 can receive the operating voltage VDD provided by the voltage regulator 202. The multiplexer 130 may be a glitch-free clock multiplexer (glitch-free multiplexer).

The frequency divider 120 may receive a clock signal output by a Phase-Locked loop (PLL) circuit or a first clock signal CK1 provided by a Voltage-Controlled Oscillator (VCO) within the PLL circuit, and generate a plurality of second clock signals CK2_1 to CK2_ N having different clock frequencies according to the first clock signal CK1, where N is a positive integer. The frequency divider 120 can provide the second clock signals CK2_1 CK2_ N to the multiplexer 130, and the controller 110 can select one of the second clock signals CK2_1 CK2_ N as the core clock signal CK3 by controlling the multiplexer 130 and output the selected one to the processing core of the system-on-a-chip 201. Therefore, the dynamic voltage frequency adjustment circuit 100 can dynamically adjust the operating voltage provided to the soc 201 and dynamically adjust the clock frequency of the core clock signal CK3 provided to the soc 201.

A system-on-chip typically contains multiple processing cores, each for implementing a different processing function. For example, a system-on-chip may include a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), a baseband processor (Modem), a Random Access Memory (RAM), a digital-to-analog/analog-to-digital converter (DAC/ADC), and so on. When the voltage and frequency of the system-on-chip with the DVFS function are adjusted, the adjustment can be performed only on the whole system-on-chip, and cannot be performed individually on each processing core inside the system-on-chip.

At least some embodiments of the present disclosure provide a system-on-chip, comprising: at least one dynamic voltage frequency adjustment circuit, wherein the system-on-chip includes at least two Power domains (Power domains), the at least one dynamic voltage frequency adjustment circuit configured to dynamically adjust an operating voltage and a clock frequency of each of the at least two Power domains.

The system-level chip is divided into a plurality of mutually independent power domains, and the system-level chip can respectively carry out dynamic voltage frequency adjustment according to requirements aiming at different power domains, so that the power requirements of different power domains can be timely met when the system-level chip operates, and the energy consumption of the system-level chip is reduced on the premise of meeting the performance of the system-level chip.

Fig. 3 is a schematic diagram of a system-on-chip according to some embodiments of the present disclosure. As shown in fig. 3, the system-on-chip 300 includes: at least two power domains 310 and at least one dynamic voltage frequency adjustment circuit 320.

For example, the at least one dynamic voltage frequency adjustment circuit may include at least one of a shared dynamic voltage frequency adjustment circuit and/or a dedicated dynamic voltage frequency adjustment circuit, wherein the shared dynamic voltage frequency adjustment circuit corresponds to the first dynamic voltage frequency adjustment circuit of the present disclosure; the dedicated type dynamic voltage frequency adjustment circuit corresponds to the second dynamic voltage frequency adjustment circuit of the present disclosure. The shared dynamic voltage frequency adjustment circuit is configured to be capable of dynamically adjusting an operating voltage and a clock frequency of a plurality of the at least two power domains. For example, the shared dynamic voltage frequency adjustment circuit may dynamically adjust the operating voltages and operating clock frequencies of the plurality of power domains 310, i.e., the plurality of power domains 310 share one dynamic voltage frequency adjustment circuit 320. Each of the plurality of power domains 310 is isolated from another power domain 310, and each of the power domains 310 may have different operating voltages and operating frequencies, and of course, some or all of the power domains 310 may have the same operating voltage and/or operating frequency.

For example, the dedicated type dynamic voltage frequency adjustment circuit is configured to be able to dynamically adjust the operating voltage and clock frequency of one power domain. For example, a dedicated dynamic voltage frequency adjustment circuit 320 is used to adjust the operating voltage and operating clock frequency of only one power domain corresponding thereto. For example, the dedicated type dynamic voltage frequency adjustment circuit may be implemented as the dynamic voltage frequency adjustment circuit shown in fig. 2.

For example, the at least one dynamic voltage frequency adjustment circuit is configured to transmit a signal to each of the at least two power domains through a level shifting circuit, each of the at least two power domains configured to output a signal through a level shifting circuit having a clamping function.

Fig. 4 is a schematic diagram of a level shift circuit provided by some embodiments of the present disclosure. The level shift circuit shown in fig. 4 can be used for the system-on-chip shown in fig. 3. As shown in fig. 4, since the operating voltage of the power domain 410 dynamically changes according to the adjustment of the dynamic voltage and frequency adjusting circuit, and the dynamic voltage and frequency adjusting circuit 420 is in a relatively stable operating voltage environment (e.g., a power normally-on domain), a voltage difference exists between the dynamic voltage and frequency adjusting circuit 420 and the power domain 410, in order to match the voltage difference during signal transmission between the power domain 410 and the dynamic voltage and frequency adjusting circuit 420, the level shifter circuit 430 may be used to match the voltage difference, so as to reduce the influence of the voltage difference on the signal transmitted between the power domain 410 and the dynamic voltage and frequency adjusting circuit 420.

Fig. 5 is a schematic diagram of a clamp level shifting circuit provided by some embodiments of the present disclosure. The level shifting circuit shown in fig. 5 may be used in the system-on-chip shown in fig. 3. As shown in fig. 5, the power domain 510 may be in a power-off state (e.g., a power-down state) in some cases, but the signal directly output from the power domain in the power-off state may affect the external operating voltage, so when the power domain 510 outputs the signal externally, the output signal of the power domain 510 may be level-converted and clamped by the clamping level conversion circuit 520. The clamp level conversion circuit can support the power domain to ensure that a signal is always at a high potential in an operating voltage off state (such as a power-down state) so as to ensure the validity of a signal value and the operation related to the signal.

At least some embodiments of the present disclosure also provide a dynamic voltage frequency adjustment circuit, including: a frequency dividing circuit configured to receive a first clock signal and output a plurality of second clock signals having a plurality of clock frequencies; a multiple-input multiple-output switch circuit configured to receive a plurality of second clock signals and output a plurality of third clock signals for a plurality of power domains, wherein the plurality of third clock signals are in one-to-one correspondence with the plurality of power domains; the control circuit is coupled with the frequency dividing circuit, the multi-input multi-output switch circuit and the voltage regulating circuit; the control circuit is configured to output a voltage management signal to the voltage regulation circuit and output a selection signal to the multiple-input multiple-output switch circuit when the system-on-chip performs a voltage frequency regulation operation, the voltage regulation circuit is configured to regulate an operating voltage provided to the multiple power domains according to the voltage management signal when the system-on-chip performs the voltage frequency regulation operation, and the multiple-input multiple-output switch circuit is configured to output a plurality of third clock signals to the multiple power domains according to the selection signal.

Fig. 6 is a schematic diagram of a dynamic voltage frequency adjustment circuit according to some embodiments of the present disclosure. The dynamic voltage frequency adjustment circuit can be used as a shared dynamic voltage frequency adjustment circuit and used in a system-on-chip as shown in fig. 3. As shown in fig. 6, the dynamic voltage frequency adjustment circuit includes: a frequency dividing circuit 620, a multiple-input multiple-output switch circuit 630 and a control circuit 610.

As shown in fig. 6, the control circuit 610 is coupled to the frequency divider circuit 620 and the mimo switch circuit 630. The frequency divider 620 is coupled to the mimo switch 630. The dynamic voltage frequency adjustment circuit 600 may be disposed in the system-on-chip 701 and provide a clock signal to one or more power domains of the system-on-chip 701. The control circuit 610 is further coupled to one or more voltage regulating circuits, and the control circuit 610 may control the voltage regulating circuits to dynamically adjust the operating voltage VDD of the power domain corresponding to the one or more voltage regulating circuits, for example, the one or more voltage regulating circuits may include the voltage regulating circuit 702_1 to the voltage regulating circuit 702_ M, which is not limited by the disclosure. One or more voltage regulation circuits may be disposed inside or outside of system-on-chip 701, and the disclosure is not limited thereto. One or more power domains of system-on-chip 701 may receive an operating voltage VDD provided by one or more voltage regulating circuits corresponding thereto. The mimo switch circuit 630 may be implemented as a plurality of glitchless clock multiplexers, and the disclosure is not limited thereto.

The frequency divider circuit 620 may receive a clock signal output by a Phase-Locked loop (PLL) circuit or a first clock signal CK1 provided by a Voltage-Controlled Oscillator (VCO) within the PLL circuit, and generate a plurality of second clock signals CK2_1 to CK2_ N having different clock frequencies according to the first clock signal CK1, where N is a positive integer. The frequency divider circuit 620 can provide the second clock signals CK2_1 CK2_ N to the multi-input multi-output switch circuit 630, and the multi-input multi-output switch circuit 630 selects and outputs at least a portion of the plurality of frequency divider circuit output clock signals CK2_1 CK2_ N according to the selection signal 603, so as to obtain the clock signals CK3_1 CK3_ M corresponding to the plurality of power domains. The control circuit 610 outputs a plurality of voltage management signals to a plurality of voltage regulation circuits (e.g., the voltage regulation circuit 702_1 to the voltage regulation circuit 702_ M) when the system-on-chip performs the voltage frequency regulation operation, wherein the plurality of voltage management signals may include the voltage management signals 602_1 to 602_ M corresponding to the voltage regulation circuits 702_1 to 702_ M in a one-to-one correspondence, so that the plurality of voltage regulation circuits regulate the operating voltage (e.g., VDD) of the corresponding power domain. The frequency-dividing circuit input clock signal corresponds to a first clock signal in the present disclosure, the plurality of frequency-dividing circuits output clock signals corresponds to a plurality of second clock signals in the present disclosure, and the plurality of power domain clock signals corresponds to a plurality of third clock signals in the present disclosure.

For example, each of the plurality of power domain clock signals CK3_ 1-CK 3_ M may be used to provide a clock frequency of a corresponding power domain, wherein the clock signals are independent of each other, and the frequencies may be the same or different. For example, the multiple-input multiple-output switch circuit 630 may include a plurality of multiplexers, each having a plurality of inputs for receiving at least some of the frequency-divided circuit output clock signals CK2_ 1-CK 2_ N and an output, the output of each multiplexer corresponding to one of the plurality of power domains and for outputting one of the plurality of power domain clock signals CK3_ 1-CK 3_ M to one of the plurality of power domains.

For example, the voltage frequency adjustment operation may include: in the case of a voltage frequency up-scaling operation for at least one of the power domains, the control circuit 610 outputs a voltage management signal to a voltage regulating circuit (e.g., a plurality of voltage regulating circuits corresponding to the power domains) to enable the voltage regulating circuit to up-scale the operating voltage of the at least one power domain according to the voltage management signal, e.g., to enable one of the voltage regulating circuits to up-scale the operating voltage of the corresponding power domain. When the operating voltage of at least one power domain is adjusted to be stable, the control circuit 610 then outputs the selection signal 603 to the mimo switch circuit 630, so that the mimo switch circuit adjusts the clock frequency of at least one power domain clock signal output to the at least one power domain according to the selection signal 603.

For example, the voltage frequency adjustment operation may include: under the condition of the voltage frequency adjustment operation of at least one of the power domains, when the voltage adjustment circuit first slowly and synchronously adjusts and increases the working voltage of at least one power domain to be stable, the mimo switch circuit 630 gradually adjusts and increases the clock frequency of at least one power domain clock signal output to at least one power domain in a low-clock-frequency to high-clock-frequency and multi-stage switching manner.

For example, the voltage frequency adjustment operation may include: under the condition of the voltage frequency adjustment and reduction operation of at least one power domain of the plurality of power domains, the control circuit 610 firstly outputs the selection signal 603 to the multiple-input multiple-output switch circuit 630, so that the multiple-input multiple-output switch circuit 630 adjusts and reduces the clock frequency of at least one power domain clock signal output to the at least one power domain according to the selection signal 603, and when the clock frequency of at least one power domain clock signal of the at least one power domain is adjusted and reduced to be stable, the control circuit 610 further outputs a voltage management signal to the voltage regulation circuit, so that the voltage regulation circuit adjusts and reduces the working voltage of the at least one power domain according to the voltage management signal.

For example, the voltage frequency adjustment operation may include: in the case of a voltage frequency down-regulation operation of at least one of the power domains, the mimo switch circuit 630 gradually reduces the clock frequency of at least one power domain clock signal output to the at least one power domain in a multi-stage switching manner from a high clock frequency to a low clock frequency, and when the clock frequency of the at least one power domain clock signal of the at least one power domain is reduced to be stable, the voltage regulation circuit then gradually reduces the operating voltage of the at least one power domain, for example, gradually reduces the operating voltage of the power domain corresponding to the voltage regulation circuit.

For example, as shown in fig. 6, the control circuit may include: state machine circuitry 611, and register circuitry 612. The state machine circuit 611 is coupled to the frequency divider circuit 620 and the mimo switch circuit 630; the register circuit 612 is coupled to the state machine circuit 611; the register circuit 612 is configured to output the control signal 605 to the state machine circuit 611 to control the state machine circuit 611 to perform a voltage frequency adjustment operation on at least one of the plurality of power domains when the system-on-chip 701 performs the voltage frequency adjustment operation, and the state machine circuit 611 is configured to output a voltage management signal to the voltage adjustment circuit according to the control signal when the system-on-chip performs the voltage frequency adjustment operation, for example, to cause the voltage adjustment circuit to adjust an operating voltage of a power domain corresponding thereto to a target voltage (e.g., a lower idle energy saving voltage or a full-load performance voltage), and to output the selection signal 603 to the multi-in and multi-out switch circuit 630, for example, to cause the multi-in and multi-out switch circuit 630 to gradually change a clock signal output to at least one power domain to adjust an operating clock frequency of the power domain. Wherein the voltage regulation circuit may include a plurality of voltage regulation circuits corresponding to the plurality of power domains.

For example, the voltage management signal includes a voltage adjustment trigger signal and adjustment target voltage information, and the voltage adjustment circuit is configured to adjust the operating voltage of at least one of the plurality of power domains to a target voltage according to the voltage adjustment trigger signal and the adjustment target voltage information when the system-on-chip performs the voltage frequency adjustment operation.

For example, the state machine circuit 611 can also be used to output the frequency-divided signal 604 to the frequency-dividing circuit 620 according to the control signal 605 when the system-on-chip performs the voltage frequency adjustment operation, so that the frequency-dividing circuit 620 outputs a plurality of frequency-divided circuit output clock signals, e.g., CK2_1 to CK2_ N, according to the frequency-divided signal 604.

For example, the control circuit 610 may be configured to receive an interrupt signal output by the voltage regulating circuit and determine whether to generate the voltage management signal and the selection signal according to the interrupt signal, so as to perform the voltage frequency regulating operation.

For example, the control circuit 610 may be configured to generate the voltage management signal and the selection signal according to the voltage identification table and the current voltage information of the voltage adjusting circuit, for example, the voltage identification table may store in advance the value of the voltage to which each power domain needs to be adjusted when performing voltage frequency adjustment and the value of the voltage to which the power domain needs to be adjusted.

The dynamic voltage frequency adjusting circuit can respectively adjust the dynamic voltage frequency according to the requirements aiming at different power domains, thereby timely meeting the power requirements of different power domains when a system-on-chip operates and improving the power efficiency of the system-on-chip.

At least some embodiments of the present disclosure also provide a dynamic voltage frequency adjustment method, including: receiving, by a frequency dividing circuit, a frequency dividing circuit input clock signal, and outputting a plurality of frequency dividing circuit output clock signals having a plurality of clock frequencies; receiving a plurality of frequency division circuit output clock signals through a multi-input multi-output switch circuit, and outputting a plurality of power domain clock signals for a plurality of power domains, wherein the plurality of power domain clock signals correspond to the plurality of power domains one to one; when the system-level chip carries out voltage frequency regulation operation, the control circuit outputs a voltage management signal to the voltage regulation circuit and outputs a selection signal to the multi-input multi-output switch circuit; adjusting, by a voltage adjustment circuit, an operating voltage provided to a plurality of power domains in accordance with a voltage management signal; and outputting a plurality of power domain clock signals to a plurality of power domains according to the selection signal through the MIMO switch circuit.

Fig. 7 is a flow chart of a dynamic voltage frequency adjustment method provided by at least some embodiments of the present disclosure. The dynamic voltage frequency adjustment method shown in fig. 7 may be used in the dynamic voltage frequency adjustment circuit shown in fig. 6. As shown in fig. 7, the dynamic voltage adjustment method may include the following five steps S101 to S105:

step S101, receiving a frequency division circuit input clock signal through a frequency division circuit, and outputting a plurality of frequency division circuit output clock signals with a plurality of clock frequencies;

step S102, receiving a plurality of frequency division circuit output clock signals through a multi-input multi-output switch circuit, and outputting a plurality of power domain clock signals for a plurality of power domains;

step S103, outputting a voltage management signal to the voltage regulating circuit through the control circuit, and outputting a selection signal to the multi-input multi-output switch circuit;

step S104, adjusting the working voltage provided to a plurality of power domains by the voltage adjusting circuit according to the voltage management signal;

step S105, a plurality of power domain clock signals are output to a plurality of power domains according to the selection signal through the mimo switch circuit.

In addition to the above five steps S101 to S105, in some embodiments, the dynamic voltage adjustment method may further include at least one of the following steps S106 and S107:

step S106, receiving the interrupt signal output by the voltage regulating circuit through the control circuit, and determining whether to generate a voltage management signal and a selection signal according to the interrupt signal;

step S107, when the system-on-chip performs the voltage frequency adjustment operation, causes the state machine circuit to further output the frequency division signal to the frequency division circuit according to the control signal, so that the frequency division circuit outputs the plurality of frequency division circuit output clock signals according to the frequency division signal.

The following describes steps S101 to S107 in detail with reference to fig. 6 and 7.

For example, the divider circuit input clock signal CK1 in step S101 may be a clock signal output by a phase-locked loop circuit or a clock signal provided by a voltage-controlled oscillator within the phase-locked loop circuit. The plurality of frequency-divided circuit output clock signals CK2_ 1-CK 2_ N may include a plurality of different clock frequencies for each of a plurality of power domains, where the plurality of different clock frequencies for each power domain may be a plurality of different clock frequencies required in a clock frequency adjustment process.

For example, the plurality of power domain clock signals CK3_1 to CK3_ M in step S102 correspond to each of the plurality of power domains in a one-to-one manner, wherein the power domain clock signals CK3_1 to CK3_ M may be the same (partially or completely the same) or different, and the plurality of power domain clock signals CK3_1 to CK3_ M are selected from the plurality of frequency division circuit output clock signals CK2_1 to CK2_ N by the multi-input multi-output switch circuit.

For example, in step S103, when the voltage frequency adjustment operation is performed on one or more power domains of the system-on-chip, the up-regulation operation of the operating voltage and the up-regulation operation of the operating clock frequency may be performed on the one or more power domains of the system-on-chip. For example, in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment operation corresponding to at least one of the plurality of power domains, the control circuit outputs a voltage management signal to the voltage adjustment circuit to enable the voltage adjustment circuit to adjust the operating voltage of the at least one power domain according to the voltage management signal, and when the operating voltage of the at least one power domain is adjusted to be stable, the control circuit outputs a selection signal to the multi-input and multi-output switch circuit to enable the multi-input and multi-output switch circuit to adjust the clock frequency of at least one power domain clock signal output to the at least one power domain according to the selection signal.

For example, in step S104, each power domain may support a higher operating clock frequency at a higher operating voltage, and in order to be able to increase the operating clock frequency of one or more power domains, it is necessary to make the voltage regulating circuit first step up the operating voltage of the one or more power domains to a higher voltage value (e.g., 5V).

For example, in step S105, the mimo switch may gradually increase the clock frequency of the one or more power domain clock signals corresponding to the one or more power domains by switching from a high clock frequency to a low clock frequency in multiple stages, where the gradually increasing of the clock frequency by switching from the low clock frequency to the high clock frequency in multiple stages may be performed by setting a plurality of clock frequencies with increasing equal gradient between the low clock frequency and the high clock frequency, and sequentially outputting the plurality of clock frequencies with increasing equal gradient in order from low to high for gradually increasing.

For example, in step S103, when the one or more power domains of the system-on-chip perform the voltage frequency adjustment operation, the operating voltage and the operating clock frequency of the one or more power domains of the system-on-chip may be reduced. For example, in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, that is, when the operating voltage and the operating frequency of the power domain are decreased, the control circuit may first output a selection signal to the multiple-input multiple-output switch circuit, so that the multiple-input multiple-output switch circuit adjusts down the clock frequency of the one or more power domain clock signals to the one or more power domains according to the selection signal, and when the clock frequency of the one or more power domain clock signals corresponding to the one or more power domains is adjusted to be stable, the control circuit may then output a voltage management signal to the plurality of voltage adjustment circuits, so that the voltage adjustment circuits adjust down the operating voltage of the one or more power domains according to the voltage management signal.

For example, in step S105, each power domain may support a higher operating clock frequency at a higher operating voltage, and may support a larger operating clock frequency adjustment range, so that the mimo switch may gradually decrease the clock frequency of the one or more power domain clock signals output to the one or more power domains in a manner of switching from a high clock frequency to a low clock frequency in multiple stages on the premise of maintaining the operating voltage of the one or more power domains, where the gradually decreasing in the manner of switching from the high clock frequency to the low clock frequency in multiple stages may be to set a plurality of clock frequencies decreasing in equal gradient between the high clock frequency and the low clock frequency, and sequentially output the plurality of clock frequencies decreasing in equal gradient in order from high to low to perform the gradual decrease.

For example, in step S104, the voltage regulating circuit is made to gradually step down the operating voltage of the one or more power domains, for example, the operating voltage of the one or more power domains may be gradually stepped down from 5V higher to 4V by the voltage regulating circuit.

For example, the control circuit may include a state machine circuit and a register circuit, and the control circuit may be the same as the control circuit 110 shown in fig. 6, and is not described herein again.

For example, step S103 may include causing the register circuit in the control circuit to output a control signal to the state machine circuit in the control circuit, and causing the state machine circuit to output a voltage management signal to the plurality of voltage regulating circuits according to the control signal, so that the plurality of voltage regulating circuits can regulate the operating voltages of the plurality of power domains corresponding thereto, and output a selection signal to the multiple-input multiple-output switch circuit, so that the multiple-input multiple-output switch circuit can select a part of the clock signals from the plurality of frequency division circuit output clock signals CK2_1 to CK2_ N as the plurality of power domain clock signals CK3_1 to CK3_ M, and output the plurality of power domain clock signals CK3_1 to CK3_ M to the corresponding plurality of power domains to provide the operating clock frequency of each of the plurality of power domains.

For example, in step S104, the voltage management signal may include a voltage regulation trigger signal and regulation target voltage information, for example, the voltage regulation trigger signal is used to inform the voltage regulation circuit whether to regulate the operating voltage of the power domain corresponding thereto; the adjustment target voltage information is used to inform the voltage adjustment circuit of a specific voltage value (e.g., a target voltage value) to adjust to, so that the voltage adjustment circuit can adjust and adjust the operating voltage of the power domain corresponding thereto to the target voltage according to the voltage adjustment trigger signal.

For example, in step S105, the mimo switch may include a plurality of multiplexers, each multiplexer having a plurality of inputs and an output, the plurality of inputs of each multiplexer being configured to receive at least a portion of the plurality of divider circuit output clock signals, the output of each multiplexer corresponding to one of the plurality of power domains and being configured to output the one of the plurality of power domain clock signals to the one of the plurality of power domains.

For example, in step S106, the interrupt signal may be a feedback signal of the voltage regulating circuit to the control circuit, and the feedback signal may inform the control circuit to stop sending the voltage management signal and the selection signal when the operating voltage of the corresponding power domain has been regulated to the target voltage; or when the working voltage of the corresponding power domain needs to be adjusted, the control circuit is informed to start sending the voltage management signal and the selection signal.

For example, in step S107, when the system-on-chip performs the voltage frequency adjustment operation, the state machine circuit is further caused to output the frequency-divided signal to the frequency dividing circuit according to the control signal, so that the frequency dividing circuit outputs a plurality of frequency-divided circuit output clock signals according to the frequency-divided signal, wherein a part of the plurality of frequency-divided circuit output clock signals can provide the clock frequency to one or more power domains.

For example, the above steps may cause the control circuit to generate the voltage management signal and the selection signal according to a voltage identification table and current voltage information of the voltage regulating circuit when adjusting the operating voltage and the operating clock frequency of one or more power domains, wherein the voltage identification table contains a low target voltage value to be adjusted and a high target voltage value to be adjusted, and a clock frequency sequence corresponding to a voltage range from the low target voltage value to the high target voltage value.

The technical effect of the dynamic voltage frequency adjustment method is the same as that of the dynamic voltage frequency adjustment circuit, and is not described herein again.

A system-on-chip, a dynamic voltage and frequency adjustment circuit for the system-on-chip, and a dynamic voltage and frequency adjustment method for the dynamic voltage and frequency adjustment circuit provided by at least some embodiments of the present disclosure will be described below with reference to a specific but non-limiting example.

Fig. 8A is a schematic diagram of a system-on-chip provided by some embodiments of the present disclosure. As shown in fig. 8A, the system-On-Chip 800A includes a plurality of power domains 810, a plurality of dynamic voltage and frequency adjusting Circuits 820A, a Network On Chip (NOC) 830, a Central Routing Control Unit (CRCU) 840, a Peripheral circuit (Peripheral Circuits)850, a plurality of voltage adjusting Circuits 860, and a normally-On power domain (Always On power domain) 870.

For example, system-on-chip 800A may be divided into multiple power domains. For example, the power domains 810 can be divided into four independent power domains, and the number of the divided power domains is not limited by the present disclosure.

For example, the number of voltage regulating circuits 860 may correspond to the number of power domains 810, and each voltage regulating circuit 860 may correspond one-to-one to each power domain 810. The voltage adjusting circuit 860 is connected to the peripheral circuit 850 to receive control information from the dynamic voltage frequency adjusting circuit 820A; the voltage regulation circuit 860 is also coupled to the corresponding power domain 810 to provide power to the corresponding power domain 810 and regulate the operating voltage of the corresponding power domain 810.

For example, the network-on-chip 830 is connected to the power domain 810, the network-on-chip 830 is connected to the peripheral circuits 850, and the network-on-chip 830 is further connected to the central routing control unit 840. The network on chip 830 is used for data transmission on the system-on-chip (e.g., data transmission between different power domains) and data transmission between the system-on-chip and the outside.

For example, the central routing control unit 840 is connected to the network-on-chip 830. Data in the network-on-chip 830 may be transmitted to the central routing control unit 840, and the central routing control unit 840 may schedule the data in the network-on-chip 830 to a corresponding destination.

For example, the peripheral circuit 850 may be connected to the dynamic voltage frequency adjustment circuit 820A, the on-chip network 830 and the voltage regulation circuit 860 for implementing system-on-chip and external input and output. The peripheral circuit 860 may be an input/output circuit (I/O circuit), among others.

For example, the power normally-on domain 870 includes the on-chip network 830, the plurality of dynamic voltage and frequency adjustment circuits 820A, the central routing control unit 840, and the peripheral circuit 850, so as to ensure the stability of the power supply of the on-chip network 830, the dynamic voltage and frequency adjustment circuits 820A, the central routing control unit 840, and the peripheral circuit 850, and to implement the power supply isolation from the plurality of power domains 810, so as to be not affected by the variation of the operating power of the plurality of power domains 810.

For example, each dynamic voltage frequency adjustment circuit 820A may correspond one-to-one with each power domain 810, such that the number of power domains and dynamic voltage adjustment circuits on a system-on-chip is the same. The dynamic voltage frequency adjustment circuit 820A is used to dynamically adjust the operating voltage and the operating frequency of the power domain 810 corresponding to the dynamic voltage frequency adjustment circuit 820A. Dynamic voltage frequency adjustment circuit 820A is coupled to power domain 810, and dynamic voltage frequency adjustment circuit 820A is further coupled to peripheral circuits 850. The dynamic voltage frequency adjustment circuit 820A dynamically adjusts the operating frequency of the power domain 810 in a step-by-step manner according to the power requirement of the power domain 810; meanwhile, the dynamic voltage frequency adjustment circuit 820A sends a voltage management signal to the voltage regulation circuit 860 corresponding to the power domain 810 through the peripheral circuit 850, so that the voltage regulation circuit 860 regulates the voltage of the power domain 810 according to the voltage management signal.

Fig. 8B is a schematic diagram of another system-on-chip provided by some embodiments of the present disclosure. The difference between the system-on-chip 800B shown in FIG. 8B and the system-on-chip 800A shown in FIG. 8A is that a plurality of power domains share one dynamic voltage-to-frequency adjustment circuit 820B. The dynamic voltage frequency adjustment circuit 820B is used to dynamically adjust the operating voltage and operating frequency of a plurality of power domains corresponding to the dynamic voltage frequency adjustment circuit 820B. The dynamic voltage frequency adjustment circuit 820B is connected to a plurality of power domains, respectively, and the dynamic voltage frequency adjustment circuit 820B is further connected to the peripheral circuit 850. The dynamic voltage frequency adjustment circuit 820B dynamically adjusts the operating frequency of each power domain 810 in the plurality of power domains in a step-by-step manner according to the power requirement of each power domain 810 in the plurality of power domains; meanwhile, the dynamic voltage frequency adjustment circuit 820B sends a voltage management signal to the voltage regulation circuit 860 corresponding to each power domain 810 through the peripheral circuit 850, so that the voltage regulation circuit 860 regulates the voltage of each power domain 810 according to the voltage management signal. For example, the dynamic voltage frequency adjustment circuit 820B in fig. 8B may be embodied as a dynamic voltage frequency adjustment circuit as shown in fig. 9 below, but is not limited thereto. For example, the remaining components in the system-on-chip 800B shown in fig. 8B can refer to the corresponding descriptions of the same components in the system-on-chip 800A shown in fig. 8A, and are not repeated herein.

Fig. 9 is a schematic diagram of a dynamic voltage frequency adjustment circuit according to some embodiments of the disclosure. As shown in fig. 9, the dynamic voltage frequency adjustment circuit 900 includes a control circuit 910, a frequency divider circuit 920, and a multiple-input multiple-output switch circuit 930. The control circuit 910 includes a Register (Register) circuit 911 and a State Machine (SM) circuit 912. The dynamic voltage frequency adjustment circuit 900 may be a common type dynamic voltage frequency adjustment circuit, and the register circuit 911 is coupled to the state machine circuit 912 and the plurality of voltage adjustment circuits, for example, the plurality of voltage adjustment circuits may include the voltage adjustment circuits 1002_1 to 1002_ M. The state machine circuit 912 is coupled to the frequency divider 920, the mimo switch 930, and the plurality of voltage regulators. In this embodiment, the dynamic voltage frequency adjustment circuit 900 may be disposed in the system-on-chip 1001 and provide the plurality of power domain clock signals CK3_ 1-CK 3_ M to a plurality of power domains, such as M power domains, of the system-on-chip 1001. The multiple power domains of the system-on-chip 1001 may receive the operating voltage VDD provided by the multiple voltage regulating circuits.

In this embodiment, the register circuit 911 may obtain the Voltage identification table (VID table) data 905 of the soc 1001 through the bus (bus) to store the Voltage identification table in advance. Thus, for example, when Firmware (Firmware) of the system-on-chip 1001 requires voltage frequency adjustment, or one or more of the plurality of voltage regulating circuits (e.g., one or more of the voltage regulating circuits 1002_1 to 1002_ M) require an overcurrent protection operation due to, for example, an overcurrent event, the register circuit 911 of the control circuit 910 may receive the interrupt signals (e.g., the interrupt signal 901_1 to the interrupt signal 901_ M) output by one or more of the plurality of voltage regulating circuits. In this regard, an over-Current event may be a condition where a Current output by one or more of the plurality of voltage regulating circuits to one or more power domains of the system-on-chip 1001 is in a surge Current (Inrush Current) or has an average Current value that is too high.

In this embodiment, the register circuit 911 may determine to generate and output the control signal 906 to the state machine circuit 912 according to the interrupt signal. In this embodiment, the state machine circuit 912 can also receive the reference clock signal CKR and the power information 909. The state machine circuit 912 may generate and output a voltage management signal to the plurality of voltage regulation circuits, a frequency division signal 904 to the frequency division circuit 920, and a selection signal 903 to the multiple-input multiple-output switch circuit 930 according to the control signal 906 and the power information 909. The state machine circuit 912 can effectively control the frequency divider circuit 920 and the mimo switch circuit 930 synchronously based on the reference clock signal CKR. In this embodiment, the voltage management signal includes a voltage regulation trigger signal and regulation target voltage information, for example, the voltage management signal output to the voltage regulation circuit 1002_1 includes a voltage regulation trigger signal 9021_1 and regulation target voltage information 9022_ 1; the voltage management signal output to the voltage adjustment circuit 1002_ M includes a voltage adjustment trigger signal 9021_ M and adjustment target voltage information 9022_ M.

In this embodiment, the register circuit 911 may determine the voltage adjustment information and the clock frequency adjustment information corresponding to each voltage adjustment circuit according to the voltage identification table and the current voltage information of the plurality of voltage adjustment circuits. The register circuit 911 may output a corresponding control signal 906 to the state machine circuit 912 according to the voltage adjustment information and the clock frequency adjustment information, so that the state machine circuit 912 may adjust the trigger signal and the adjustment target voltage information to each voltage adjustment circuit according to the corresponding voltage. Each voltage regulating circuit may dynamically adjust the operating voltage VDD of the power domain corresponding to the voltage regulating circuit according to the voltage regulation trigger signal it receives and the adjustment target voltage information. The state machine circuit 912 can also output the corresponding selection signal 903 and the frequency-divided signal 904 to the frequency-dividing circuit 920 and the mimo switch circuit 930 in a matching manner to adjust the clock frequencies of the clock signals CK3_1 to CK3_ M of the power domains. The voltage frequency adjustment operation performed by each power domain of the system-on-chip 1001 may be a voltage frequency up-scaling operation or a voltage frequency down-scaling operation. In other words, the dynamic voltage and frequency adjustment circuit 900 of the embodiment can dynamically adjust the operating voltage VDD of each power domain of the system-on-chip 1001, and dynamically adjust the clock frequencies of the clock signals of the power domains in cooperation, so as to flexibly adjust the performance of the system-on-chip 1001.

In the present embodiment, the state machine circuit 912 of the control circuit 910 may output the frequency-divided signal 904 to the frequency-dividing circuit 920 such that the frequency-dividing circuit 920 outputs a plurality of frequency-divided circuit output clock signals CK2_1 to CK2_ N in accordance with the frequency-divided signal 904 and the frequency-divided circuit input clock signal CK 1. The state machine circuit 912 of the control circuit 910 may control the mimo switch circuit 930 to output partial clock signals of the plurality of frequency-divided circuit output clock signals as the clock signals CK3_1 to CK3_ M of the plurality of power domains in advance.

In this embodiment, when the power domains of the system-on-chip 1001 perform the voltage frequency up-conversion operation, the state machine circuit 912 of the control circuit 910 may first output the voltage regulation trigger signal and the adjustment target voltage information to the voltage regulation circuits, so that the voltage regulation circuits can up-convert the operating voltages VDD supplied to the power domains of the system-on-chip 1001 according to the voltage regulation trigger signal and the adjustment target voltage information. Moreover, when the operating voltage VDD is increased to be stable, the state machine circuit 912 of the control circuit 910 may then output the selection signal 903 to the mimo switch circuit 930, so that the mimo switch circuit 930 may output some of the divided-circuit output clock signals with higher clock frequencies according to the selection signal 903 as the clock signals CK3_ 1-CK 3_ M of the power domains. In other words, in the present embodiment, each of the plurality of voltage regulating circuits may first ramp up the operating voltage VDD of the corresponding power domain to be stable during the voltage ramp-up period, so as to effectively suppress or reduce the generation of power noise (power noise). The mimo switch circuit 930 may then sequentially output at least a portion of the plurality of divided-circuit output clock signals CK2_ 1-CK 2_ N in a multi-stage switching manner from a low clock frequency to a high clock frequency during the first response period to appropriately boost the power of each of the plurality of power domains. In the present embodiment, the voltage ramp-up period and the first response period do not overlap.

In this embodiment, when the power domains of the soc 1001 perform the voltage frequency down-scaling operation, the state machine circuit 912 of the control circuit 910 may first output the selection signal 903 to the mimo switch circuit 930, so that the mimo switch circuit 930 may output some of the clock signals output by the frequency-dividing circuits with lower clock frequencies according to the selection signal 903 as the clock signals CK3_ 1-CK 3_ M of the power domains. When the adjustment of the clock signals CK3_ 1-CK 3_ M of the power domains is completed, the state machine circuit 912 of the control circuit 910 may then output a plurality of sets of voltage adjustment trigger signals and adjustment target voltage information to the plurality of voltage adjustment circuits, so that each of the plurality of voltage adjustment circuits may adjust the operating voltage VDD of a corresponding power domain of the plurality of power domains of the system-on-chip 1001 according to the voltage adjustment trigger signal and the adjustment target voltage information received by the voltage adjustment circuit. In other words, in the present embodiment, the mimo switch circuit 930 may sequentially output at least a portion of the plurality of frequency-divided circuit output clock signals CK2_ 1-CK 2_ N in a multi-stage switching manner from the high clock frequency to the low clock frequency in the second response period, so as to effectively maintain the operation of the plurality of power domains. And, the plurality of voltage regulating circuits can then gradually step down the operating voltage VDD to be stable during the voltage step-down period, so as to effectively suppress or reduce the generation of power noise. In the present embodiment, the voltage drop period and the second response period do not overlap.

In the present embodiment, when the control circuit 910 completes the voltage frequency adjustment operation, the state machine circuit 912 can output the state signal 907 to the register circuit 911 according to the current operating voltages VDD of the plurality of power domains and the switching results of the clock signals CK3_1 to CK3_ M of the plurality of power domains, for example, to clear the voltage frequency adjustment trigger records recorded in the register circuit 911. Also, the state machine circuit 912 may further output a status signal 908 to each of the plurality of power domains of the system-on-chip 1001 to notify each of the plurality of power domains that the voltage frequency adjustment operation thereof has been completed.

It should be noted that the voltage regulation circuits 1002_1 and 1002_ M and the corresponding voltage regulation trigger signal 9021_1, regulation target voltage information 9022_1, voltage regulation trigger signal 9021_ M, regulation target voltage information 9022_ M, interrupt signal 901_1, and interrupt signal 901_ M are only for convenience of explaining the case where the present disclosure includes a plurality of voltage regulation circuits, and the present disclosure does not limit the number of voltage regulation circuits.

Fig. 10 is a schematic diagram of a common dynamic voltage frequency adjustment circuit according to some embodiments of the disclosure. The common dynamic voltage frequency adjustment circuit shown in fig. 10 may be a case where one dynamic voltage frequency adjustment circuit is shared by a plurality of power domains in fig. 8B. As shown in fig. 10, the plurality of voltage regulation circuits may include a voltage regulation circuit 1110A and a voltage regulation circuit 1110B.

For example, the dynamic voltage frequency adjustment circuit 1130 may adjust the operating voltages of the power domains corresponding to the voltage adjustment circuit 1110A and the voltage adjustment circuit 1110B through the voltage adjustment circuit 1110A and the voltage adjustment circuit 1110B, respectively. For example, the dynamic voltage frequency adjustment circuit 1130 transmits status information and clock signals of a plurality of power domains to the chip internal circuit 1140 via the status and control bus 1105; the on-chip circuitry 1140 may communicate power information, a voltage identification table signal, a divide-by-circuit input clock signal, and a reference clock to the dynamic voltage frequency adjustment circuit 1130 via the status and control bus 1105.

For example, the dynamic voltage frequency adjustment circuit 1130 may send a voltage management signal to the voltage regulation circuit 1110A through the peripheral circuit 1120 via a voltage management bus 1104A corresponding to the voltage regulation circuit 1110A, where the voltage management signal may include a voltage regulation trigger signal 1101A and regulation target voltage information 1102A; the voltage regulation circuit 1110A may send an interrupt signal 1103A to the dynamic voltage frequency adjustment circuit 1130 through the peripheral circuit 1120 and over the voltage management bus 1104A. The signal transmission and control relationship between the dynamic voltage frequency adjustment circuit 1130 and the voltage adjustment circuit 1110B, and the related voltage management bus 1104B, the voltage adjustment trigger signal 1101B, the adjustment target voltage information 1102B, and the interrupt signal 1103B are the same as the dynamic voltage frequency adjustment circuit 1130 and the voltage adjustment circuit 1110A, and are not repeated herein.

Fig. 11 is a schematic diagram of a dedicated dynamic voltage frequency adjustment circuit according to some embodiments of the disclosure. The dedicated-type dynamic voltage frequency adjustment circuit shown in fig. 11 may be a case where each of the plurality of power domains in fig. 8A corresponds to each of the plurality of dynamic voltage frequency adjustment circuits one to one. As shown in fig. 11, the plurality of voltage regulation circuits may include a voltage regulation circuit 1210A and a voltage regulation circuit 1210B, the plurality of dynamic voltage frequency adjustment circuits may include a dynamic voltage frequency adjustment circuit 1230A and a dynamic voltage frequency adjustment circuit 1230B, and the plurality of on-chip circuits may include an on-chip circuit 1240A and an on-chip circuit 1240B.

For example, the dynamic voltage frequency adjustment circuit 1230A may adjust the operating voltage of the power domain corresponding to the voltage adjustment circuit 1210A through the voltage adjustment circuit 1210A. For example, the dynamic voltage frequency adjustment circuit 1230A may communicate status information to the on-chip circuitry 1240A via the status and control bus 1205A as well as clock signals for multiple power domains; the on-chip circuitry 1240A may communicate power information, the voltage identification table signal, the first clock signal, and the reference clock to the dynamic voltage frequency adjustment circuitry 1230A via the status and control bus 1205A. The signal transmission, control relationship and related status between the dynamic voltage and frequency adjusting circuit 1230B and the chip internal circuit 1240B and the control bus 1205B are the same as the dynamic voltage and frequency adjusting circuit 1230A and the chip internal circuit 1240A, and are not described herein again.

For example, the dynamic voltage frequency adjustment circuit 1230A may send a voltage management signal to the voltage regulation circuit 1210A through the peripheral circuit 1220 via the voltage management bus 1204A corresponding to the voltage regulation circuit 1210A, where the voltage management signal may include the voltage regulation trigger signal 1201A and the regulation target voltage information 1202A; the voltage regulation circuit 1210A may send an interrupt signal 1203A to the dynamic voltage frequency adjustment circuit 1230A through the peripheral circuit 1220 and over the voltage management bus 1204A. The signal transmission and control relationship between the dynamic voltage frequency adjustment circuit 1230B and the voltage adjustment circuit 1210B, and the related voltage management bus 1204B, the voltage adjustment trigger signal 1201B, the adjustment target voltage information 1202B, and the interrupt signal 1203B are the same as the dynamic voltage frequency adjustment circuit 1230A and the voltage adjustment circuit 1210A, and are not repeated herein.

Fig. 12 is a schematic diagram of a level shift circuit provided by some embodiments of the present disclosure. The level shift circuit shown in fig. 12 can be used for signal communication between the power domain and the power normally-on domain in fig. 8A or 8B. As shown in fig. 12, the on-chip network 1330 and the dynamic voltage frequency adjustment circuit 1340 are located in the power supply normally-on domain.

For example, since the operating voltage of the power domain 1310 is dynamically changed according to the adjustment of the dynamic voltage frequency, and the on-chip network 1330 is located in the power normally-on domain and needs a stable operating voltage, when the on-chip network 1330 cannot directly transmit signals to the power domain 1310, for example, the on-chip network 1330 may transmit signals to the power domain 1310 through the level shifter 1320. For example, the power conversion circuit 1320 may level convert the input signal 1302 of the on-chip network 1330 into a level-converted input signal 1301 and transmit the level-converted input signal to the power domain 1310.

For example, since the power domain 1310 may be in an off state in some cases, the power domain 1310 may also need to Clamp (Clamp) a signal when transmitting the signal to the on-chip network 1330 to ensure that the on-chip network 1330 in the power-normally-on domain is not affected by the off voltage of the power domain 1310 in the off state. The clamp can be generated by a special circuit or a core detection circuit of a system-on-chip. The power domain 1310 may transmit signals to the network-on-chip 1330 through the clamp level shifting circuit 1350. For example, the clamp power conversion circuit 1350 may clamp the output signal 1303 of the power domain 1310 to obtain a clamp level conversion input signal 1304, and transmit the clamp level conversion input signal to the on-chip network 1330.

For example, the process of the dynamic voltage frequency adjustment circuit 1340 transmitting the clock signal 1306 and the level shift clock signal 1305 to the power domain 1310 through the level shift circuit 1320 and the process of the power domain 1310 transmitting the interrupt signal 1307 and the clamp level shift interrupt signal 1308 to the dynamic voltage frequency adjustment circuit 1340 through the clamp level shift circuit 1350 are similar to the above-mentioned signal transmission process between the on-chip network 1330 and the power domain 1310, and are not described herein again.

Fig. 13 is a schematic diagram of a level shift circuit provided by some embodiments of the present disclosure. The level shifting circuit shown in fig. 13 may be used for signal communication between the power domains in fig. 8A or 8B.

For example, since the power domain 1410A may be in an off state in some cases, the power domain 1410A may also need to Clamp (Clamp) a signal when transmitting a signal to the power domain 1410B to ensure that the power domain 1410B is not affected by the off voltage of the power domain 1410A in the off state. The clamp can be generated by a special circuit or a core detection circuit of a system-on-chip. The power domain 1410A may pass inter-power domain signals to the power domain 1410B through the clamping level shifting circuit 1420. For example, the clamp power conversion circuit 1420 may clamp the inter-domain power signal 1401 from the power domain 1410A to obtain a clamp level-converted inter-domain power signal 1402, which is then transmitted to the power domain 1410B. The process of the power domain 1410B transmitting the inter-domain signal 1404 and the clamping the inter-domain signal 1403 to the power domain 1410A is the same as the process of the power domain 1410A transmitting the signal to the power domain 1410B, and the description thereof is omitted.

The level conversion circuit avoids the situations of excessive power leakage and wrong transmitted signal values caused by large difference of working voltages between different domains. The clamp level conversion circuit can also support the power domain to ensure that the signal is always at a high potential when the working voltage is in an off state (such as a power-down state), so as to ensure the validity of the signal value and the operation related to the signal.

Fig. 14 is a schematic diagram of clock signals and the ramp up of operating voltage for some embodiments of the present disclosure. Referring to fig. 9 and 14, when one of the power domains of the soc 1001 performs the voltage frequency up-conversion operation OP1, the dynamic voltage frequency adjustment circuit 900 may adjust the frequency of the operating voltage VDD and the clock signal CK3_1 corresponding to the power domain among the clock signals CK3_1 to CK3_ M of the power domains during the adjustment period P1 from time t0 to time t 5. Specifically, at time t0, the state machine circuit 912 may first output the voltage adjustment trigger signal and the adjustment target voltage information to the voltage adjustment circuit corresponding to the power domain, so that the operating voltage VDD output by the voltage adjustment circuit corresponding to the power domain is gradually stepped up from the voltage V1 to the voltage V2 between time t0 and time t 1.

Moreover, after the operating voltage VDD is adjusted to the stable voltage V2, at time t2, the register circuit 911 may then output the control signal 906 to the state machine circuit 912, so that the state machine circuit 912 may control the multi-input multi-output switch circuit 930 to switch from outputting the clock signal CK3_1 (e.g., the frequency-dividing circuit output clock signal CK2_1) of the power domain with the clock frequency f0 to outputting the clock signal CK3_1 (e.g., the frequency-dividing circuit output clock signal CK2_2) of the power domain with the clock frequency f1, for example.

Then, after waiting for the ramp-up waiting period of several reference clock cycles of the reference clock signal CKR, at time t3, the state machine circuit 912 may control the multiple-input multiple-output switch circuit 930 to switch, for example, from outputting the clock signal CK3_1 of the power domain having the clock frequency f1 (e.g., the frequency-dividing circuit output clock signal CK2_2) to outputting the clock signal CK3_1 of the power domain having the clock frequency f2 (e.g., the frequency-dividing circuit output clock signal CK2_ 3).

Then, after waiting for a frequency-up waiting period of several reference clock cycles of the reference clock signal CKR, at time t4, the state machine circuit 912 may control the mimo switch circuit 930 to switch, for example, from outputting the clock signal CK3_1 of the power domain having the clock frequency f2 (e.g., the frequency-dividing circuit output clock signal CK2_3) to outputting the clock signal CK3_1 of the power domain having the clock frequency f3 (e.g., the frequency-dividing circuit output clock signal CK2_ 4). In this way, the dynamic voltage frequency adjustment circuit 900 completes the frequency up operation of the clock signal CK3_1 of the power domain at time t 4.

Thus, when the performance of the soc 1001 needs to be improved, the dynamic voltage frequency adjustment circuit 900 can dynamically adjust the clock frequency of the operating voltage VDD and the clock signal CK3_1 of the power domain in real time in response to the voltage frequency adjustment requirement.

Fig. 15 is a schematic diagram of clock signals and regulation of operating voltage drops for some embodiments of the present disclosure. Referring to fig. 9 and fig. 15, when the soc 1001 performs the voltage frequency down operation OP2, the dynamic voltage frequency adjustment circuit 900 may adjust the operating voltage VDD and the clock frequency of the clock signal CK3_1 of the power domain during the adjustment period P2 from time t6 to time t 11. Specifically, at time t7, the register circuit 911 may first output the control signal 906 to the state machine circuit 912, such that the state machine circuit 912 may control the mimo switch circuit 930 to switch from outputting the clock signal CK3_1 (e.g., the frequency-divided circuit output clock signal CK2_4) of the power domain with the clock frequency f0 'to outputting the clock signal CK3_1 (e.g., the frequency-divided circuit output clock signal CK2_3) of the power domain with the clock frequency f 1', for example.

Then, after waiting for a down-conversion waiting period of several reference clock cycles of the reference clock signal CKR, at time t8, the state machine circuit 912 may control the multi-input multi-output switch circuit 930 to switch, for example, from outputting the clock signal CK3_1 of the power domain having the clock frequency f1 '(e.g., the frequency-dividing circuit output clock signal CK2_3) to outputting the clock signal CK3_1 of the power domain having the clock frequency f 2' (e.g., the frequency-dividing circuit output clock signal CK2_ 2).

Then, after waiting for a down waiting period of several reference clock cycles of the reference clock signal CKR, at time t9, the state machine circuit 612 can control the multi-input multi-output switch circuit 930 to switch, for example, from outputting the clock signal CK3_1 (e.g., the frequency division circuit output clock signal CK2_2) of the power domain with the clock frequency f2 'to outputting the clock signal CK3_1 (e.g., the frequency division circuit output clock signal CK2_1) of the power domain with the clock frequency f 3'. In this way, the dynamic voltage frequency adjustment circuit 900 can complete the down-conversion operation of the clock signal CK3_1 of the power domain at time t 9.

After the soc 1001 completes the down-conversion of the clock signal CK3_1 of the power domain, the state machine circuit 912 can then output the voltage adjustment trigger signal and the adjustment target voltage information to one of the voltage adjustment circuits (e.g., one of the voltage adjustment circuits 1002_1 to 1002_ M) so that the operating voltage VDD outputted by the voltage adjustment circuit is gradually stepped down from the voltage V1 'to the voltage V2' between time t10 and time t 11.

Thus, when the performance of the soc 1001 needs to be degraded, the dynamic voltage frequency adjustment circuit 900 can dynamically adjust the operating voltage VDD and the clock signal CK3_1 of the power domain in real time in response to the voltage frequency adjustment requirement. In addition, when the system on chip 701 has an over-current event, the dynamic voltage frequency adjustment circuit 900 can also dynamically adjust the clock frequency of the operating voltage VDD and the clock signal CK3_1 of the power domain in real time to achieve the over-current protection function. In this regard, the dynamic voltage frequency adjustment circuit 900 may enable the system-on-chip 1001 to maintain operation in a low performance manner, so as to avoid a situation where one or more power domains of the system-on-chip 1001 stop operating due to an over-current event, a processing core of the power domain operates abnormally, and even the chip is damaged.

It is noted that the voltage frequency up-regulation operation OP1 in fig. 14 and the voltage frequency down-regulation operation OP2 in fig. 15 may be independent voltage frequency adjustment events. In other embodiments of the present disclosure, the dynamic voltage frequency adjustment circuit 900 may perform the voltage frequency up operation OP2 after the voltage frequency up operation OP1, or perform the voltage frequency up operation OP1 after the voltage frequency down operation OP2, or perform the voltage frequency up operation OP1 or the voltage frequency down operation OP2 continuously, but the invention is not limited to the number and sequence of the dynamic voltage frequency adjustment circuit 900 performing the voltage frequency up and the voltage frequency down. Meanwhile, in the above description, taking the power domain corresponding to the clock signal CK3_1 of the plurality of clock signals CK3_1 to CK3_ M as an example, the voltage frequency rising operation and the voltage frequency falling operation of the power domain corresponding to the plurality of clock signals CK3_2 to CK3_ M are the same as those of the power domain corresponding to the clock signal CK3_1, and are not repeated here.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above are merely specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be determined by the scope of the claims.

Claims

1. A system-on-chip comprising: at least one dynamic voltage frequency adjustment circuit, wherein,

the system-on-chip comprises at least two power domains,

the at least one dynamic voltage frequency adjustment circuit is configured to enable dynamic adjustment of an operating voltage and a clock frequency of each of the at least two power domains.

2. The system-on-chip of claim 1, wherein the at least one dynamic voltage frequency adjustment circuit comprises a first dynamic voltage frequency adjustment circuit,

the first dynamic voltage frequency adjustment circuit is configured to enable dynamic adjustment of an operating voltage and a clock frequency of a plurality of the at least two power domains.

3. The system-on-chip of claim 2, wherein the first dynamic voltage frequency adjustment circuit comprises:

a frequency dividing circuit configured to receive a first clock signal and output a plurality of second clock signals having a plurality of clock frequencies;

a multiple-input multiple-output switch circuit configured to receive the plurality of second clock signals and output a plurality of third clock signals for the plurality of power domains, wherein the plurality of third clock signals are in one-to-one correspondence with the plurality of power domains; and

the control circuit is coupled with the frequency dividing circuit, the multiple-input multiple-output switch circuit and the voltage regulating circuit;

wherein the control circuit is configured to output a voltage management signal to the voltage regulation circuit and output a selection signal to the multiple-input multiple-output switch circuit when the system-on-chip performs a voltage frequency regulation operation,

the voltage regulation circuit is configured to regulate the operating voltage provided to the plurality of power domains according to the voltage management signal when the system-on-chip performs a voltage frequency regulation operation,

the multiple-input multiple-output switch circuit is configured to output the plurality of third clock signals to the plurality of power domains according to the selection signal.

4. The system-on-chip of claim 1, wherein the at least one dynamic voltage frequency adjustment circuit comprises a second dynamic voltage frequency adjustment circuit,

the second dynamic voltage frequency adjustment circuit is configured to enable dynamic adjustment of an operating voltage and a clock frequency of one of the at least two power domains.

5. The system-on-chip of any one of claims 1-4,

the at least one dynamic voltage frequency adjustment circuit is configured to transmit signals to each of the at least two power domains through a level shifting circuit,

each of the at least two power domains is configured to output a signal through a level shifting circuit having a clamping function.

6. A dynamic voltage frequency adjustment circuit applied to a system-on-chip including a plurality of power domains, wherein the dynamic voltage frequency adjustment circuit comprises:

7. The dynamic voltage frequency adjustment circuit of claim 6, wherein in the event that the voltage frequency adjustment operation comprises a voltage frequency scaling operation corresponding to at least one of the plurality of power domains, the control circuit outputs the voltage management signal to the voltage adjustment circuit first to cause the voltage adjustment circuit to scale up the operating voltage of the at least one power domain in accordance with the voltage management signal, and when the operating voltage of the at least one power domain is scaled up to be stable, the control circuit then outputs the selection signal to the multiple-input multiple-output switch circuit to cause the multiple-input multiple-output switch circuit to scale up the clock frequency of at least one third clock signal output to the at least one power domain in accordance with the selection signal.

8. The dynamic voltage frequency adjustment circuit of claim 7, wherein in a case where the voltage frequency adjustment operation includes a voltage frequency adjustment operation corresponding to at least one of the plurality of power domains, the voltage adjustment circuit first steps up an operating voltage of the at least one power domain, and when the operating voltage of the at least one power domain is adjusted to be stable, the mimo switching circuit then steps up a clock frequency of the at least one third clock signal output to the at least one power domain in a low clock frequency to high clock frequency and switching in multiple stages.

9. The dynamic voltage frequency adjustment circuit of claim 6, wherein in a case that the voltage frequency adjustment operation comprises a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, the control circuit first outputs the selection signal to the multiple-input multiple-output switch circuit to cause the multiple-input multiple-output switch circuit to adjust down the clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal, and when the clock frequency of the at least one third clock signal of the at least one power domain is adjusted down to be stable, the control circuit outputs the voltage management signal to the voltage adjustment circuit to cause the voltage adjustment circuit to adjust down the operating voltage of the at least one power domain according to the voltage management signal.

10. The dynamic voltage frequency adjustment circuit of claim 9, wherein in the case that the voltage frequency adjustment operation comprises a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, the multiple input multiple output switch circuit first steps down the clock frequency of the at least one third clock signal output to the at least one power domain in a high to low clock frequency and multi-phase switching manner, and when the clock frequency of the at least one third clock signal of the at least one power domain is adjusted down to be stable, the voltage adjustment circuit then steps down the operating voltage of the at least one power domain.

11. A dynamic voltage frequency adjustment circuit according to any of claims 6-10, wherein the control circuit comprises:

the state machine circuit is coupled with the frequency division circuit and the MIMO switch circuit; and

the register circuit is coupled with the state machine circuit;

the register circuit is configured to output a control signal to the state machine circuit while the system-on-chip performs the voltage frequency adjustment operation,

the state machine circuit is configured to output the voltage management signal to the voltage regulation circuit and output the selection signal to the multiple-input multiple-output switch circuit according to the control signal when the system-on-chip performs a voltage frequency regulation operation.

12. The dynamic voltage frequency adjustment circuit of claim 11, wherein the voltage management signal includes a voltage regulation trigger signal and regulation target voltage information,

the voltage regulation circuit is configured to regulate an operating voltage of at least one of the plurality of power domains to a target voltage according to the voltage regulation trigger signal regulation and the regulation target voltage information when the system-on-chip performs a voltage frequency regulation operation.

13. The dynamic voltage frequency adjustment circuit of claim 11, wherein the state machine circuit is further configured to output a divided signal to the dividing circuit according to the control signal to cause the dividing circuit to output the plurality of second clock signals according to the divided signal when the system-on-chip performs a voltage frequency adjustment operation.

14. The dynamic voltage frequency adjustment circuit of any of claims 6-10, wherein the multiple-input multiple-output switch comprises a plurality of multiplexers in one-to-one correspondence with the plurality of power domains,

each of the plurality of multiplexers is configured to receive at least a portion of the plurality of second clock signals and output a third clock signal for a power domain corresponding to the each multiplexer.

15. A dynamic voltage frequency adjustment circuit according to any of claims 6 to 10, wherein the control circuit is configured to receive an interrupt signal output by the voltage regulation circuit and to decide whether to generate the voltage management signal and the selection signal in dependence on the interrupt signal.

16. A dynamic voltage frequency adjustment circuit according to any of claims 6-10, wherein the control circuit is configured to generate the voltage management signal and the selection signal based on a voltage identification table and current voltage information of the voltage regulation circuit.

17. A dynamic voltage frequency adjustment method is applied to a system-on-chip comprising a plurality of power domains, wherein the dynamic voltage frequency adjustment method comprises the following steps:

receiving the first clock signal through a frequency dividing circuit and outputting a plurality of second clock signals with a plurality of clock frequencies;

receiving the plurality of second clock signals through a multiple-input multiple-output (MIMO) switch circuit, and outputting a plurality of third clock signals for the plurality of power domains, wherein the plurality of third clock signals correspond to the plurality of power domains one to one;

when the system-on-chip performs the voltage frequency adjustment operation,

the control circuit outputs a voltage management signal to the voltage regulating circuit and outputs a selection signal to the multiple input multiple output switch circuit, the voltage regulating circuit regulates working voltages provided to the multiple power domains according to the voltage management signal, and the multiple input multiple output switch circuit outputs the multiple third clock signals to the multiple power domains according to the selection signal.

18. The dynamic voltage frequency adjustment method of claim 17, wherein in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment operation corresponding to at least one of the plurality of power domains, the voltage management signal is first output to the voltage adjustment circuit by the control circuit to cause the voltage adjustment circuit to adjust the operating voltage of the at least one power domain according to the voltage management signal, and when the operating voltage of the at least one power domain is adjusted to be stable, the selection signal is output to the multiple input multiple output switch circuit by the control circuit to cause the multiple input multiple output switch circuit to adjust the clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal.

19. The dynamic voltage frequency adjustment method of claim 18, wherein causing the voltage regulation circuit to boost the operating voltage of the at least one power domain in accordance with the voltage management signal comprises: enabling the voltage regulating circuit to slowly step up the working voltage of the at least one power domain;

causing the mimo switching circuit to ramp up a clock frequency of at least one third clock signal output to the at least one power domain in accordance with the selection signal, comprising: and gradually increasing the clock frequency of the at least one third clock signal output to the at least one power domain by the MIMO switch circuit in a low-clock frequency to high-clock frequency and multi-stage switching manner.

20. The dynamic voltage frequency adjustment method according to claim 17, wherein in a case that the voltage frequency adjustment operation includes a voltage frequency adjustment down operation corresponding to at least one of the plurality of power domains, the selection signal is first output to the multiple-input multiple-output switch circuit through the control circuit, so that the multiple-input multiple-output switch circuit adjusts down the clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal, and when the clock frequency of the at least one third clock signal of the at least one power domain is adjusted down to be stable, the voltage management signal is output to the voltage adjustment circuit through the control circuit, so that the voltage adjustment circuit adjusts down the operating voltage of the at least one power domain according to the voltage management signal.

21. The dynamic voltage frequency adjustment method of claim 20, wherein causing the multiple-input multiple-output switching circuit to down-regulate a clock frequency of at least one third clock signal output to the at least one power domain according to the selection signal comprises:

gradually reducing the clock frequency of the at least one third clock signal output to the at least one power domain by the multiple-input multiple-output switch in a high-clock-frequency to low-clock-frequency and multi-stage switching manner;

causing the voltage regulation circuit to regulate down the operating voltage of the at least one power domain in accordance with the voltage management signal, comprising: and enabling the voltage regulating circuit to slowly step down the working voltage of the at least one power domain.

22. A dynamic voltage frequency adjustment method according to any one of claims 17-21, wherein the control circuit comprises:

the register circuit is coupled with the state machine circuit;

when the system-on-chip performs the voltage frequency adjustment operation, the control circuit outputs the voltage management signal to the voltage adjustment circuit and outputs the selection signal to the multiple-input multiple-output switch circuit, including:

enabling the register circuit to output a control signal to the state machine circuit; and

and enabling the state machine circuit to output the voltage management signal to the voltage regulating circuit according to the control signal and output the selection signal to the multi-input multi-output switch circuit.

23. The dynamic voltage frequency adjustment method of claim 22, wherein the voltage management signal includes a voltage regulation trigger signal and regulation target voltage information,

when the system-on-chip performs the voltage frequency adjustment operation, adjusting, by the voltage adjustment circuit, the operating voltages provided to the plurality of power domains according to the voltage management signal, including:

causing the voltage regulation circuit to regulate an operating voltage of at least one of the plurality of power domains to a target voltage in accordance with the voltage regulation trigger signal regulation and the regulation target voltage information.

24. The dynamic voltage frequency adjustment method of claim 22, further comprising:

when the system-on-chip performs the voltage frequency adjustment operation, the state machine circuit is enabled to output a frequency division signal to the frequency division circuit according to the control signal, so that the frequency division circuit outputs the plurality of second clock signals according to the frequency division signal.

25. The dynamic voltage frequency adjustment method of any one of claims 17-21, wherein the multiple-input multiple-output switch comprises a plurality of multiplexers in one-to-one correspondence with the plurality of power domains,

receiving, by the multiple-input multiple-output switch circuit, the plurality of second clock signals, outputting the plurality of third clock signals for the plurality of power domains, comprising:

receiving at least a portion of the plurality of second clock signals through each of the plurality of multiplexers, outputting a third clock signal for a power domain corresponding to the each multiplexer.

26. A method of dynamic voltage frequency adjustment according to any of claims 17-21, further comprising: and receiving an interrupt signal output by the voltage regulating circuit through the control circuit, and determining whether to generate the voltage management signal and the selection signal according to the interrupt signal.

27. The dynamic voltage frequency adjustment method of any one of claims 17-21, wherein outputting, by the control circuit, the voltage management signal to the voltage regulation circuit and the selection signal to the multiple-input multiple-output switch circuit comprises:

and enabling the control circuit to generate the voltage management signal and the selection signal according to a voltage identification table and the current voltage information of the voltage regulating circuit.