CN114127936A - Imaging device, method for supplying power to imaging device and related equipment - Google Patents
Imaging device, method for supplying power to imaging device and related equipment Download PDFInfo
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Abstract
The application provides an imaging device, a method for supplying power to the imaging device and related equipment, the imaging device comprises a semiconductor substrate, a first trap and a second trap are arranged on two sides of the semiconductor substrate, a first insulating medium layer and a control gate electrode are sequentially arranged on the surface of the first trap, the size of the voltage applied to the control gate electrode and the quantity of charges stored in the first trap are in positive correlation. Under the environment of different illumination intensities, voltages with different magnitudes can be applied to the control gate electrode, and the larger the voltage applied to the control gate electrode is, the larger the capacitance capacity of the first well is, so that the full well capacity of the imaging device can meet different illumination environments.
Description
The present application relates to the field of electronic circuit technology, and more particularly, to an imaging device, a method for powering an imaging device, and related apparatus.
An image sensor is a device for converting photoelectrons into electrical signals, and a partial structure of an imaging device provided in the related art for constituting the sensor is described below with reference to fig. 1.
The imaging device comprises a semiconductor substrate 100, an N-type impurity is implanted at the outer edge of the semiconductor substrate 100 to form a shallow N buried layer 101, the N buried layer 101 and the semiconductor substrate 100 close to the N buried layer 101 form a Photodiode (PD) 103, when external incident light irradiates on the PD103, the PD103 generates photoelectrons corresponding to the incident light, and the photoelectrons can transfer into a floating diffusion node 104 to generate an electric signal for acquiring a corresponding image.
However, as the size of the image sensor is continuously reduced, the area of the PD103 of a single imaging device is reduced, so that the reduced-area N buried layer 101 cannot provide sufficient Full Well Capacity (FWC) for the imaging device, and the reduction of the full well capacity causes the signal-to-noise ratio, the sensitivity, and the like of the imaging device to be reduced.
Disclosure of Invention
An imaging device, a method for powering an imaging device, and related apparatus are provided that have a full well capacity that is matched to illumination intensities such that the full well capacity of the imaging device can meet different illumination intensities.
A first aspect of the embodiments of the present application provides an imaging device, including a semiconductor substrate, where a first well and a second well are respectively disposed on two sides of the semiconductor substrate through ion implantation doping, the semiconductor substrate and the second well have a first doping type, and the first well has a second doping type; the surface of the first trap is sequentially provided with a first insulating medium layer and a control gate electrode, and the magnitude of the voltage applied to the control gate electrode is in positive correlation with the quantity of the charges stored in the first trap.
It is understood that, in the environment of different light intensities, voltages of different magnitudes may be applied to the control gate electrode, that is, the stronger the light in the light environment in which the imaging device is located, the larger the voltage applied to the control gate electrode, in the case where the voltage is applied to the control gate electrode, the first well becomes a capacitor for storing charges, and the larger the voltage applied to the control gate electrode, the larger the capacitance capacity of the first well, that is, the positive correlation between the magnitude of the voltage applied to the control gate electrode and the amount of charges that can be stored in the first well is obtained. Therefore, when the illumination intensity is higher, high voltage can be applied to the control gate electrode, so that the first well can contain more charges, and the full-well capacity of the imaging device is improved; when the illumination intensity is weak, weak voltage can be applied to the control gate electrode, so that the full-well capacity of the first well can meet the requirement under weak light, and the waste of power consumption is avoided.
Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, a second insulating medium layer is disposed on a surface of the control gate electrode facing the semiconductor substrate, an accommodating cavity is formed between the first insulating medium layer and the second insulating medium layer, and a floating gate for storing charges is disposed in the accommodating cavity.
It can be appreciated that in an imaging device, the floating gate for storing charge is added, thereby increasing the full well capacity of the imaging device and increasing the amount of charge that can be stored by the imaging device.
Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, along the transverse direction of the imaging device, a channel region is formed between the first well and the second well, along a direction away from the channel region, the surface of the channel region is sequentially provided with the first insulating medium layer and the charge transfer transistor, the charge transfer transistor is configured to enable charges in the first well to be transferred to a floating diffusion node via the channel region, and the floating diffusion node is located in the second well.
Therefore, the floating diffusion nodes are arranged in the second trap, so that the second trap can effectively isolate the floating diffusion nodes, charges are effectively prevented from entering the floating diffusion nodes in the exposure process, the interference of the charges on the floating diffusion nodes in the exposure process is avoided, the accuracy of reading the number of the charges is effectively improved, and the quality of the generated image is improved.
Based on the first aspect of the present embodiment, in an optional implementation manner of the first aspect of the present embodiment, the first insulating medium layer is provided with at least one window, the floating gate and the first well are connected through the window, and the charge transfer transistor is further configured to enable charges in the floating gate to be transferred into the floating diffusion node through the channel region.
Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, the opening is perpendicular to the direction of the imaging device, the opening includes a first opening and a second opening that are arranged oppositely, the first opening is located toward the first insulating medium layer on the surface of the floating gate, the second opening is located toward the first insulating medium layer on the surface of the first well, and the first opening and the second opening are conducted with each other.
Based on the first aspect of the present embodiment, in an optional implementation manner of the first aspect of the present embodiment, the floating gate extends to the second opening via the first opening along the window-opening direction, and the floating gate located at the second opening is connected to the first well.
It is understood that, in the case of completing the disposing of the first insulating medium layer, a window may be disposed directly through the first insulating medium layer, and then the floating gate may be directly deposited on the surface of the first insulating medium layer by, for example, a Chemical Vapor Deposition (CVD) method, so that the floating gate deposited in the window is directly connected to the first well.
Based on the first aspect of the present embodiment, in an optional implementation manner of the first aspect of the present embodiment, the first well extends to the first opening via the second opening along the window-opening direction, and is located at the first opening where the floating gate is connected to the first well.
Based on the first aspect of the present embodiment, in an optional implementation manner of the first aspect of the present embodiment, the floating gate extends to the inside of the window through the first opening, the first well extends to the inside of the window through the second opening, and the floating gate and the first well which are located inside the window are connected.
It can be understood that the direct connection between the first well and the floating gate is realized through the windowing, the full well capacity of the imaging device is improved, the charge transfer efficiency and the quality of the obtained image are improved, the first insulating medium layer is not damaged in the charge transfer process through the windowing, the requirement on the thickness of the first insulating medium layer is reduced, the accuracy of the read charge quantity and the quality of the image are effectively improved due to the fact that the first insulating medium layer is effectively prevented from being damaged, the service life of the imaging device is prolonged in the using process, and the reliability of the imaging device is improved.
Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, an isolation dielectric layer is disposed between the first well and the first insulating dielectric layer along a direction perpendicular to the imaging device, and the isolation dielectric layer is a high-density P ion implantation medium.
It can be understood that the isolation dielectric layer is arranged between the first well and the first insulation dielectric layer, so that the first well and the first insulation dielectric layer are effectively isolated, the generation of dark current is reduced, the influence of the dark current on reading the quantity of the charges stored in the floating gate is avoided, the accuracy of reading the quantity of the charges is improved, and the quality of images is further improved.
Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, a cross-sectional area of the first well is larger than a cross-sectional area of the second well along a lateral direction of the imaging device.
It can be understood that, because the cross-sectional area of the first well is greater than that of the second well, the photosensitive area for performing the photosensitive operation to generate the charges in the exposure time period is effectively increased.
Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, along a lateral direction of the imaging device, a first distance is provided between the first well and the second well, a second distance is provided between the first insulating dielectric layer and the second well, and the first distance is smaller than the second distance.
It can be understood that, because the first distance is smaller than the second distance, the success rate and the transfer rate of the charges stored in the floating gate transferred into the floating diffusion node through the first well are improved, and the situation that the charges stored in the floating gate cannot be successfully transferred into the floating diffusion node is effectively avoided.
Based on the first aspect of the embodiment of the present application, in an optional implementation manner of the first aspect of the embodiment of the present application, the first doping type is n-type impurity doping, and the second doping type is p-type impurity doping; or, the first doping type is p-type impurity doping, and the second doping type is n-type impurity doping.
A second aspect of embodiments of the present application provides a method for powering an imaging device, the method being for a logic control circuit electrically connected to the imaging device, the method comprising:
the logic control circuit adjusts the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is in positive correlation with the amount of the charge stored in the imaging device.
It can be understood that, the quantity of the charges that can be stored by the photosensitive transistor with the photoelectric effect is in positive correlation with the illumination intensity, that is, the greater the light intensity in the illumination environment where the photosensitive transistor is located, the greater the quantity of the charges that the photosensitive transistor needs to store, the weaker the light intensity in the illumination environment where the photosensitive transistor is located, the smaller the quantity of the charges that the photosensitive transistor needs to store, and the logic control circuit can adjust the magnitude of the voltage applied to the control gate electrode according to the intensity of the illumination in the illumination environment where the photosensitive transistor is located, so that the quantity of the charges that the imaging device can store can match the requirements in different illumination environments.
Based on the second aspect of the embodiment of the present application, in an optional implementation manner of the second aspect of the embodiment of the present application, the method specifically includes:
a logic control circuit acquires a target amount of charge stored by the imaging device in a first exposure time period; adjusting a voltage applied to a control gate electrode of the imaging device in a second exposure period according to the target number, wherein the magnitude of the voltage applied to the control gate electrode is in positive correlation with the target number, and the first exposure period is earlier than the second exposure period.
It can be understood that, if the logic control circuit determines that the photosensitive transistor is in a strong light environment in the first exposure time period, the logic control circuit may increase the voltage applied to the control gate electrode, so as to increase the capacitance of the first well, so that the first well can accommodate more charges in the second exposure time period, and thus the full well capacity of the photosensitive transistor shown in this embodiment can meet the requirement of strong light; if the logic control circuit determines that the photosensitive transistor is in a weak illumination environment in the first exposure time period, the logic control circuit can reduce the voltage applied to the control gate electrode, so that the capacitance of the first well is reduced, the capacity of the first well capable of containing charges is matched with the current illumination in the second exposure time period, the power consumption of applying the voltage to the control gate electrode is effectively saved, and the waste of the power consumption is avoided under the condition that the full well capacity of the photosensitive transistor can meet the current illumination environment.
Based on the second aspect of the embodiment of the present application, in an optional implementation manner of the second aspect of the embodiment of the present application, the adjusting the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number includes: and if the target number is greater than or equal to a preset value, increasing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
It can be understood that, when the logic control circuit determines that the target number is greater than or equal to the preset value, the logic control circuit may determine that the imaging device is in an environment with strong light in the first exposure time period, and the logic control circuit may increase the voltage applied to the control gate electrode, so as to increase the capacitance of the first well, so that in the second exposure time period, the first well can accommodate more charges, and thus the full-well capacity of the light sensing transistor shown in this embodiment can meet the requirement of strong light.
Based on the second aspect of the embodiment of the present application, in an optional implementation manner of the second aspect of the embodiment of the present application, the adjusting the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number includes: and if the target number is less than a preset value, reducing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
It can be understood that, when the logic control circuit determines that the target number is smaller than the preset value, the logic control circuit may determine that the imaging device is in a low-light environment in the first exposure time period, and the logic control circuit may reduce the voltage applied to the control gate electrode, so that in the second exposure time period, the full well capacity of the first well may meet the requirement in the low-light environment, and waste of power consumption is avoided.
Based on the second aspect of the embodiment of the present application, in an optional implementation manner of the second aspect of the embodiment of the present application, the method further includes: acquiring a preset voltage regulation list, wherein the preset voltage regulation list comprises corresponding relations between different charge quantity ranges and different voltage values; adjusting the voltage applied to the control gate electrode of the imaging device for a second exposure period according to the target number comprises: determining target voltages corresponding to the target number according to the preset voltage adjusting list; applying the target voltage to a control gate electrode of the imaging device for a second exposure time period.
It can be understood that dynamic adjustment of the target voltage applied to the control gate electrode is realized through the preset voltage adjustment list, so that the imaging device can be matched with more various illumination environments, the matching degree of the imaging device and the illumination environments is improved, and the full-well capacity of the imaging device can meet the requirements of the current illumination environments after the target voltage is applied to the control gate electrode by the logic control circuit.
A third aspect of the embodiments of the present application provides a logic processing circuit, where the logic processing circuit is electrically connected to an imaging device, and the logic processing circuit includes: the adjusting unit is used for adjusting the voltage applied to the control gate electrode of the imaging device according to the charges stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is in positive correlation with the quantity of the charges stored in the imaging device.
Based on the third aspect of the present embodiment, in an optional implementation manner of the third aspect of the present embodiment, the roadbed processing circuit further includes an obtaining unit, configured to obtain a target number of charges stored in the imaging device in a first exposure time period; the adjusting unit is further configured to adjust a voltage applied to a control gate electrode of the imaging device in a second exposure period according to the target number, wherein the magnitude of the voltage applied to the control gate electrode is in positive correlation with the target number, and the first exposure period is earlier than the second exposure period.
Based on the third aspect of the embodiment of the present application, in an optional implementation manner of the third aspect of the embodiment of the present application, the adjusting unit is specifically configured to: and if the target number is greater than or equal to a preset value, increasing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
Based on the third aspect of the embodiment of the present application, in an optional implementation manner of the third aspect of the embodiment of the present application, the adjusting unit is specifically configured to: and if the target number is less than a preset value, reducing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
Based on the third aspect of the embodiment of the present application, in an optional implementation manner of the third aspect of the embodiment of the present application, the adjusting unit is specifically configured to: acquiring a preset voltage regulation list, wherein the preset voltage regulation list comprises corresponding relations between different charge quantity ranges and different voltage values; determining target voltages corresponding to the target number according to the preset voltage adjusting list; applying the target voltage to a control gate electrode of the imaging device for a second exposure time period.
A fourth aspect of the embodiments of the present application provides an image sensor, where the image sensor includes a pixel array and a logic control circuit, where the pixel array includes at least one imaging device, the imaging device is electrically connected to the logic control circuit, the imaging device is as shown in the above first aspect, and the logic control circuit is as shown in the above third aspect, which is not specifically described in detail.
A fifth aspect of embodiments of the present application provides an electronic device, which includes a processor and an image sensor, where the image sensor is as described in the fourth aspect above, and the processor is configured to acquire the image from the image sensor.
A sixth aspect of embodiments of the present application provides a storage medium having stored therein computer instructions that, when invoked by a logic control circuit, cause the logic control circuit to perform the method of the second aspect.
A seventh aspect of embodiments of the present application provides a computer program product, which includes computer program code, when called by a logic control circuit, causes the logic control circuit to execute the method shown in the second aspect.
Fig. 1 is a view showing an example of a structure of an imaging device provided in the prior art;
FIG. 2 is a diagram illustrating an exemplary structure of an electronic device according to an embodiment of the present disclosure;
FIG. 3 is a diagram illustrating an exemplary structure of a pixel array according to an embodiment of the present disclosure;
fig. 4 is a view showing another example of the structure of an imaging device provided in the prior art;
FIG. 5 is a side view cross-sectional structure of an embodiment of a phototransistor provided in the present application;
FIG. 6 is a side view cross-sectional structural illustration of one embodiment of an imaging device as provided herein;
FIG. 7 is a side view cross-sectional structural illustration of another embodiment of an imaging device as provided herein;
FIG. 8 is a side view cross-sectional structural illustration of another embodiment of an imaging device as provided herein;
FIG. 9 is a transfer diagram illustrating one embodiment of optoelectronics provided herein;
FIG. 10 is a flow chart illustrating steps of one embodiment of powering an imaging device as provided herein;
FIG. 11 is a flow chart illustrating steps of another embodiment for powering an imaging device as provided herein;
FIG. 12 is a flow chart illustrating steps in another embodiment for powering an imaging device as provided herein;
fig. 13 is a schematic structural diagram of an embodiment of a logic control circuit provided in the present application.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The term "and/or" appearing in the present application may be an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this application generally indicates that the former and latter related objects are in an "or" relationship.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Moreover, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.
To better understand the imaging device provided in the present application, the following first exemplifies the structure of an electronic device including the imaging device:
as shown in fig. 2, the electronic device 20 may be any camera-equipped electronic device, and the electronic device 20 includes, but is not limited to, a smartphone, a mobile computer, a tablet computer, a Personal Digital Assistant (PDA), and the like. As shown in fig. 2, the electronic device 20 includes, but is not limited to, an image sensor 200, a processor 210, a display 220, a communication unit 260, a storage unit 270, a radio frequency circuit 240, a power supply 250, and the like.
Optionally, the processor 210 may be one or more of the following processors: a Central Processing Unit (CPU), an Image Signal Processor (ISP), a Graphics Processing Unit (GPU), and a Digital Signal Processor (DSP).
The logic control circuit 202 may be provided with a processing device, which is configured to control the pixel array to generate charges and generate corresponding images, and the processing device may be one or more field-programmable gate arrays (FPGAs), Application Specific Integrated Circuits (ASICs), system on chips (socs), Central Processing Units (CPUs), Network Processors (NPs), digital signal processing circuits (DSPs), Micro Controllers (MCUs), Programmable Logic Devices (PLDs), or other integrated chips, or any combination of the above chips or processors.
Specifically, the imaging device can be a three-transistor active pixel (3T-APS), a clamp diode four-transistor active pixel (4T-APS) and a clamp diode five-transistor active pixel (5T-APS), and the imaging device is exemplified as the 4T-APS.
The image sensor 200 may be controlled by the processor 210, and the processor 210 may output an image that the image sensor 200 has sensed and output to the display 230. The display 230 may be a display panel configured in the form of a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED), a Field Emission Display (FED), and the like.
A storage unit 270 for storing code and data, the code for execution by the processor 210. In this embodiment, the storage unit 270 may include a volatile memory and may further include a nonvolatile memory.
A communication unit 260 for establishing a communication channel through which the electronic device connects to a remote server and downloads media data from the remote server. The communication unit 260 may include a wireless local area network (wlan) module, a bluetooth module, a baseband module, and other communication modules, and a Radio Frequency (RF) circuit corresponding to the communication module, and is configured to perform wlan communication, bluetooth communication, infrared communication, and/or cellular communication system communication.
The rf circuit 240 is used for receiving and transmitting signals during information transceiving or communication. For example, after receiving the downlink information of the base station, the downlink information is processed by the processor 210; in addition, the uplink data is transmitted to the base station. Generally, the radio frequency circuit 240 includes well-known circuits for performing these functions, including but not limited to an antenna system, a radio frequency transceiver, one or more amplifiers, a tuner, one or more oscillators, a digital signal processor, a Codec (Codec) chipset, a Subscriber Identity Module (SIM) card, memory, and so forth. In addition, the radio frequency circuit 240 may also communicate with networks and other devices via wireless communication.
A power supply 250 for powering the various components of the electronic device to maintain operation thereof. As a general understanding, the power source 250 may be a built-in battery, such as a common lithium ion battery, a nickel metal hydride battery, or the like, and also include an external power source for directly supplying power to the electronic device, such as an Alternating Current (AC) adapter or the like. In some embodiments of the present invention, the power supply 250 may be more broadly defined and may include, for example, a power management system, a charging system, a power failure detection circuit, a power converter or inverter, a power status indicator (e.g., a light emitting diode), and any other components associated with power generation, management, and distribution of an electronic device.
A specific structure of the pixel array provided in the present application is illustrated below with reference to fig. 3, where fig. 3 is a schematic diagram illustrating a top view structure of an embodiment of the pixel array provided in the present application.
As shown in fig. 3, the pixel array 300 includes a plurality of imaging devices 301, and the pixel array 300 further includes a word line set 310, a bit line set 320, and a source line set, the source line set includes a plurality of source lines, and any source line is perpendicular to the pixel array 300, which is not shown in fig. 3. The word line set 310 includes a plurality of word lines, such as the word line 3101, the word line 3102, the word line 3103 and the word line 310y shown in fig. 3, the number y of the word lines included in the word line set 310 is not limited in this embodiment, as long as y is a positive integer greater than 1; the bit line set 320 includes a plurality of bit lines, such as the bit lines 3201, 3202 and the bit lines 320x shown in fig. 3, the number x of the bit lines included in the bit line set 320 is not limited in this embodiment, as long as x is a positive integer greater than 1. Specifically, any one of the source lines is connected to one imaging device included in the pixel array 300, any one of the word lines included in the word line set 310 is connected to one imaging device included in the pixel array 300, any one of the bit lines in the bit line set 320 is connected to one imaging device included in the pixel array 300, and it can be seen that any one of the imaging devices included in the pixel array 300 is respectively connected to one of the bit lines in the bit line set 302, one of the word lines in the word line set 310, and any one of the source lines in the source line set. Any imaging device is coupled with the logic control circuit through the bit line, the word line and the source line, the logic control circuit can control the imaging device to generate charges through the bit line, the word line and the source line, and a corresponding image is obtained according to the charges generated by the imaging device.
The following description will be made by taking the structure of the conventional imaging device as shown in fig. 4 as an example, where fig. 4a on the left side of fig. 4 and fig. 4b on the right side of fig. 4 are two structures of the imaging device, and as shown in fig. 4a, the longitudinal depth of the N buried layer 401 is L1, in order to increase the full-well capacity of the imaging device, so as to improve the signal-to-noise ratio, the sensitivity, and the like of the imaging device even if the area of the imaging device is reduced, then as shown in fig. 4b, the longitudinal depth of the N buried layer 402 is L2, and the length of L2 is greater than that of L1, it can be seen that, as shown in fig. 4b, the longitudinal depth of the N buried layer is increased with respect to fig. 4a, so that the full-well capacity of the imaging device of fig. 4b is greater than that of the imaging device of fig. 4 a.
However, the buried N layer 402 of fig. 4b has a deeper longitudinal depth, which results in an increased difficulty in transferring photoelectrons in the buried N layer 402 to the floating diffusion node 404, so that the photoelectrons in the buried N layer 402 are less efficiently transferred to the floating diffusion node 404, and image degradation, such as image tailing, is easily caused.
The following structure of the imaging device provided by the application is exemplarily described, and the imaging device provided by the application can effectively guarantee the image quality and relieve the image trailing condition under the condition of improving the full-well capacity of the imaging device. The utility model provides an imaging device includes photosensitive transistor and reading unit, and is specific, photosensitive transistor includes the semiconductor substrate, the semiconductor substrate is provided with first trap, the surface of first trap has set gradually first insulating medium layer and control gate electrode, and is specific, shines at incident light the semiconductor substrate with photoelectric effect can take place in the time on the first trap in order to generate electric charge, first trap is used for shifting the electric charge that generates to reading unit, reading unit is used for according to coming from the electric charge of first trap acquires corresponding image. In addition, in this embodiment, when a voltage is applied to the control gate electrode, the first well becomes a capacitor capable of accommodating charges, and the larger the voltage applied to the control gate electrode is, the larger the capacitance capacity of the first well is, so that the number of charges that can be accommodated by the first well is, which means that the capacitance capacity of the first well is widened by applying a voltage to the control gate electrode, and thus the full well capacity of the phototransistor can meet the requirement of strong light.
For better understanding, the structure of the imaging device is first described in detail with reference to fig. 5 and 6, where fig. 5 is an exemplary diagram of a cross-sectional structure of an embodiment of the imaging device provided in the present application, and fig. 6 is an exemplary diagram of a cross-sectional structure of an embodiment of the imaging device provided in the present application.
Specifically, the following describes a process of the light sensing transistor 500 generating corresponding charges according to incident light:
the photo transistor 500 shown in this embodiment includes a Photodiode (PD) for generating corresponding charges according to incident light, and more specifically, the photodiode shown in this embodiment for sensing light includes a semiconductor substrate 501 and a first well 502.
The semiconductor substrate 501 is first described in detail below:
the semiconductor substrate 501 shown in this embodiment has a first doping type, optionally, the first doping type is n-type impurity doping, specifically, the material of the semiconductor substrate 501 is pure silicon crystal, and a pentavalent element (such as phosphorus) is doped in the silicon crystal, so that the doped phosphorus replaces the position of a silicon atom in the semiconductor substrate 501, thereby forming an n-type semiconductor substrate, the concentration of free electrons of the n-type semiconductor substrate is far greater than that of an impurity semiconductor with a hole concentration, and the more impurities are doped in the semiconductor substrate 501, the higher the concentration of free electrons of the semiconductor substrate 501 is, and the stronger the conductivity is. Optionally, the first doping type is p-type impurity doping, specifically, the semiconductor substrate 501 is made of pure silicon crystal, and a trivalent element (e.g., boron) is doped in the silicon crystal, so that the doped boron replaces the position of a silicon atom in the semiconductor substrate 501, thereby forming a p-type semiconductor substrate, the hole concentration of the p-type semiconductor substrate is greater than that of an impurity semiconductor of free electrons, and the more impurities are doped in the semiconductor substrate 501, the higher the hole concentration of the semiconductor substrate 501 is, and the stronger the conductivity is. In this embodiment, a material of the semiconductor substrate 501 is exemplified as silicon, but not limited thereto, in other examples, the material of the semiconductor substrate 501 may also be germanium, and in this embodiment, the semiconductor substrate 501 is exemplified as a p-type semiconductor substrate.
The first well 502 is illustrated below:
optionally, if the semiconductor substrate 501 is a p-type semiconductor substrate, the charge generated by the photodiode is a photoelectron, and if the semiconductor substrate 501 is an n-type semiconductor substrate, the charge generated by the photodiode is a hole, and this embodiment is exemplified by taking the charge generated by the photodiode as a photoelectron:
as shown in this embodiment, a first ion implantation doping may be performed on a first side of the semiconductor substrate 501 to form a first WELL (WELL)502, and as shown in fig. 6 as an example, that is, as exemplified by a left side of the semiconductor substrate 501 as a first side, a first ion implantation doping may be performed on a left side of the semiconductor substrate 501 to form a first WELL 502;
specifically, if the first ion is a trivalent element (e.g., boron), the first well 502 formed is PWELL; if the first ions are quinvalent elements (such as phosphorus), the formed first well 502 is NWELL, and in this embodiment, to form the photodiode capable of performing sensitization, if the first doping type of the semiconductor substrate 501 is a p-type semiconductor substrate, the first ions are boron ions, and if the first doping type of the semiconductor substrate 501 is an n-type semiconductor substrate, the first ions are phosphorus ions. The present embodiment is exemplified by taking the semiconductor substrate 501 as a p-type substrate.
The following exemplifies the arrangement position of the control gate electrode 504 included in the photo transistor 500 shown in the present embodiment:
specifically, the first well 502, the first insulating dielectric layer 503 and the control gate electrode 504 are sequentially disposed above the semiconductor substrate 501;
the first insulating dielectric layer 503 shown in this embodiment has an insulating function, and the specific material of the first insulating dielectric layer 503 is not limited in this embodiment as long as it is a dielectric with a high dielectric constant, for example, the material of the first insulating dielectric layer 503 is one or a combination of more of silicon oxide, silicon oxynitride (SiON), silicon nitride, and aluminum oxide.
The material of the control gate electrode 504 in this embodiment may be a conductor with a conductive function, such as polysilicon, metal, etc., and the specific material is not limited in this embodiment. The control gate electrode 504 shown in this embodiment is used to be connected to a logic control circuit, and the logic control circuit is used to apply a voltage to the control gate electrode 504, and the specific connection manner between the control gate electrode 504 and the logic control circuit is not limited in this embodiment, for example, the control gate electrode 504 may be connected to the logic control circuit through a word line or a bit line shown in fig. 3, and for example, the control gate electrode 504 may be connected to the logic control circuit through an independent wire.
The function of the control gate electrode 504 provided in the present embodiment is explained below:
specifically, the logic control circuit can apply a voltage in an exposure time period to the control gate electrode 504 so that the first well 502 becomes a capacitance for storing photoelectrons, and the larger the voltage applied to the control gate electrode 504, the larger the capacitance capacity of the first well 502, that is, the magnitude of the voltage applied to the control gate electrode 504 and the number of photoelectrons that can be stored in the first well 502 are in a positive correlation relationship.
While the above description is made for the specific structure of the photo transistor 500 of the imaging device, it should be clear that the description of the structure of the reading unit 600 in this embodiment is an optional example, and for example, the reading unit shown in this embodiment may be a metal-oxide-semiconductor field-effect transistor (MOSFET), a V-groove metal-oxide-semiconductor (VMOS), a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET), or a lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET).
The following describes, with reference to fig. 6, a specific structure of the reading unit 600 shown in the present embodiment:
the reading unit 600 includes a floating diffusion node 603, a charge transfer transistor 604, a reset transistor 605, a source follower transistor 606, and a row selection transistor 607, and the specific arrangement position of the floating diffusion node 603 is first exemplarily described below:
optionally, the floating diffusion node 603 shown in this embodiment is disposed in the second well 602 of the semiconductor substrate 501, and the second well 602 is described below with reference to fig. 6:
in this embodiment, a second ion implantation doping may be performed on the second side of the semiconductor substrate 501 to form the second well 602, and in the case that the first side is the left side of the semiconductor substrate 501 as an example, the second side is the right side of the semiconductor substrate 501 as shown in this example. Taking fig. 6 as an example, a second ion implantation doping is performed on the right side of the semiconductor substrate 501 to form a second well 602.
Specifically, the doping type of the first well 502 and the doping type of the second well 602 shown in this embodiment are different, if the first ion is a trivalent element (e.g., boron), the formed first well 502 is PWELL, the second ion is a pentavalent element (e.g., phosphorus), the formed second well 602 is NWELL, similarly, if the first ion is phosphorus, the formed first well 502 is NWELL, the second ion is boron, the formed second well 502 is PWELL, as the present embodiment takes the first well 502 as NWELL as an example, the second well 602 in this example is PWELL, and because the doping type of the first well 502 is different from the doping type of the second well 602, the photoelectrons generated by the photodiode cannot enter the second well 602, so as to avoid the photoelectrons flowing to the second well 602 to affect the accuracy of the quantity of the photoelectrons read by the reading unit 600.
Continuing with the description of fig. 6, how the floating diffusion node 603 is specifically disposed within the second well 602;
doping the surface of the second well 602 by ion implantation to form the floating diffusion node 603, where the doping type of the floating diffusion node 603 is different from the doping type of the second well 602, that is, the doping type of the floating diffusion node 603 is the first doping type, and for a specific description of the first doping type, please refer to the above description, which is not repeated.
The following illustrates an electrical connection relationship between the components included in the reading unit 600:
the drain of the reset transistor 605 and the drain of the source follower transistor 606 shown in this embodiment are respectively connected to a power supply voltage VDD to be connected to a logic control circuit, the source of the source follower transistor 606 is connected to the drain of the row selection transistor 607, the source of the row selection transistor 607 is connected to the logic control circuit, the source of the reset transistor 605 and the gate of the source follower transistor 606 are connected to the floating diffusion node 603, and the charge transfer transistor 604 is connected to the logic control circuit.
The following is an exemplary description of the specific operation of the reading unit 600:
the logic control circuit shown in this embodiment presets an imaging period, where one imaging period includes a reset time period, an exposure time period, a transfer time period, and a reading time period, which are sequentially arranged in time sequence, and the duration of each time period is not limited in this embodiment, and is specifically described below:
first, the first step is reset, the reset transistor 605 is used to reset the photodiode, specifically, the logic control circuit simultaneously turns on the charge transfer transistor 604 and the reset transistor 605, so that the electrons inside the first well 502 are depleted, at this time, the first well 502 is in an empty well state, and the floating diffusion node 603 is at a high potential, at this time, the potential of the floating diffusion node 603 is read out through the source follower transistor 606 and the row select transistor 607, and is output to the bus as a first signal of Correlated Double Sampling (CDS);
the second step is exposure, specifically, the logic control circuit turns off the charge transfer transistor 604 and the reset transistor 605, the photosensitive transistor 500 generates photoelectrons under the excitation of incident light, and after the exposure time period, the photosensitive transistor 500 accumulates enough photoelectrons;
specifically, in an exposure time period, a depletion layer is formed in the formation of the first well 502, and when external incident light irradiates the depletion layer, a photoelectric effect can occur in the depletion layer, that is, photons of the incident light are absorbed to generate photoelectrons; in this embodiment, the direction of the external incident light irradiating on the pixel array is not limited, and optionally, as shown by the arrow direction of an arrow 608 shown in fig. 6, that is, the light irradiates on the photodiode through the control gate electrode 504 and the first insulating medium layer 503 in sequence; still alternatively, it is continued as indicated by the arrow direction of the arrow 609 shown in fig. 6, i.e. the illumination is directly impinging on the photodiode. The quantity of photoelectrons generated by the photodiode is in positive correlation with the illumination intensity and/or illumination time of the photodiode irradiated by external incident light.
In order to better understand the specific process of transferring photoelectrons, with reference to fig. 6, a channel region 610 is formed between the first well 502 and the second well 602 along the lateral direction of the imaging device, and the first insulating dielectric layer 503 and the charge transfer transistor 604 are sequentially disposed on the surface of the channel region 610 along the direction away from the channel region 610;
wherein a logic control circuit turns on the charge transfer transistor 604 for a transfer period and drops the voltage of the control gate electrode 504 to a reset voltage so that photoelectrons in the first well 502 can be completely transferred into the floating diffusion node 603 through the channel region 610;
it can be seen that, when the charge transfer transistor 604 of the present embodiment is used to transfer the photoelectrons in the first well 502 to the floating diffusion node 603 through the channel region 610, the charge transfer transistor 604 needs to be disposed above the channel region 610 in a direction perpendicular to the imaging device, so that the charge transfer transistor 604 can control the photoelectrons to be completely transferred to the floating diffusion node 603 through the channel region 610 when the charge transfer transistor 604 is turned on by the logic control circuit.
The fourth step is reading, specifically, since photoelectrons are transferred to the floating diffusion node 603, so that the potential of the floating diffusion node 603 is lowered, the floating diffusion node 603 is configured to convert the transferred photoelectrons into corresponding electrical signals, and output optical signals to the logic control circuit sequentially through the source follower transistor 606 and the row select transistor 607, where the optical signals at this time are output to the logic control circuit as the second signal of the CDS, and the logic control circuit performs a difference on the two CDS signals to obtain a corresponding image.
Optionally, in the lateral direction of the imaging device, the cross-sectional area of the first well 502 is greater than the cross-sectional area of the second well 602, so that the photosensitive area of the imaging device shown in this embodiment is effectively increased, and because the cross-sectional area of the first well 502 is greater than the cross-sectional area of the second well 602, the photosensitive sensitivity of the imaging device is increased while the full-well capacitance of the imaging device is not reduced.
The following describes the electrical connection relationship of the pixel array shown in this embodiment with reference to fig. 3 and 6:
all the reading units 600 included in the pixel array 300 shown in this embodiment are interconnected by using a flash NOR, so that the logic control circuit shown in this embodiment can control the bit lines and the word lines perpendicular to each other to perform X-Y address reading on all the imaging devices included in the pixel array 300.
All the imaging devices included in the pixel array 300 shown in this embodiment have a common source, and in the exposure time period, the logic control circuit controls the common source of all the imaging devices included in the pixel array 300 to be grounded, so that the common source reading unit 600 can be effectively prevented from causing interference to the phototransistor 500 in the exposure time period.
All the light sensing transistors included in the pixel array 300 shown in this embodiment are interconnected by using a flash memory NAND, so that the light sensing transistors 500 of each imaging device are independent, and even if one light sensing transistor 500 fails, the normal operation of other light sensing transistors 500 in the pixel array is not affected.
Optionally, as shown in fig. 6, isolation layers 511 are disposed on two sides of the imaging device, and isolation between the imaging device and the surrounding imaging devices in the pixel array is realized through the isolation layers 511, where the isolation layers 511 may be formed by Shallow Trench Isolation (STI), specifically, by forming a shallow trench and filling the trench with an oxide or a nitride to perform isolation, so as to ensure that adjacent imaging devices do not interfere with each other; alternatively, the isolation layer 511 may also be formed according to a local oxidation of silicon (silicon) isolation technology, and is not limited in this embodiment.
How the imaging device provided by the present embodiment effectively reduces the influence of dark current is exemplarily described below with reference to fig. 7:
first, referring to fig. 5 and fig. 6, to describe dark current, in the phototransistor 500, in a state where no light is irradiated, a current flowing between the first well 502 and the first insulating medium layer 503 is dark current, the dark current may interfere with a process of obtaining a corresponding electrical signal by the reading unit 600 according to photoelectrons, and in order to reduce an influence of the dark current on obtaining the electrical signal by the reading unit, as shown in fig. 7, in this embodiment, an insulating medium layer 701 is disposed between the first well 502 and the first insulating medium layer 503.
In this embodiment, specific materials of the isolation dielectric layer 701 are not limited, as long as the isolation dielectric layer 701 can perform a function of isolating the first well 502 from the first insulating dielectric layer 503, for example, the isolation dielectric layer 701 may be a high density of P ion implantation (high density of P ion implantation) dielectric, and the first well 502 and the first insulating dielectric layer 503 may be effectively isolated by the isolation dielectric layer 701, so that interference of a dark current between the first well 502 and the first insulating dielectric layer 503 on the reading unit 600 is effectively reduced.
Another structure of the imaging device is exemplified as follows with reference to fig. 8:
in the phototransistor 500 shown in this example, the first well 502, the isolation dielectric layer 701, the first insulating dielectric layer 503, the floating gate 800, the second insulating dielectric layer 801 and the control gate electrode 504 are sequentially disposed right above the semiconductor substrate 501, and the first well 502, the isolation dielectric layer 701, the first insulating dielectric layer 503 and the control gate electrode 504 are specifically described, please see the above embodiments, which is not limited in this embodiment.
In this example, the material of the second insulating dielectric layer 801 may be the same as or different from the material of the first insulating dielectric layer 503, as long as the second insulating dielectric layer 801 is also a high-k dielectric.
As shown in fig. 8, since the floating gate 800 is located in the accommodating cavity formed between the first insulating medium layer 503 and the second insulating medium layer 801, so that the first insulating medium layer 503 and the second insulating medium layer 801 can effectively isolate the floating gate 800, and photoelectrons are limited in the floating gate 800 to achieve a storage function of photoelectrons, the floating gate 800 shown in this embodiment can be a broadband semiconductor, such as polysilicon, silicon nitride (Si3N4) or other electronic conductors or semiconductors, and it is effectively ensured that the photoelectrons can enter the floating gate 800 and be stored in the floating gate 800 by the floating gate 800 shown in this embodiment.
In order to store photoelectrons generated by the photodiode in the floating gate 800, a window 803 is disposed through the first insulating layer 503 in a direction perpendicular to the imaging device, where the specific number of the windows 803 is not limited in this embodiment, that is, the number of the windows 803 may be one or more, in this embodiment, taking fig. 8 as an example, that is, one imaging device includes one window 803, specifically, the window 803 includes a first opening 8031 and a second opening 8032 which are opposite, the first opening 8031 is located on an end surface of the first insulating layer 503 facing the floating gate 800, the second opening 8032 is located on an end surface of the first insulating layer 503 facing the first well 502, and the first opening 8031 and the second opening 8032 are conducted with each other.
In order to realize that photoelectrons generated by the photodiode can be stored in the floating gate 800 through the window 803, so that a phototransistor can simultaneously store photoelectrons through the first well 502 and the floating gate 800, and for the purpose of realizing that photoelectrons generated by the photodiode can be transmitted to the floating gate 800, the first well 502 shown in this embodiment can be connected with the floating gate 800 through the window 803, and the following description exemplifies a specific connection manner:
The medium of the floating gate 800 extends to the second opening 8032 through the first opening 8031 along the guide of the opening 803, and the floating gate 800 and the first well 502 are connected at the second opening 8032.
Mode 2
The medium of the first well 502 extends to the first opening 8031 along the guide of the open window 803 via the second opening 8032, and the floating gate 800 and the first well 502 are connected at the first opening 8031.
Mode 3
The medium of the floating gate 800 extends into the window 803 along the guide of the window 803 through the first opening 8031, and the medium of the first well 502 extends into the window 803 along the guide of the window 803 through the second opening 8032, so that the floating gate 800 in the window 803 is connected with the first well 502.
With the image sensor that this application provided in terminal application, like in the smart mobile phone, can accomplish below 0.7um with image device, it is visible, the image device that this application shows can also satisfy the demand miniaturized to image device when satisfying full well capacity demand.
How the photoelectrons in the photodiode are transferred to the floating gate 800 is described below with reference to fig. 9:
specifically, the depletion layer 900 is formed in the photodiode in the exposure time period, and for a specific description of the depletion layer 900, please refer to the foregoing embodiments in detail, which is not described in detail in this embodiment.
When external incident light irradiates the depletion layer 900, a photoelectric effect can occur in the depletion layer 900, that is, photons of the external incident light are absorbed to generate photoelectrons 901; for a specific description of the generation of the photoelectrons 901, please refer to the above embodiments in detail, and details are not repeated in this embodiment. Photoelectrons 901 generated in the depletion layer 900 drift in a direction toward the floating gate 800, and enter the floating gate 800 through the window 803 when the photoelectrons 901 move to the interface of the first well 502;
in the transfer period, the logic control circuit turns on the charge transfer transistor 604 in the transfer period, and reduces the voltage of the control gate electrode 504 to a reset voltage, so that the photoelectrons stored in the floating gate 800 can flow to the channel region 610 through the window 803, so that the floating gate 800 completely transfers the photoelectrons to the floating diffusion node 603 through the channel region 610, for the specific description of the transfer period, please refer to the above description, and details are not repeated.
Optionally, as shown in fig. 8, along the lateral direction of the imaging device, a first distance L1 is provided between the first well 502 and the second well 602, a second distance L2 is provided between the first insulating medium layer 503 and the second well 602, and the first distance L1 is smaller than the second distance L2, with the structure shown in this embodiment, because the first distance L1 is smaller than the second distance L2, the success rate and the transfer rate of transferring the photoelectrons stored in the floating gate 800 into the floating diffusion node 603 through the first well 502 are improved, and the occurrence of a situation that the photoelectrons stored in the floating gate 800 cannot be successfully transferred to the floating diffusion node 603 is effectively avoided.
Based on the description of the structure of the imaging device in the above embodiment, the present application also provides a method for supplying power to the imaging device, and the specific description of the imaging device is shown in the above embodiment and is not repeated in this embodiment;
the method specifically comprises the following steps: the logic control circuit adjusts a voltage applied to a control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is in positive correlation with the amount of the charge stored in the imaging device.
Specifically, the amount of the charges that can be stored in the photo transistor with the photo effect is positively correlated with the illumination intensity, that is, the greater the light intensity in the illumination environment where the photo transistor is located, the greater the amount of the charges that the photo transistor needs to store, and the weaker the light intensity in the illumination environment where the photo transistor is located, the smaller the amount of the charges that the photo transistor needs to store, and the logic control circuit may adjust the magnitude of the voltage applied to the control gate electrode according to the intensity of the illumination in the illumination environment where the photo transistor is located, specifically, for example, if the stronger the illumination in the illumination environment where the photo transistor is located, the greater the voltage applied to the control gate electrode is, so that the greater the amount of the charges that the photo transistor can store, and the weaker the illumination in the illumination environment where the photo transistor is located, the smaller the voltage applied to the control gate electrode is, so that the smaller the amount of charges that can be stored by the photosensitive transistor is, the method provided by the embodiment can enable the amount of charges that can be stored by the imaging device to match the requirements in different lighting environments.
For better understanding of the method provided by the present application, a specific implementation of the method for powering an imaging device provided by the present application is exemplarily described below with reference to fig. 10, where as shown in fig. 10, the method shown in the present embodiment specifically includes:
1001, acquiring a target quantity of charges stored in a first exposure time period by a logic control circuit;
for a specific description of the logic control circuit, please refer to the above description, and specifically, no detailed description is given in this embodiment, where the logic control circuit shown in this embodiment first determines a first exposure time period, where the first exposure time period is a time period in which the imaging device has completed exposure, that is, the light sensing transistor completes exposure in the first exposure time period and obtains a target number of charges in the first exposure time period, where a specific description of the light sensing transistor obtaining the target number of charges in the exposure time period is given in the above embodiment, and specifically, no detailed description is given in this embodiment.
In this embodiment, the voltage applied to the control gate electrode by the logic control circuit is dynamically adjusted, and specifically, the logic control circuit is adjusted according to the target amount of the charges stored in the light sensing transistor in the first exposure time period.
More specifically, the target amount of charge that can be stored in the phototransistor in which the photoelectric effect occurs is positively correlated with the intensity of light, that is, the greater the light intensity of the light-sensitive transistor in the light environment in which the light-sensitive transistor is located in the first exposure period, the greater the target amount of the charges stored in the light-sensitive transistor, the weaker the light intensity of the light-sensitive transistor in the light environment in which the light-sensitive transistor is located in the first exposure period, the smaller the target amount of charge stored by the photosensitive transistor, the smaller the logic control circuit determines the illumination condition of the photosensitive transistor in the first exposure time period, namely, the voltage applied to the control gate electrode of the imaging device in the second exposure period can be correspondingly adjusted, the first exposure time period is earlier than the second exposure time period, and the second exposure time period is the next time period required to be subjected to light sensing by the light sensing transistor.
The specific adjustment process may be that, if the logic control circuit determines that the photosensitive transistor is in a strong light environment in the first exposure time period, the logic control circuit may increase the voltage applied to the control gate electrode, so as to increase the capacitance of the first well, so that the first well can accommodate more charges in the second exposure time period, and thus the full well capacity of the photosensitive transistor shown in this embodiment can meet the requirement of strong light;
if the logic control circuit determines that the photosensitive transistor is in a weak illumination environment in the first exposure time period, the logic control circuit can reduce the voltage applied to the control gate electrode, so that the capacitance of the first well is reduced, the capacity of the first well capable of containing charges is matched with the current illumination in the second exposure time period, the power consumption of applying the voltage to the control gate electrode is effectively saved, and the waste of the power consumption is avoided under the condition that the full well capacity of the photosensitive transistor can meet the current illumination environment.
A specific process of the logic control circuit adjusting the magnitude of the voltage applied to the control gate electrode is described below with reference to fig. 11:
the specific execution process of step 1101 shown in this embodiment is shown in step 1001 shown in fig. 10, and the specific execution process is not described in detail in this embodiment.
Specifically, the logic control circuit shown in this embodiment may preset the preset value, and when the target number of charges generated by the imaging device according to the photoelectric effect is greater than or equal to the preset value, the logic control circuit determines that the first exposure time period is photosensitive in the environment of strong light, and when the target number of charges generated by the imaging device according to the photoelectric effect is smaller than the preset value, the logic control circuit determines that the first exposure time period is photosensitive in the environment of weak light.
And 1104, the logic control circuit reduces the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
The method shown in the present embodiment is described below with reference to specific examples:
taking a first exposure time period of 10 milliseconds as an example, ten thousand charges can be generated in the first well 502 when the light sensitive transistor 500 is irradiated by incident light under weak light, and one hundred thousand charges can be generated in the first well 502 when the light sensitive transistor 500 is irradiated by incident light under strong light, and if the capacitance of the first well 502 is fixed, the light sensitive transistor 500 cannot meet the requirement of strong light;
in the embodiment, the logic control circuit determines that the target amount (one hundred thousand charges) stored in the phototransistor 500 is greater than the preset value (sixty thousand charges) in the first exposure period, it can be known that, if the photo transistor 500 is exposed in the environment of strong light, the next exposure period (second exposure period) of the first exposure period is very likely to be the photo transistor 500 in the environment of strong light, the logic control circuit shown in this embodiment may decrease the voltage applied to the control gate electrode of the imaging device during the second exposure period, so as to increase the full well capacity of the first well 502, so that the capacitance of photoelectrons that can be accommodated in the first well 502 is also increased, therefore, the charge depletion region of the first well 502 is widened, so that the full well capacity of the light sensing transistor shown in this embodiment can meet the requirement of strong light.
Another specific process of the logic control circuit adjusting the magnitude of the voltage applied to the control gate electrode is described below with reference to fig. 12:
for details of the specific execution process of step 1201 shown in this embodiment, please refer to step 1001 shown in fig. 10, and the specific execution process is not described in detail in this embodiment.
The preset voltage adjustment list shown in this embodiment includes different charge number ranges and different voltage values, and in order to achieve the purpose that the stronger the illumination irradiating the imaging device is, the larger the capacitance value of the first well is to accommodate more charges, in the preset voltage adjustment list, the larger the charge number range is, the larger the corresponding voltage value is.
And 1204, applying the target voltage to the control gate electrode of the imaging device by the logic control circuit in a second exposure time period.
By adopting the embodiment, the dynamic adjustment of the target voltage applied to the control gate electrode is realized through the preset voltage adjustment list, so that the method disclosed by the embodiment can be matched with more various illumination environments, the matching degree of the imaging device and the illumination environments is improved, and after the target voltage is applied to the control gate electrode by the logic control circuit, the full-well capacity of the imaging device can meet the requirements of the current illumination environments.
With reference to fig. 13, a specific structure of the logic control circuit provided in this embodiment is exemplarily described below, where the logic control circuit shown in this embodiment is used for a processing device that executes corresponding processing and/or steps in any of the above method embodiments, and please refer to the above method embodiments in detail;
specifically, the logic control circuit includes:
the adjusting unit 1301 is configured to adjust a voltage applied to a control gate electrode of the imaging device according to the charge stored in the imaging device, where a magnitude of the voltage applied to the control gate electrode and an amount of the charge stored in the imaging device are in a positive correlation.
Optionally, the logic control circuit further comprises an acquiring unit 1302, configured to acquire a target amount of charges stored in the imaging device in a first exposure time period;
the adjusting unit 1301 is further configured to adjust a voltage applied to the control gate electrode of the imaging device in a second exposure period according to the target number, wherein the magnitude of the voltage applied to the control gate electrode is in positive correlation with the target number, and the first exposure period is earlier than the second exposure period.
Optionally, the adjusting unit 1301 is specifically configured to: and if the target number is greater than or equal to a preset value, increasing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
Optionally, the adjusting unit 1301 is specifically configured to: and if the target number is less than a preset value, reducing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.
Optionally, the adjusting unit 1301 is specifically configured to: acquiring a preset voltage regulation list, wherein the preset voltage regulation list comprises corresponding relations between different charge quantity ranges and different voltage values; determining target voltages corresponding to the target number according to the preset voltage adjusting list; applying the target voltage to a control gate electrode of the imaging device for a second exposure time period.
In a specific application process, the obtaining unit 1302 may be an input/output interface or a transceiver circuit, where the input/output interface may include an input interface and an output interface, and the transceiver circuit may include an input interface circuit and an output interface circuit.
The adjusting unit 1301 may be a processing device, and the functions of the processing device may be partially or completely implemented by software. Alternatively, the functions of the processing means may be partly or wholly implemented by software. At this time, the processing device may include a memory for storing the computer program and a processor for reading and executing the computer program stored in the memory to perform the corresponding processes and/or steps in any one of the method embodiments. Alternatively, the processing means may comprise only a processor. The memory for storing the computer program is located outside the processing device and the processor is connected to the memory by means of circuits/wires to read and execute the computer program stored in the memory. Alternatively, part or all of the functions of the processing device may be implemented by hardware, which is not limited in this embodiment as long as the processing device can execute corresponding processes and/or steps in any of the above method embodiments.
The present application further provides a storage medium, where computer instructions are stored, and when the computer instructions are called by a logic control circuit, the logic control circuit is enabled to execute corresponding processes and/or steps as shown in any one of the above method embodiments.
Embodiments of the present application further provide a computer program product, which includes computer program code, when called by a logic control circuit, causes the logic control circuit to execute the corresponding processes and/or steps as shown in any of the above method embodiments.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (15)
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2019
- 2019-07-31 CN CN201980098625.7A patent/CN114127936A/en active Pending
- 2019-07-31 WO PCT/CN2019/098693 patent/WO2021016939A1/en not_active Ceased
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4994876A (en) * | 1988-08-31 | 1991-02-19 | Mitsubishi Denki Kabushiki Kaisha | Light detecting element and light detecting array |
| JP2012080560A (en) * | 2005-11-14 | 2012-04-19 | Panasonic Corp | Photo detector, control method of photo detector, and detector of space information |
| JP2010278653A (en) * | 2009-05-27 | 2010-12-09 | Fujifilm Corp | Solid-state imaging device, imaging apparatus, and imaging method |
| CN101715041A (en) * | 2009-11-20 | 2010-05-26 | 苏州东微半导体有限公司 | Method for controlling semiconductor photosensitive component |
| US20120002089A1 (en) * | 2010-01-13 | 2012-01-05 | Xinyang Wang | Pixel structure with multiple transfer gates |
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