CN114122147B - Thin film transistor, array substrate and display panel - Google Patents
Thin film transistor, array substrate and display panel Download PDFInfo
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- CN114122147B CN114122147B CN202111415586.4A CN202111415586A CN114122147B CN 114122147 B CN114122147 B CN 114122147B CN 202111415586 A CN202111415586 A CN 202111415586A CN 114122147 B CN114122147 B CN 114122147B
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current
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- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6731—Top-gate only TFTs
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
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Abstract
本公开提供了一种薄膜晶体管、阵列基板和显示面板，薄膜晶体管包括：有源层、栅绝缘层和栅极，有源层包括沟道区和位于所述沟道区两侧的源极区和漏极区；栅绝缘层位于所述有源层的一侧；栅极位于所述栅绝缘层背离所述有源层的一侧，所述栅极包括靠近所述漏极区的第一区域、靠近所述源极区的第二区域和位于所述第一区域和所述第二区域之间的第三区域；其中，所述栅极在相同电平信号下，所述第三区域作用于所述沟道区上的电场强度，大于所述第一区域作用于所述沟道区上的电场强度。本公开提供的薄膜晶体管，能够减少薄膜晶体管的漏电。
The present disclosure provides a thin film transistor, an array substrate and a display panel, wherein the thin film transistor comprises: an active layer, a gate insulating layer and a gate electrode, wherein the active layer comprises a channel region and a source region and a drain region located on both sides of the channel region; the gate insulating layer is located on one side of the active layer; the gate electrode is located on the side of the gate insulating layer away from the active layer, and the gate electrode comprises a first region close to the drain region, a second region close to the source region and a third region located between the first region and the second region; wherein, under the same level signal of the gate electrode, the electric field strength of the third region acting on the channel region is greater than the electric field strength of the first region acting on the channel region. The thin film transistor provided by the present disclosure can reduce the leakage of the thin film transistor.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a thin film transistor, an array substrate and a display panel.
Background
The thin film transistor (Thin Film Transistor, TFT) is a key component for active driving of display devices such as a Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD) and an Organic Light-Emitting Diode (OLED), and plays an important role.
According to the different materials forming the Active layer (Active) structure, the thin film transistor comprises an amorphous silicon thin film transistor (a-Si TFT), an Oxide thin film transistor (Oxide TFT) and a low temperature polysilicon thin film transistor (LTPS TFT), and compared with the amorphous silicon thin film transistor and the Oxide thin film transistor, the low temperature polysilicon thin film transistor has the advantages of high mobility and the like, and is suitable for medium and small display technology of high PPI and multi-system integration (such as GOA).
However, the leakage of the low-temperature polysilicon thin film transistor is much higher than that of amorphous silicon and oxide semiconductor due to the presence of defects such as grain boundaries.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of an embodiment of the present disclosure is to provide a thin film transistor, an array substrate and a display panel, which can reduce leakage of the thin film transistor.
According to an aspect of an embodiment of the present disclosure, there is provided a thin film transistor including:
The active layer comprises a channel region, and a source electrode region and a drain electrode region which are positioned at two sides of the channel region;
A gate insulating layer located at one side of the active layer;
A gate electrode located on a side of the gate insulating layer facing away from the active layer, the gate electrode including a first region adjacent to the drain region, a second region adjacent to the source region, and a third region located between the first region and the second region;
The electric field intensity of the third region acting on the channel region is larger than the electric field intensity of the first region acting on the channel region under the same level signal.
In an exemplary embodiment of the present disclosure, the third region acts on the channel region with an electric field strength greater than that of the second region under the same level signal.
In one exemplary embodiment of the present disclosure, the gate insulating layer is located between the first region of the gate electrode and the active layer to have a thickness greater than a thickness located between the third region of the gate electrode and the active layer.
In one exemplary embodiment of the present disclosure, the gate insulating layer is located between the second region of the gate electrode and the active layer to have a thickness greater than a thickness located between the third region of the gate electrode and the active layer.
In an exemplary embodiment of the present disclosure, further comprising:
The thickness of the buffer layer corresponding to the third region is larger than that of the buffer layer corresponding to the first region, so that the thickness of the gate insulating layer between the first region and the active layer of the gate is larger than that between the third region and the active layer of the gate.
In one exemplary embodiment of the present disclosure, the buffer layer has a thickness corresponding to the third region that is greater than a thickness corresponding to the second region such that the gate insulating layer has a thickness between the second region and the active layer of the gate electrode that is greater than a thickness between the third region and the active layer of the gate electrode.
In an exemplary embodiment of the present disclosure, the gate electrode is formed with a first hollowed-out portion on the first region.
In an exemplary embodiment of the present disclosure, the gate electrode is formed with a second hollowed-out portion on the first region.
In an exemplary embodiment of the present disclosure, the gate electrode is formed with a third hollowed-out portion on the third region.
In an exemplary embodiment of the disclosure, the first hollowed-out portion, the second hollowed-out portion and the third hollowed-out portion are in a strip-shaped hollowed-out structure, and a length extending direction of the strip-shaped hollowed-out structure intersects with a length direction of the channel region.
In an exemplary embodiment of the disclosure, the first hollowed-out portion is communicated with the second hollowed-out portion and the third hollowed-out portion, and the gate forms an interdigital structure.
In an exemplary embodiment of the present disclosure, a width of the first region is 0.001 μm to 50 μm in a direction in which the gate electrode faces the drain region.
In one exemplary embodiment of the present disclosure, the thickness of the gate insulating layer between the first region of the gate electrode and the active layer is greater than the thickness between the third region of the gate electrode and the active layer by1 μm to 50 μm.
In one exemplary embodiment of the present disclosure, the gate insulating layer includes:
a first sub-insulating layer between the active layer and the gate electrode;
the second sub-insulating layer is positioned between the first sub-insulating layer and the grid electrode, and the selective etching ratio of the second sub-insulating layer to the first sub-insulating layer is larger than 10:1.
In one exemplary embodiment of the present disclosure, the material of the gate insulating layer includes at least one of silicon oxide, a high-K material.
According to another aspect of the embodiments of the present disclosure, there is provided an array substrate including the thin film transistor described above.
According to still another aspect of the embodiments of the present disclosure, there is provided a display panel, which includes the above-described array substrate.
The electric field intensity of the third region acting on the channel region is larger than the electric field intensity of the first region acting on the channel region under the same level signal, namely, for example, when the thin film transistor is switched from a high level signal to a low level signal and is in a closed state, the electric field intensity of the first region, which is close to the drain region, of the channel region is relatively smaller, which is equivalent to that of the channel region, a resistor is connected in series with the channel region, an uneven electric field is generated in the channel region, and concentration of the electric field at the drain terminal is restrained, so that electric leakage of the thin film transistor is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:
FIG. 1 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a thin film transistor according to another embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a thin film transistor according to another embodiment of the present disclosure;
fig. 4 is a schematic diagram of a gate hollow portion according to an embodiment of the disclosure;
Fig. 5 is a schematic view of a gate hollow portion according to another embodiment of the disclosure;
fig. 6 is a schematic view of a gate hollow portion according to another embodiment of the disclosure;
fig. 7 is a schematic mask diagram of a gate forming hollowed-out portion according to an embodiment of the disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other components, devices, etc. In other instances, well-known components, device implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," and "at least one" are used to indicate the presence of one or more elements/components/etc., the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc., in addition to the listed elements/components/etc., and the terms "first," "second," etc. are used as labels only, and not as limitations on the number of objects thereof.
Currently, compared with NMOS (N-type metal oxide semiconductor field effect transistor), since carriers operating in PMOS (P-type metal oxide semiconductor field effect transistor) are holes, the effective mobility is lower, and the relative leakage is smaller, which is currently being generally adopted. The leakage mechanism of LTPS (low temperature polysilicon) is mainly carrier generation-recombination (G-R), and the sub-mechanism is mainly two of heat generation mechanism (THE THERMAL generation) and field enhancement (the field-enhanced generation). A common technology for reducing the leakage current is a lightly doped drain LDD (Lightly Doped Drain) technology, but an offset region exists between a channel and a source drain, self alignment cannot be adopted, an LDD region is narrow and is not easy to control, and the reduction of the on current can be brought.
The present disclosure provides a thin film transistor, which mainly aims at a field enhancement mechanism, avoids an electric field concentration phenomenon existing at a drain terminal of a TFT, and includes an active layer 310, a gate insulating layer 321, and a gate electrode 351 as shown in fig. 1 to 3. The active layer 310 includes a channel region and source and drain regions located at both sides of the channel region, a gate insulating layer 321 located at one side of the active layer 310, and a gate electrode 351 located at one side of the gate insulating layer 321 facing away from the active layer 310, the gate electrode 351 including a first region A1 adjacent to the drain region, a second region A2 adjacent to the source region, and a third region A3 located between the first region A1 and the second region A2. Wherein, the electric field intensity of the third region A3 acting on the channel region is greater than the electric field intensity of the first region A1 acting on the channel region under the same level signal of the gate 351.
In the thin film transistor provided by the disclosure, the electric field intensity of the third area A3 acting on the channel area is larger than the electric field intensity of the first area A1 acting on the channel area under the same level signal, namely, for example, when the thin film transistor is switched from a high level signal to a low level signal and is in a closed state, the electric field intensity of the first area A1 of the channel area, which is close to the drain area, is relatively smaller, which is equivalent to that of the channel area, a resistor is connected in series with the channel area, an uneven electric field is generated in the channel area, and concentration of the electric field at the drain end is restrained, so that electric leakage (off-state current) of the thin film transistor is reduced.
In one embodiment of the present disclosure, the third region A3 acts on the channel region with an electric field strength greater than that of the second region A2 under the same level signal. That is, for example, when the thin film transistor is switched from a high level signal to a low level signal and is in an off state, the electric field strength at the second region A2 of the channel region near the drain region is relatively small, which corresponds to the channel region having a resistor connected in series thereto, and an uneven electric field is generated in the channel region, thereby suppressing concentration of the electric field at the source terminal.
In one embodiment of the present disclosure, as shown in fig. 1, the thickness of the gate insulating layer 321 between the first region A1 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, i.e., the distance between the first region A1 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, so that the electric field strength of the gate 351 acting on the channel region from the third region A3 is greater than the electric field strength of the first region A1 acting on the channel region under the same level signal, which is equivalent to that the channel region is serially connected with a resistor, an uneven electric field is generated in the channel region, and concentration of the electric field at the drain terminal is suppressed, thereby reducing leakage of the thin film transistor.
Further, the thickness of the gate insulating layer 321 between the second region A2 of the gate electrode 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate electrode 351 and the active layer 310, i.e. the distance between the second region A2 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, so that the electric field strength of the gate electrode 351 acting on the channel region by the third region A3 is greater than the electric field strength of the second region A2 acting on the channel region under the same level signal, which is equivalent to the fact that the channel region is serially connected with a resistor, an uneven electric field is generated in the channel region, and concentration of the electric field at the source terminal is inhibited. In addition, the gate insulating layer 321 is thicker at the positions corresponding to the first area A1 and the second area A2, which is convenient for forming the gate insulating layer 321 and reduces the process difficulty.
Illustratively, the width of the first region A1 in the direction of the gate 351 toward the drain region is 0.001 μm to 50 μm, e.g., 0.001 μm, 0.01 μm, 0.1 μm, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., which are not specifically recited herein. Of course, the width of the first region A1 may be less than 0.001 μm or more than 50 μm, which is not limited by the present disclosure. The width of the first area A1 is set to be 0.001-50 mu m, on-state current can be balanced under the condition that electric leakage of the thin film transistor is reduced, and the influence on the on-state current is avoided to be too large.
Illustratively, the width of the second region A2 in the direction of the gate 351 toward the drain region may be 0.001 μm to 50 μm, such as 0.001 μm, 0.01 μm, 0.1 μm, 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., which are not specifically recited herein. Of course, the width of the second region A2 may also be less than 0.001 μm or greater than 50 μm, which is not limited by the present disclosure. The width of the second area A2 may be the same as the width of the first area A1.
The thickness of the gate insulating layer 321 between the first region A1 of the gate electrode 351 and the active layer 310 is greater than 1 μm to 50 μm, such as 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., between the third region A3 of the gate electrode 351 and the active layer 310, which are not specifically recited herein. Of course, the thickness of the gate insulating layer 321 between the first region A1 of the gate electrode 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate electrode 351 and the active layer 310, which may be less than 1 μm or greater than 50 μm, without limitation of the present disclosure.
The thickness of the gate insulating layer 321 between the second region A2 of the gate electrode 351 and the active layer 310 is greater than 1 μm to 50 μm, such as 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, etc., between the third region A3 of the gate electrode 351 and the active layer 310, which are not specifically recited herein. Of course, the thickness of the gate insulating layer 321 between the second region A2 of the gate electrode 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate electrode 351 and the active layer 310, which may be less than 1 μm or greater than 50 μm, without limitation of the present disclosure. The gate insulating layer 321 may have the same thickness between the second region A2 and the first region A1 of the gate electrode 351 and the active layer 310.
As shown in fig. 1, the gate insulating layer 321 includes a first sub-insulating layer 3211 and a second sub-insulating layer 3212, that is, the gate insulating layer 321 is of a stacked structure. The first sub-insulating layer 3211 is located between the active layer 310 and the gate 351, the second sub-insulating layer 3212 is located between the first sub-insulating layer 3211 and the gate 351, and a selective etching ratio of the second sub-insulating layer 3212 to the first sub-insulating layer 3211 is greater than 10:1. Such as 10:1, 20:1, 50:1, 100:1, etc. By selectively etching the second sub-insulating layer 3212 and the first sub-insulating layer 3211, the second sub-insulating layer 3212 may be etched to form a recess in the middle of the gate insulating layer 321, so that the thickness of the gate insulating layer 321 between the first region A1 and the second region A2 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310.
The material of the first sub-insulating layer 3211 is silicon oxide, the material of the second sub-insulating layer 3212 is silicon nitride, and the etching selectivity of silicon oxide and silicon nitride is relatively high, which is more favorable for the uniformity of the recess depth of the gate insulating layer 321, i.e. the electrical uniformity is not affected basically. Of course, the gate insulating layer 321 may be a single-layer structure, for example, formed using silicon oxide, silicon nitride, silicon oxynitride, or the like, which is not limited by the present disclosure.
In one embodiment of the present disclosure, as shown in fig. 2, the thin film transistor further includes a buffer layer 200. The buffer layer 200 is located at one side of the active layer 310 away from the gate insulating layer 321, and the thickness of the buffer layer 200 corresponding to the third region A3 is greater than the thickness corresponding to the first region A1, so that the thickness of the gate insulating layer 321 between the first region A1 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, i.e., the distance between the first region A1 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, thereby enabling the electric field strength of the gate 351 acting on the channel region by the third region A3 to be greater than the electric field strength of the first region A1 acting on the channel region under the same level signal, which is equivalent to the series connection of resistors by the channel region, generating uneven electric fields in the channel region, suppressing concentration of the electric fields at the drain terminal, and reducing leakage of the thin film transistor.
Further, the thickness of the buffer layer 200 corresponding to the third region A3 is greater than the thickness corresponding to the second region A2, so that the thickness of the gate insulating layer 321 between the second region A2 of the gate 351 and the active layer 310 is greater than the thickness between the third region A3 of the gate 351 and the active layer 310, i.e. the distance between the second region A2 of the active layer 310 and the channel region is greater than the distance between the third region A3 and the channel region, so that the electric field strength of the third region A3 acting on the channel region is greater than the electric field strength of the second region A2 acting on the channel region under the same level signal, which is equivalent to the fact that the channel region is connected in series with a resistor, an uneven electric field is generated in the channel region, and concentration of the electric field at the source terminal is suppressed. In addition, the positions of the gate insulating layer 321 corresponding to the first area A1 and the second area A2 are thicker, so that the gate insulating layer 321 is formed conveniently, and the process difficulty is reduced.
Wherein, before the active layer 310 is fabricated, the buffer layer 200 is patterned, and a gray tone mask (gray tone mask) may be used to fabricate structures with different heights at the two ends and the middle of the channel (the height difference is within several to several tens micrometers, and within the depth of focus DOF of the optical devices such as ELA and photo). The active layer 310 and the gate insulating layer 321 are sequentially formed. Because the coverage of different film forming techniques is different, the active layer 310 has better profiling property due to the thinner film layer and the CVD deposition of the front film layer a-Si, the pattern of the buffer layer 200 is basically replicated, the gate insulating layer 321 is generally thicker than the active layer 310, and various deposition techniques such as CVD/PVD can be used to planarize the pattern of the buffer layer 200, so that non-uniformity of the gate insulating layer 321 is formed in the channel (only the thickness of the gate insulating layer 321 near the source 330 and the drain 340 is actually required to be different, and the gate insulating layer 321 inside the channel can be uniform).
The fabrication process of the structure adds buffer (buffer layer 200) patterning before the conventional self-aligned LTPS PMOS process. The other flows are the same. Where fabrication of the gate insulator 321 is critical to electrical performance, CVD may be used to deposit silicon oxide (with a good interface to LTPS), and then a high K material such as zirconium oxide, hafnium oxide, etc. may be deposited, such as by sputtering, to provide non-uniform thickness of the gate insulator 321 in the trench.
In one embodiment of the disclosure, as shown in fig. 3, the gate 351 is formed with a first hollowed portion 3511 on the first region A1, and the first hollowed portion 3511 forms a partial voltage by patterning the gate 351 to generate an uneven electric field in a channel, so that the electric field intensity of the third region A3 acting on the channel region is greater than the electric field intensity of the first region A1 acting on the channel region under the same level signal, and the electric field concentration near the drain end is reduced, thereby reducing the leakage of the thin film transistor.
Specifically, as shown in fig. 3 and fig. 4, the first hollow portion 3511 may be a strip-shaped hollow structure, and a length extending direction of the strip-shaped hollow structure intersects with a length direction of the channel region, for example, the length extending direction of the strip-shaped hollow structure is perpendicular to the length direction of the channel region. Of course, the first hollowed-out portion 3511 may be curved, shaped or formed by a plurality of intermittent through holes, which is not limited in the disclosure, and can be a hollowed-out area, so as to achieve the effect of weakening the electric field influence on the channel.
Further, as shown in fig. 3 and 4, the gate 351 has a second hollowed-out portion 3512 formed on the second region A2. An uneven electric field is generated in the channel to form a partial voltage, so that the electric field intensity of the third area A3 acting on the channel area is larger than the electric field intensity of the second area A2 acting on the channel area under the same level signal of the grid 351, and the electric field concentration near the source end is reduced.
Specifically, as shown in fig. 4, the second hollow portion 3512 may be a strip-shaped hollow structure, and the length extending direction of the strip-shaped hollow structure intersects with the length direction of the channel region, for example, the length extending direction of the strip-shaped hollow structure is perpendicular to the length direction of the channel region. Of course, the second hollowed-out portion 3512 may be curved, shaped or formed by a plurality of intermittent through holes, which is not limited in the disclosure, and can be a hollowed-out area, so as to achieve the effect of weakening the electric field influence on the channel. The shapes and sizes of the first hollow portion 3511 and the second hollow portion 3512 may be the same or different.
Further, as shown in fig. 5, the gate 351 has a third hollowed-out portion 3513 formed in the third region A3, that is, a plurality of hollowed-out structures are formed along the length direction of the channel, and the influence of the hollowed-out portions on the electric field of the channel is weakened, which is equivalent to connecting a plurality of resistors in series in the channel, so that the electric field concentration near the drain end is reduced, and thus the leakage of the thin film transistor is reduced.
Specifically, as shown in fig. 5, the third hollow portion 3513 may be a strip-shaped hollow structure, and the length extending direction of the strip-shaped hollow structure intersects with the length direction of the channel region, for example, the length extending direction of the strip-shaped hollow structure is perpendicular to the length direction of the channel region. Of course, the third hollowed-out portion 3513 may be curved, shaped or formed by a plurality of intermittent through holes, which is not limited in the disclosure, and the effect of weakening the electric field influence on the channel can be achieved only in the hollowed-out area. The shapes and sizes of the third hollow portion 3513 and the first hollow portion 3511 and the second hollow portion 3512 may be the same or different.
Specifically, as shown in fig. 5, the first hollow portion 3511, the second hollow portion 3512 and the third hollow portion 3513 are in a strip-shaped hollow structure, and the length extending direction of the strip-shaped hollow structure intersects with the length direction of the channel region, the influence of the multiple hollow portions on the electric field of the channel region is weakened, which is equivalent to connecting a plurality of resistors in series in the channel region, so that the concentration of the electric field at the drain end can be reduced, and the leakage of the thin film transistor is reduced.
Specifically, as shown in fig. 6, the first hollowed-out portion 3511 is communicated with the second hollowed-out portion 3512 and the third hollowed-out portion 3513, the gate 351 forms an interdigital structure, the influence of the multiple hollowed-out portions on the electric field of the channel region becomes weak, which is equivalent to connecting a plurality of resistors in series in the channel region, so that concentration of the electric field at the drain end can be reduced, and leakage of the thin film transistor is reduced.
Of course, the first hollow portion 3511, the second hollow portion 3512 and the third hollow portion 3513 may be partially connected to form an insertion structure with the gate 351, and partially form an unconnected spaced-strip hollow structure. The present disclosure is not limited thereto, and any technical solution that can change the size and shape of the hollowed-out portion to achieve the effect of weakening the electric field influence on the channel belongs to the protection scope of the present disclosure.
Since the gate 351 needs to be hollowed out by adding a mask for SD doping, the other process is the same as that of the conventional PMOS. For the newly added SD doping mask, in order to reduce the influence of manufacturing bias (such as photo capping and precision overlay, etc.) on TFT uniformity, as shown in fig. 7, a photoresist 800 may be used to cover only the hollowed-out area of the gate 351, and the gate 351 is still used in other parts to block SD doping ions as hrad mask (hard mask), which is partially self-aligned.
In one embodiment of the present disclosure, as shown in fig. 1 to 3, the thin film transistor further includes a second gate insulating layer 322 (gate insulating layer 321 as a first gate insulating layer), an interlayer insulating layer 360, a source electrode 330, and a drain electrode 340. The second gate insulating layer 321 is disposed on a side of the first gate insulating layer 321 facing away from the gate electrode 351, the interlayer insulating layer 360 is disposed on a side of the gate electrode 351 facing away from the active layer 310, and is formed with through holes exposing the source region and the drain region, respectively, the source electrode 330 and the drain electrode 340 are disposed on a side of the interlayer insulating layer 360 facing away from the active layer 310, and the source electrode 330 and the drain electrode 340 are in contact with the source region and the drain region, respectively.
The embodiment of the disclosure also provides an array substrate, which comprises the thin film transistor. The thin film transistor array substrate is a main component in the current LCD device and AMOLED device, and is directly related to the development direction of the high performance flat panel display device, and is used for providing a driving circuit for the display, and generally, a plurality of gate scan lines and a plurality of data lines are provided, which define a plurality of pixel units, each pixel unit is provided with a thin film transistor and a pixel electrode, the gate of the thin film transistor is connected with the corresponding gate scan line, and when the voltage on the gate scan line reaches the on voltage, the source and the drain of the thin film transistor are turned on, so that the data voltage on the data line is input to the pixel electrode, and further, the display of the corresponding pixel region is controlled. The structure of the thin film transistor on the array substrate generally further includes a gate electrode, a gate insulating layer, an active layer, a source/drain electrode, and an insulating protection layer stacked on the substrate. The beneficial effects of the present invention are described in detail in the thin film transistor, and are not described herein.
As shown in fig. 1, the array substrate further includes a substrate 100, a flat layer (PLN) 400 disposed on the substrate 100 and covering the interlayer insulating layer 360 and away from the source 330 and the drain 340, a pixel electrode 500 disposed on a side of the flat layer 400 facing away from the second gate insulating layer 322 and contacting the source 330 or the drain 340 through a via hole, a metal layer (GI 2) 352 disposed between the second gate insulating layer 321 and the interlayer insulating layer 360, a Pixel Defining Layer (PDL) 600 disposed on a side of the flat layer 400 facing away from the interlayer insulating layer 360, and a spacer (PS) 700 disposed on a side of the pixel defining layer 600 facing away from the flat layer 400.
The embodiment of the disclosure also provides a display panel, which comprises the array substrate. The display panel can be used for any product or component with a display function, such as a vehicle-mounted display device, a liquid crystal panel, an advertising screen, electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame or a navigator. The beneficial effects of the present invention are described in detail in the thin film transistor, and are not described herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (15)
1. A thin film transistor, comprising:
The active layer comprises a channel region, and a source electrode region and a drain electrode region which are positioned at two sides of the channel region;
A gate insulating layer located at one side of the active layer;
the grid electrode is positioned on one side of the grid insulating layer, which is away from the active layer, and comprises a first area, a second area and a third area, wherein the first area is close to the drain area, the second area is close to the source area, and the third area is positioned between the first area and the second area;
The thin film transistor further comprises a buffer layer, wherein the buffer layer is positioned on one side, away from the gate insulating layer, of the active layer, the thickness, corresponding to the third area, of the buffer layer is larger than the thickness, corresponding to the first area, of the buffer layer, so that the thickness, between the first area and the active layer, of the gate insulating layer is larger than the thickness, between the third area and the active layer, of the gate electrode, or a first hollowed-out portion is formed on the first area of the gate electrode.
2. The thin film transistor according to claim 1, wherein an electric field strength of the third region acting on the channel region is larger than an electric field strength of the second region acting on the channel region under the same level signal.
3. The thin film transistor according to claim 1, wherein a thickness of the gate insulating layer between the first region of the gate electrode and the active layer is greater than a thickness between the third region of the gate electrode and the active layer.
4. The thin film transistor according to claim 3, wherein a thickness of the gate insulating layer between the second region of the gate electrode and the active layer is greater than a thickness between the third region of the gate electrode and the active layer.
5. The thin film transistor according to claim 1, wherein a thickness of the buffer layer corresponding to the third region is greater than a thickness corresponding to the second region such that a thickness of the gate insulating layer between the second region and the active layer of the gate electrode is greater than a thickness between the third region and the active layer of the gate electrode.
6. The thin film transistor according to claim 1, wherein the gate electrode is formed with a second hollowed-out portion on the second region.
7. The thin film transistor according to claim 6, wherein the gate electrode is formed with a third hollowed-out portion on the third region.
8. The thin film transistor according to claim 7, wherein the first hollow portion, the second hollow portion and the third hollow portion are in a strip-shaped hollow structure, and a length extending direction of the strip-shaped hollow structure intersects with a length direction of the channel region.
9. The thin film transistor according to claim 7, wherein the first hollowed-out portion is communicated with the second hollowed-out portion and the third hollowed-out portion, and the gate forms an interdigital structure.
10. The thin film transistor according to claim 1, wherein a width of the first region is 0.001 μm to 50 μm in a direction in which the gate electrode faces the drain region.
11. A thin film transistor according to claim 1 or 3, wherein the thickness of the gate insulating layer between the first region of the gate electrode and the active layer is greater than 1 μm to 50 μm between the third region of the gate electrode and the active layer.
12. The thin film transistor according to claim 3, wherein the gate insulating layer comprises:
a first sub-insulating layer between the active layer and the gate electrode;
the second sub-insulating layer is positioned between the first sub-insulating layer and the grid electrode, and the selective etching ratio of the second sub-insulating layer to the first sub-insulating layer is larger than 10:1.
13. The thin film transistor according to claim 1, wherein the material of the gate insulating layer includes at least one of silicon oxide and a high-K material.
14. An array substrate comprising the thin film transistor of any one of claims 1-13.
15. A display panel comprising the array substrate of claim 14.
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| KR100477102B1 (en) * | 2001-12-19 | 2005-03-17 | 삼성에스디아이 주식회사 | CMOS TFT with Multiple Gates and Fabrication Method thereof using MILC |
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