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CN114141622A - Preparation method of GAAFET gallium nitride field effect transistor - Google Patents

Preparation method of GAAFET gallium nitride field effect transistor Download PDF

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Publication number
CN114141622A
CN114141622A CN202111421947.6A CN202111421947A CN114141622A CN 114141622 A CN114141622 A CN 114141622A CN 202111421947 A CN202111421947 A CN 202111421947A CN 114141622 A CN114141622 A CN 114141622A
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China
Prior art keywords
nanowire
growing
oxide layer
gallium nitride
annealing
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CN202111421947.6A
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刘新科
高麟飞
黎晓华
宋利军
黄双武
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Shenzhen University
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Shenzhen University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The embodiment of the invention discloses a preparation method of a GAAFET gallium nitride field effect crystal, which comprises the following steps: etching the surface of a single crystal substrate to form a nanowire with a vertically protruding middle part, growing oxide layers on the etched surfaces at two sides of the nanowire to enable the oxide layers to be flush with the nanowire in height, evaporating metal films, and forming a grid electrode through stripping and annealing; growing an oxide layer on the surface of the grid electrode, then epitaxially growing a Si epitaxial layer, etching the Si epitaxial layer to the height of the grid electrode oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowire to form a first nanowire, growing an oxide layer, evaporating a metal film, stripping and annealing; growing an oxide layer and epitaxially growing a Si epitaxial layer, growing strip-shaped gallium nitride in a direction vertical to the nanowire to form a second nanowire, growing an oxide layer, evaporating a metal film, stripping and annealing; and selectively etching the epitaxial growth Si epitaxial layer, evaporating metal at two ends of the first nanowire and the second nanowire, and stripping and annealing to form the ohmic electrode.

Description

Preparation method of GAAFET gallium nitride field effect transistor
Technical Field
The embodiment of the invention relates to the technical field of transistors, in particular to a preparation method of a GAAFET gallium nitride field effect transistor.
Background
Wide bandgap gallium nitride (GaN) has become a well-known semiconductor in power and rf device applications due to its superior material properties in recent years. A FinFET vertical nanowire complementary metal-semiconductor Field Effect Transistor (FinFET for short) having a three-dimensional structure has excellent gate controllability, and has attracted great attention and been widely used.
The existing FinFET has the outstanding characteristics that: (1) the control circuit on the two sides of the grid is turned on and off. (2) In the FinFET structure, the gate is designed into a fork-shaped 3D structure similar to a fin, so that the leakage current can be greatly improved and reduced, and the gate length of the transistor can be greatly shortened. (3) The method has the advantages of low power consumption and small area. But the prior FinFET also has obvious defects: due to the narrow width of the channel, the current density is extremely high, the efficiency is low, and high heat is generated, but the GaN channel can not effectively dissipate heat, so that the temperature in the channel is increased, and the performance of the device is poor.
Disclosure of Invention
To solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a GAAFET gallium nitride field effect transistor, including:
etching the surface of a single crystal substrate to form a nanowire with a vertically protruding middle part, growing oxide layers on the etched surfaces of two sides of the nanowire to enable the oxide layers to be lower than the height of the nanowire, evaporating metal films on the surface of the nanowire, and forming a grid electrode through stripping and annealing;
growing an oxide layer on the surface of the grid, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, etching the Si epitaxial layer to the height of the grid oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowire to form a first nanowire, growing the oxide layer on the first nanowire, evaporating a metal film on the surface of the oxide layer, stripping and annealing;
growing an oxide layer on the surface of the first drain electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowire to form a second nanowire, growing the oxide layer on the second nanowire, evaporating a metal film on the surface of the oxide layer, stripping and annealing;
and selectively etching the oxide layer on the surface of the first drain electrode to epitaxially grow a Si epitaxial layer so as to fix the first nanowire and the second nanowire by the device, evaporating metal at two ends of the first nanowire and the second nanowire, and stripping and annealing to form the ohmic electrode.
Further, a barrier layer is formed by using a photolithography process, and Cl is performed on the surface of the single crystal substrate2/SiCl4And (3) performing dry etching and TMAH solution wet etching to form a middle vertically protruding nanowire, wherein the width of the nanowire is 10-100 nm.
Further, the thickness of the Si epitaxial layer is 10-20 nm.
Furthermore, when the grid electrode or the drain electrode is prepared, the metal evaporation film is Cr, and the thickness is 150-300 nm.
Furthermore, when the ohmic electrode is prepared, the metal film is evaporated and at least one of Ti, Al, Ni or Au, and the thickness is 20-80 nm.
Further, the single crystal substrate is an N + type gallium nitride single crystal or a silicon carbide single crystal with a thickness of 200-500 μm, wherein the N + type gallium nitride substrate uses silicon as a dopant with a doping concentration of 5 × 1018cm-3。
Further, the oxide layer is aluminum oxide or silicon oxide.
Furthermore, the thickness of the long-strip gallium nitride is 0.2-0.4 μm when the first nanowire and the second nanowire are prepared.
Further, gallium nitride uses magnesium as a dopant with a doping concentration of 2 × 1018cm-3-3×1018cm-3。
Further, comprising: when preparing the electrode, annealing is carried out under the conditions of nitrogen environment and 650 ℃.
The embodiment of the invention has the beneficial effects that: the invention provides a GAAFET vertical gallium nitride field effect transistor, which adds a nanowire on the structure of the prior FinFET, and has the advantages that: (1) because the existing vertical GAAFET device integrates two MOS tubes vertically on a substrate when being conducted, compared with the traditional phase inverter, the vertical GAAFET device has the advantages of lower static power consumption, lower time delay, reduced device volume and improved integration level. (2) The upper surface, the lower surface and the side surfaces of the nanowires are all provided with channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated ring gate and the comprehensive performance of the multi-layer nanowires are further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without paying creative efforts.
Fig. 1 is a schematic flow chart of a fabrication method of a GAAFET vertical gan field effect transistor according to an embodiment of the present invention;
fig. 2 is a schematic perspective view of a GAAFET vertical gan field effect transistor according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, fig. 1 is a method for manufacturing a GAAFET vertical gan field effect transistor according to an embodiment of the present invention, as shown in fig. 1, the method specifically includes the following steps:
etching the surface of a single crystal substrate to form a nanowire with a vertically protruding middle part, growing oxide layers on the etched surfaces of two sides of the nanowire to enable the oxide layers to be lower than the height of the nanowire, evaporating metal films on the surface of the nanowire, and forming a grid electrode through stripping and annealing;
the single crystal substrate is N + type gallium nitride single crystal or silicon carbide single crystal with a thickness of 200-500 μm, preferably 300 μm, wherein the N + type gallium nitride substrate uses silicon as dopant with a doping concentration of 5 × 1018cm-3. During etching, a photoetching process is used for manufacturing a barrier layer, and Cl is carried out on the original structure2/SiCl4And (3) performing dry etching and TMAH solution wet etching to form the middle vertically-protruded nanowire with the width of 10-100 nm, preferably 50 nm.
Growing an oxide layer, e.g., Al, on a device surface using Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) methods2O3. A metal film such as Cr is deposited on the nanowires by thermal evaporation, magnetron sputtering or electron beam evaporation to a thickness of 100-300nm, preferably 200nm, to form a gate.
Growing an oxide layer on the surface of the grid, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, etching the Si epitaxial layer to the height of the grid oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowires to form first nanowires, growing an oxide layer on the first nanowires, evaporating a metal film on the surface of the oxide layer, stripping and annealing;
growing aluminum oxide (Al) on the surface of the device by using Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) method2O3) Then epitaxially growing an Si (15nm) epitaxial layer on the substrate, the Si layer being grown at a temperature below 500 deg.C, and growing the Si layer by etching the Si layer to the height of the alumina layer, using Hydride Vapor Phase Epitaxy (HVPE) orGrowing a layer of long-strip gallium nitride (GaN) by using a Molecular Beam Epitaxy (MBE) or metal organic compound chemical vapor deposition (MOCVD) method, growing alumina on the surface of a device by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) method, wrapping the nanowire of the freshly grown layer, evaporating a metal film (such as Cr (200nm)) by using methods such as thermal evaporation, magnetron sputtering or electron beam evaporation, forming an electrode by using a stripping process, and annealing at 650 ℃ under an N2 environment to form the first drain electrode.
Growing an oxide layer on the surface of the first drain electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowire to form a second nanowire, growing the oxide layer on the second nanowire, evaporating a metal film on the surface of the oxide layer, stripping and annealing;
please refer to step two for the detailed method of step three. The thickness of the first nanowire and the second nanowire is 0.2-0.4 μm. Gallium nitride using magnesium as a dopant at a doping concentration of 2X 1018cm-3-3×1018cm-3。
And step four, selectively etching the oxide layer on the surface of the first drain electrode to epitaxially grow a Si epitaxial layer so that the first nanowire and the second nanowire are fixed by the device, evaporating metal at two ends of the first nanowire and the second nanowire, and stripping and annealing to form the ohmic electrode.
The silicon layer was selectively etched using a tetramethylammonium hydroxide (TMAH) aqueous solution, and after the selective etching, a Forming Gas Anneal (FGA) was performed on the nanowire to remove dislocations. In order to achieve good selective etching between GaN/Si, the solution temperature was chosen around 60 ℃ with the help of ultra-large ultrasonic agitation.
After the photolithography process, a metal film, such as Ti (25nm), Al (75nm), Ni (25nm) or Au (75nm), is evaporated at both ends of the nanowire by thermal evaporation, magnetron sputtering, electron beam evaporation, or the like, and the nanowire is annealed at 650 ℃ in an N2 atmosphere after forming electrodes by a lift-off process.
Optionally, in the above embodiment, the oxide layer is aluminum oxide or silicon oxide. Fig. 2 is a schematic perspective view of a GAAFET vertical gan field effect transistor according to an embodiment of the present invention, where, as shown in fig. 2, 1 is a single crystal substrate, 2 is an oxide layer, 3 is a vertically protruding nanowire, 4 is a second nanowire, 5 is a first nanowire, and 6 is an ohmic electrode.
The foregoing is only a partial embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A preparation method of GAAFET gallium nitride field effect crystal is characterized by comprising the following steps:
etching the surface of a single crystal substrate to form a nanowire with a vertically protruding middle part, growing oxide layers on the etched surfaces at two sides of the nanowire to enable the oxide layers to be lower than the height of the nanowire, evaporating metal films on the surface of the nanowire, and forming a grid electrode through stripping and annealing;
growing an oxide layer on the surface of the grid, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, etching the Si epitaxial layer to the height of the grid oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowire to form a first nanowire, growing the oxide layer on the first nanowire, evaporating a metal film on the surface of the oxide layer, stripping and annealing;
growing an oxide layer on the surface of the first drain electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, growing long-strip gallium nitride in a direction vertical to the nanowire to form a second nanowire, growing the oxide layer on the second nanowire, evaporating a metal film on the surface of the oxide layer, stripping and annealing;
and selectively etching the oxide layer on the surface of the first drain electrode to epitaxially grow a Si epitaxial layer so as to fix the first nanowire and the second nanowire by the device, evaporating metal at two ends of the first nanowire and the second nanowire, and stripping and annealing to form the ohmic electrode.
2. The method of claim 1, wherein the barrier layer is formed on a single crystal substrate using a photolithography processSurface treatment with Cl2/SiCl4And (3) performing dry etching and TMAH solution wet etching to form the nanowire with the middle part vertically protruding, wherein the width of the nanowire is 10-100 nm.
3. The production method according to claim 1, wherein the thickness of the Si epitaxial layer is 10 to 20 nm.
4. The method according to claim 1, wherein the deposited metal film is Cr and has a thickness of 150 to 300nm when the gate electrode or the drain electrode is formed.
5. The method according to claim 1, wherein the evaporation metal film is at least one of Ti, Al, Ni, or Au, and has a thickness of 20-80 nm.
6. The method according to claim 1, wherein the single crystal substrate is an N + -type gallium nitride single crystal or a silicon carbide single crystal having a thickness of 200-500 μm, and wherein the N + -type gallium nitride substrate uses silicon as a dopant having a doping concentration of 5 x 1018cm-3。
7. The method according to claim 1, wherein the oxide layer is alumina or silica.
8. The method of claim 1, wherein the growth of the elongated gan is performed to a thickness of 0.2-0.4 μm when the first and second nanowires are formed.
9. The method according to claim 8, wherein the gallium nitride is doped with magnesium at a concentration of 2 x 1018cm-3-3×1018cm-3。
10. The method of claim 1, comprising: when preparing the electrode, annealing is carried out under the conditions of nitrogen environment and 650 ℃.
CN202111421947.6A 2021-11-26 2021-11-26 Preparation method of GAAFET gallium nitride field effect transistor Pending CN114141622A (en)

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