CN114157278B

CN114157278B - Power MOS drive circuit

Info

Publication number: CN114157278B
Application number: CN202010937236.3A
Authority: CN
Inventors: 雷晗; 夏云凯
Original assignee: Xi'an Dingxin Microelectronic Co ltd
Current assignee: Xi'an Dingxin Microelectronic Co ltd
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2025-09-23
Anticipated expiration: 2040-09-08
Also published as: CN114157278A

Abstract

The present application discloses a power MOS driver circuit, comprising: a second NMOS transistor NM2, a third NMOS transistor NM3, and a clamping circuit 3 arranged between the second NMOS transistor NM2 and the third NMOS transistor NM3, wherein the source of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3 are connected to generate an output control square wave; and the clamping circuit 3 is used to limit the high level of the output control square wave.

Description

Power MOS driving circuit

Technical Field

The application relates to the technical field of power MOS driving circuits, in particular to a power MOS driving circuit.

Background

The power MOS is used as an electronic switching device, has the characteristics of high switching speed, low conduction loss, low manufacturing cost and the like, and is widely applied to various power fields such as battery chargers, power adapters and the like. Almost all power supply products are not separated from the electronic switch, and as the electronic switch which is most widely used at present, how to match the device characteristics of the power MOS in use becomes an important research direction, and how to guarantee the reliability of the power MOS is very important.

The breakdown voltage of the gate and the source of most current power MOS switches does not exceed 30V. The device characteristics of the power MOS switch are that the higher the gate-source voltage is, the smaller the on-resistance is, the smaller the loss as a switch is, and the higher the system efficiency is, whereas the lower the gate-source voltage is, the larger the on-resistance is, the larger the loss as a switch is, and the lower the system efficiency is. In practical application, proper driving voltage (generally controlled to 10V-20V) is needed to be selected, so that the conduction loss is ensured to be too small, and breakdown damage caused by too high gate source voltage of the power MOS is avoided.

The conventional power MOS switch driving circuit adopts the structure shown in fig. 2, and this structure solves the problem of outputting square wave high level when the power VCC is too high by using a zener diode. However, when VCC is too low, the output square wave will be one NM2 transistor threshold VTH lower than VCC, that is, VCC-VTH, due to the effect of the on threshold VTH of the NMOS transistor NM 2.

In view of this problem, referring to fig. 3, the driving circuit of the conventional power MOS switch is optimized, and a PMOS transistor PM2 is connected in parallel to a second NMOS transistor NM2 transistor. When the power supply VCC is too low, the second NMOS transistor NM2 is turned on while PM2 is turned on, clamping the output square wave high level at VCC. This solution solves the problem of the drive voltage when VCC is too low, but the current capability of the PMOS transistor is about 1/3 of that of the NMOS transistor, so that the PMOS needs to occupy more area and cost more on the premise of providing the same drive capability.

Aiming at the technical problems that the cost of the power MOS driving circuit becomes high and the power consumption is large in the prior art in the scheme that the power MOS switch cannot be started when the voltage of the power VCC in the power MOS driving circuit is too low, no effective solution is proposed at present.

Disclosure of Invention

The disclosure provides a power MOS driving circuit, which solves the technical problems that in the prior art, in the scheme of solving the problem that a power MOS switch cannot be started when the voltage of a power supply VCC in the power MOS driving circuit is too low, the cost of the power MOS driving circuit is high and the power consumption is large.

According to one aspect of the application, a power MOS driving circuit is provided, which comprises a second NMOS transistor, a third NMOS transistor and a clamping circuit arranged between the second NMOS transistor and the third NMOS transistor, wherein the source electrode of the second NMOS transistor is connected with the drain electrode of the third NMOS transistor and is used for generating an output control square wave, and the clamping circuit is used for limiting the high level of the output control square wave.

Therefore, according to the power MOS driving circuit provided by the embodiment of the application, the output control square wave for starting the switch is output through the connection of the source electrode of the second NMOS transistor and the drain electrode of the third NMOS transistor. Wherein the second NMOS transistor is used for outputting a high level of the control square wave, and the third NMOS transistor is used for outputting a low level of the control square wave. And the application also sets a clamping circuit at the connection of the second NMOS transistor and the third NMOS transistor, wherein the clamping circuit is used for controlling the high level of the output control square wave. The technical effect of preventing the grid breakdown of the power MOS switch caused by the high level of the output control square wave is achieved. The application realizes the high-low voltage clamping setting of the power MOS grid drive, prevents the grid breakdown of the power MOS switch by high voltage and prevents the overlarge conduction loss of the power MOS switch caused by overlarge drive by low voltage through a simple circuit structure, thereby saving the area and the cost of the circuit and providing the technical effect of enough driving capability. And further, the technical problems that the cost of the power MOS driving circuit is high and the power consumption is large in the existing scheme for solving the problem that the power MOS switch cannot be started when the voltage of the power VCC in the power MOS driving circuit is too low in the prior art are solved.

The above, as well as additional objectives, advantages, and features of the present application will become apparent to those skilled in the art from the following detailed description of a specific embodiment of the present application when read in conjunction with the accompanying drawings.

Drawings

Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. It will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the accompanying drawings:

fig. 1 is a schematic diagram of a power MOS drive circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a drive circuit of a conventional power MOS switch as described in the background art, and

Fig. 3 is an optimized schematic diagram of a driving circuit of a conventional power MOS switch described in the background art.

Detailed Description

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order that those skilled in the art will better understand the present disclosure, a technical solution in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure, shall fall within the scope of the present disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in connection with other embodiments. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

Fig. 1 is a schematic diagram of a power MOS drive circuit according to an embodiment of the present application. Referring to fig. 1, the power MOS driving circuit includes a second NMOS transistor NM2, a third NMOS transistor NM3, and a clamp circuit 3 disposed between the second NMOS transistor NM2 and the third NMOS transistor NM3, wherein a source of the second NMOS transistor NM2 and a drain of the third NMOS transistor NM3 are connected for generating an output control square wave, and the clamp circuit 3 is for limiting a high level of the output control square wave.

As described in the background art, the driving circuit of the conventional power MOS switch adopts the structure shown in fig. 2, which solves the problem of outputting the square wave high level when the power VCC is excessively high by using the zener diode. However, when VCC is too low, the output square wave will be one NM2 transistor threshold VTH lower than VCC, that is, VCC-VTH, due to the effect of the on threshold VTH of the NMOS transistor NM 2. In view of this problem, referring to fig. 3, the driving circuit of the conventional power MOS switch is optimized, and a PMOS transistor PM2 is connected in parallel to a second NMOS transistor NM2 transistor. When the power supply VCC is too low, the second NMOS transistor NM2 is turned on while PM2 is turned on, clamping the output square wave high level at VCC. This solution solves the problem of the drive voltage when VCC is too low, but the current capability of the PMOS transistor is about 1/3 of that of the NMOS transistor, so that the PMOS needs to occupy more area and cost more on the premise of providing the same drive capability.

In view of this, the present embodiment provides a power MOS drive circuit that outputs an output control square wave for activating a power MOS switch through connection of the source of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM 3. Wherein the second NMOS transistor NM2 is used to output a high level of the control square wave, and the third NMOS transistor NM3 is used to output a low level of the control square wave. In addition, the invention also sets a clamping circuit 3 in the middle of the second NMOS transistor NM2 and the third NMOS transistor NM3, when the high level of the output control square wave is too high, the clamping circuit 3 is used for controlling the high level of the output control square wave not to exceed the highest voltage of the power MOS switch. The technical effect of preventing the grid breakdown of the power MOS switch caused by the high level of the output control square wave is achieved. The invention realizes the high-low voltage clamping setting of the power MOS switch grid drive, prevents the grid breakdown of the power MOS switch by high voltage and prevents the overlarge conduction loss of the power MOS switch caused by overlarge drive by low voltage through a simple circuit structure, thereby saving the area and the cost of the circuit and providing the technical effect of enough driving capability. And further, the technical problems that the cost of the power MOS driving circuit is high and the power consumption is large in the existing scheme for solving the problem that the power MOS switch cannot be started when the voltage of the power VCC in the power MOS driving circuit is too low in the prior art are solved.

Optionally, the power MOS driving circuit further comprises a level shift circuit 2, wherein the second NMOS transistor NM2 and the third NMOS transistor NM3 are arranged in the level shift circuit 2, and the level shift circuit 2 is used for converting the received input control square wave into an output control square wave capable of driving the power MOS switch.

Specifically, referring to FIG. 1, the power MOS drive circuit further includes a level shift circuit 2, wherein the second NMOS transistor NM2 and the third NMOS transistor NM3 are both disposed in the level shift circuit 2, and the level shift circuit 2 is configured to convert an input control square wave into an output control square wave that can drive the power MOS switch. Thereby achieving the technical effect that the power MOS switch can be controlled to be turned on and off through the level conversion circuit 2.

Optionally, the power MOS driving circuit further comprises a power supply circuit 1, wherein the power supply circuit 1 is connected with the level conversion circuit 2 and is used for providing input voltage for the level conversion circuit 2.

Specifically, referring to fig. 1, a power supply circuit 1 is connected to a level shift circuit 2, and a control power supply is supplied to the level shift circuit, that is, an input voltage is supplied to the level shift circuit 2 through the power supply circuit 1.

Optionally, the power MOS driving circuit further comprises a power supply VCC, and the power supply circuit 1 comprises a current limiting circuit I _DC, a first Zener diode ZD1, a first capacitor C1, a first NPN transistor NPN1 and a second NPN transistor NPN2, wherein the positive end of the current limiting circuit I _DC is connected with the power supply VCC, the negative end of the current limiting circuit I _DC is connected with the cathode of the first Zener diode ZD1, the cathode of the first Zener diode ZD1 is connected with the base of the first NPN transistor NPN1 and the base of the second NPN transistor NPN2, the anode of the first Zener diode ZD1 is connected with the ground, the first capacitor C1 is connected with the first Zener diode ZD1 in parallel, the base of the first NPN transistor NPN1 is connected with the cathode of the first NPN transistor NPN1, the emitter of the first NPN transistor NPN1 is connected with the level conversion circuit 2, and the base of the second NPN transistor 2 is connected with the power supply VCC, and the collector of the second NPN transistor NPN2 is connected with the level conversion circuit VCC 2.

Specifically, referring to fig. 1, a power supply VCC supplies power to a power MOS drive circuit. And the positive end of the current limiting circuit I _DC is connected with the power supply VCC, the negative end of the current limiting circuit I _DC is connected with the cathode of the first Zener diode ZD1, and the anode of the first Zener diode ZD1 is grounded. The first capacitor C1 is connected in parallel to two ends of the first zener diode ZD1. The bases of the first NPN transistor NPN1 and the second NPN transistor NPN2 are connected with the cathode of the first zener diode ZD1, and the collectors of the first NPN transistor NPN1 and the second NPN transistor NPN2 are connected with the power supply VCC. The emitter of the first NPN transistor NPN1 supplies power to the level shifter circuit 2. The emitter of the second NPN transistor NPN2 is connected to the source of the PMOS transistor PM. The emitter of the first NPN transistor NPN1 supplies power to the level shift circuit 2, and the emitter of the second NPN transistor NPN2 supplies power to the PMOS transistor PM. And the first zener diode ZD1 provides base clamping (a measure in which clamping is to limit the potential to a prescribed potential) for the first NPN transistor NPN1 and the second NPN transistor NPN2, with the purpose of preventing the voltages supplied from the emitters of the first NPN transistor NPN1 and the second NPN transistor NPN2 to the level shift circuit 2 from becoming excessively high. The purpose of the current limiting circuit I _DC is to provide base drive currents for the first NPN transistor NPN1 and the second NPN transistor NPN2 without damaging the first zener diode ZD1.

Further, the first zener diode ZD1 functions only when the voltage of the power supply VCC reaches the start-up voltage set in advance for the first zener diode ZD 1. Thereby clamping the voltages of the emitters of the first NPN transistor NPN1 and the second NPN transistor NPN 2.

Further, emitter voltage=v _ZD1-0.7V(V_ZD1 of the first NPN transistor NPN1 and the second NPN transistor NPN2 is a breakdown voltage of the first zener diode ZD1, and 0.7V is a voltage drop between the base and the emitter of NPN), as power supply voltages of the level shifter circuit 2 and the clamp circuit 3.

Alternatively, the level shifter circuit 2 includes a level shifter 21, wherein the level shifter 21 is configured to receive an input control square wave and an input voltage of an emitter of the first NPN transistor NPN1, convert the input control square wave into a high-low level that matches the input voltage, and the level shifter 21 includes a first input terminal 211, a second input terminal 212, a first output terminal Q1, and a second output terminal Q2, wherein the first input terminal 211 of the level shifter 21 is connected to the emitter of the first NPN transistor NPN1, is configured to receive the input voltage, and the second input terminal 212 of the level shifter 21 is configured to receive the input control square wave, and the first output terminal Q1 and the second output terminal Q2 of the level shifter 21 are configured to output the converted level signal.

Specifically, referring to fig. 1, the second input terminal 212 of the level shifter 21 is connected to the input control square wave, the first output Q1 of the level shifter 21 is connected to the gates of the PMOS transistor PM and the first NMOS transistor NM1, and the second output Q2 of the level shifter 21 is connected to the gate of the third NMOS transistor NM 3. So that the received input control square wave can be converted into a responsive output voltage by the level shifter 21 in the level shifter circuit 2.

Further, in the case where the input voltage is 10V and the high and low levels of the input control square wave are respectively ground and 5V, the level shifter 21 shifts the high and low levels of the input control square wave to ground and 10V. I.e. the high level of the input control square wave is converted into the voltage of the emitter of the first NPN transistor NPN 1.

Optionally, the level shift circuit 2 further comprises a PMOS transistor PM, a first NMOS transistor NM1, a second NMOS transistor NM2 and a third NMOS transistor NM3, wherein the drain of the PMOS transistor PM is connected with the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2, the source of the PMOS transistor PM is connected with the emitter of the second NPN transistor NPN2, the gate of the PMOS transistor PM is connected with the first output terminal Q1 of the level shifter 21 and the gate of the first NMOS transistor NM1, the gate of the first NMOS transistor NM1 is connected with the first output terminal Q1 of the level shifter 21, the drain of the first NMOS transistor NM1 is connected with the drain of the PMOS transistor PM and the gate of the second NMOS transistor NM2, and the source of the first NMOS transistor NM1 is connected with ground, the gate of the second NMOS transistor NM2 is connected with the drain of the PMOS transistor PM and the drain of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2 is connected with the source of the NMOS transistor VCC 21 and the drain of the third NMOS transistor NM2 is connected with the drain of the third NMOS transistor NM 3.

The drain of the PMOS transistor PM is connected with the drain of the first NMOS transistor NM1, the grid of the second NMOS transistor NM2, the source of the first NMOS transistor NM1 is grounded, the drain of the second NMOS transistor NM2 is connected with a power supply VCC, and the source of the second NMOS transistor NM2 is connected with the drain of the third NMOS transistor NM3 to generate an output control square wave. The source of the third NMOS transistor NM3 is grounded. So that by means of the above-mentioned elements a control square wave for activating the MOS switch can be generated.

Further, when the voltages of the first output terminal Q1 and the second output terminal Q2 are high, the third NMOS transistor NM3 is turned on, the first NMOS transistor NM1 is also turned on, and the PMOS transistor PM is turned off, so that the output is low at this time. While the second capacitor C2 is charged to V _ZD1 -0.7V.

When the voltage at the first output terminal Q1 and the second output terminal Q2 is low, the third NMOS transistor NM3 is turned off, the first NMOS transistor NM1 is also turned off, the PMOS transistor PM is turned on, at this time, the gate voltage of the second NMOS transistor NM2 is equal to V _ZD1 -0.7V, so the second NMOS transistor NM2 is turned on, since the voltage at the second capacitor C2 is always present, the gate voltage=vout+v _C2＝Vout+V_ZD1 -0.7v of the second NMOS transistor NM2 is increased with the increase of the output voltage, the gate voltage of the second NMOS transistor NM2 is always higher than the output voltage V _ZD1 -0.7V (this voltage is several V higher than the threshold Vth of the NMOS transistor, so when the power supply is very low, the output high level of the second NMOS transistor NM2 is equal to the power supply VCC, but not-Vth. When the power supply VCC is high, the gate voltage=vout+v _C2＝Vout+V_ZD1-0.7V>V_ZD2 of the second NMOS transistor NM2 is discharged through the zener diode V _C2＝Vout+V_ZD1-0.7V>V_ZD2, so the output voltage of the second NMOS transistor NM2 is equal to V3525.

Further, for example, vth=3.0v (fixed), if V _ZD1＝V_ZD2 =15.0v is selected, then when vcc=30v, then when Q1 and Q2 are low, the gate voltage of the second NMOS transistor NM2 is 15V (equal to V _ZD2), and the output is equal to 12.0V. Vcc=10v, then the voltages of the first output terminal Q1 and the second output terminal Q2 are low, since the second capacitor C2 is charged to 9.3V (10V-0.7V) when the third NMOS transistor NM3 and the first NMOS transistor NM1 are turned on. Then after the first NMOS transistor NM1 and the third NMOS transistor NM3 are turned off, the PMOS transistor PM is turned on, the gate of the second NMOS transistor NM2 is equal to 9.3V, the second NMOS transistor NM2 is turned on, the output starts to rise, since the second capacitor C2 is not discharged, the voltage of 9.3V on the second capacitor C2 is not changed, when the output rises, the voltage on the upper end of the second capacitor C2 (i.e., the end connected to the second NPN transistor NPN 2) also rises (vout+9.3v), when Vout rises to 5.7V, the voltage on the upper end of the C2 reaches 15V, when the output continues to rise, the second zener diode ZD2 breaks down, and the voltage on the upper end of the second capacitor C2 is clamped at 15V. (this period PM is conductive and the voltage on the upper side of the second capacitor C2 is equal to the voltage on the NM2 gate). When the output continues to rise, the gate voltage of the second NMOS transistor NM2 has not changed. The output at this point is at most equal to vcc=10v.

When breakdown occurs in the first zener diode ZD1, the base voltages of the first NPN transistor NPN1 and the second NPN transistor NPN2 are set, and the power supply voltage for driving the level shifter circuit 2 is also set. When the second zener diode ZD2 breaks down, it is used to set the highest voltage of the output control square wave, i.e. V _ZD2 -Vth. The breakdown voltage of the first zener diode ZD1 is V _ZD1 and the breakdown voltage of the second zener diode ZD2 is V _ZD2. Wherein V _ZD1 -0.7V must be less than or equal to V _ZD2, so as to prevent the direct conduction of NPN2 and ZD2 channels from generating electric leakage. V _ZD2-V_ZD1 must also be less than the breakdown voltage BV _EBO of the emitter E and base B of the second NPN transistor NPN2 to prevent damage to the second NPN transistor NPN 2. I.e., -0.7v < v _ZD2-V_ZD1 < BV _EBO of NPN 2.

Optionally, the clamping circuit 3 comprises a second capacitor C2 and a second zener diode ZD2, wherein a first end of the second capacitor C2 is connected to an emitter of the second NPN transistor NPN2, and a second end of the second capacitor C2 is connected to a source of the second NMOS transistor NM2, and a cathode of the second zener diode ZD2 is connected to an emitter of the second NPN transistor NPN2, and an anode of the second zener diode ZD2 is connected to ground.

Specifically, referring to fig. 1, one end of the second capacitor C2 is connected to the emitter of the second NPN transistor NPN2, and the other end of the second capacitor C2 is connected to the output. The cathode of the second zener diode ZD2 is connected to the emitter of the second NPN transistor NPN2, and the anode of the second zener diode ZD2 is grounded. The second zener diode ZD2 clamps the highest level of the output control square wave when the voltage of the power supply VCC is higher, so as to achieve the purpose of protecting the gate of the power MOS switch when the voltage of the power supply VCC is too high. The second capacitor C2 has the function of clamping the highest level bit of the output control square wave to be the power VCC when the power VCC is low, so as to prevent the power MOS driving voltage from being too low, the conduction loss from becoming large, and the system efficiency from being reduced.

Thus, according to the power MOS driving circuit provided by the embodiment of the application, the output control square wave for starting the switch is output through the connection of the source electrode of the second NMOS transistor NM2 and the drain electrode of the third NMOS transistor NM 3. Wherein the second NMOS transistor NM2 is used to output a high level of the control square wave, and the third NMOS transistor NM3 is used to output a low level of the control square wave. And the present application is also provided with a clamp circuit 3 at the junction of the second NMOS transistor NM2 and the third NMOS transistor NM3, wherein the clamp circuit 3 is for controlling the high level of the output control square wave. The technical effect of preventing the grid breakdown of the power MOS switch caused by the high level of the output control square wave is achieved. The application realizes the high-low voltage clamping setting of the power MOS grid drive, prevents the grid breakdown of the power MOS switch by high voltage and prevents the overlarge conduction loss of the power MOS switch caused by overlarge drive by low voltage through a simple circuit structure, thereby saving the area and the cost of the circuit and providing the technical effect of enough driving capability. And further, the technical problems that the cost of the power MOS driving circuit is high and the power consumption is large in the existing scheme for solving the problem that the power MOS switch cannot be started when the voltage of the power VCC in the power MOS driving circuit is too low in the prior art are solved.

In addition, the PMOS is P-CHANNEL METAL oxide semiconductor FET, a P-channel metal oxide semiconductor field effect transistor;

NMOS N-CHANNEL METAL oxide semiconductor FET, N channel metal oxide semiconductor field effect transistor.

NPN, negative Positive Negative transistor, NPN transistor.

Further, a driving circuit of the present invention applied to a switching power supply power MOS includes a power supply circuit 1 (power supply generation circuit), a level shift circuit 2 (driving level shift circuit), and a clamp circuit 3 (power supply VCC high-low voltage clamp circuit), as shown in fig. 1. Referring to fig. 1, it includes only a current limiting circuit I _DC, a first zener diode ZD1, a first capacitor C1, first NPN transistor NPN1 and second NPN transistor NPN2, a level shifter 21, a PMOS transistor PM, a second NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a second capacitor C2, and a second zener diode ZD2.

The current limiting circuit I _DC is characterized in that the positive end of the current limiting circuit I _DC is connected with a power supply VCC, the negative end of the current limiting circuit I _DC is connected with the cathode of a first Zener diode ZD1, the anode of the first Zener diode ZD1 is grounded, a first capacitor C1 is connected in parallel with two ends of the first Zener diode ZD1, bases of the first NPN transistor NPN1 and the second NPN transistor NPN2 are both connected with the cathode of the first Zener diode ZD1, collectors of the first NPN transistor NPN1 and the second NPN transistor NPN2 are both connected with the power supply VCC, an emitter of the first NPN transistor NPN1 is provided with a power supply by a level converter, an emitter of the second NPN transistor NPN2 is connected with a source of a PMOS transistor PM, a second input end 212 of the level converter 21 is connected with an input control square wave, a first output end Q1 of the level converter 21 is connected with a grid of the PMOS transistor PM and a grid of the first NMOS transistor NM1, a second output end Q2 of the level converter 21 is connected with a grid of a third NMOS transistor NM3, a drain of the PMOS transistor PM is connected with a drain of the first NMOS transistor 1, a drain of the second NPN2 is connected with a grid of the second NMOS transistor NPN2, a drain of the second NPN2 is connected with a Zener 2, an emitter of the second NPN2 is connected with a drain of the second NPN2, and a drain of the second NPN2 is connected with a drain of the second NPN2 is grounded, and another drain of the second NPN2 is connected with a drain of the NMOS 2N 2.

The current limiting circuit I _DC is used for providing base driving currents for the first NPN transistor NPN1 and the second NPN transistor NPN2 without damaging the first zener diode ZD1, the first zener diode ZD1 is used for providing base clamping for the first NPN transistor NPN1 and the second NPN transistor NPN2, the purpose of the current limiting circuit I _DC is to prevent the voltages provided by the emitters of the first NPN transistor NPN1 and the second NPN transistor NPN2 from being too high, the emitter of the first NPN transistor NPN1 is used for providing a power supply for a level conversion circuit, the emitter of the second NPN transistor NPN2 is used for providing a power supply for a PMOS transistor PM, the second zener diode ZD2 is used for clamping the highest level of an output control square wave when the power VCC is high, the highest level of the output control square wave is used for achieving the purpose of protecting the power MOS grid when the VCC is low, the power MOS driving voltage is prevented from being too low, the conduction loss is large, and the system efficiency is reduced.

The driving circuit applied to the switching power supply power MOS reduces the number of devices in the circuit through a simple circuit structure, simplifies the design, reduces static power consumption and dynamic power consumption, reduces the effective area of an integrated circuit chip and reduces the generation cost. Meanwhile, on the basis, the high level of the output square wave is clamped when the VCC power supply is too high, the grid electrode of the power MOS is prevented from being damaged, the high level of the output square wave can be clamped to VCC when the VCC power supply is too low, enough driving capability is provided for the power MOS, the conduction loss is reduced, and the system efficiency is improved.

The embodiment of the invention simplifies the design and reduces the cost. Meanwhile, the power MOS driving circuit applied to the switching power supply can meet the driving requirement of most power supplies on the power MOS switch.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Spatially relative terms, such as "above," "upper" and "upper surface," "above" and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the description of the present disclosure, it should be understood that the azimuth terms such as "front, rear, upper, lower, left, right", "transverse, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, and are merely for convenience of describing the present disclosure and simplifying the description, and the azimuth terms do not indicate and imply that the apparatus or element to be referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present disclosure, and the azimuth terms "inside and outside" refer to inside and outside with respect to the outline of each component itself.

The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A power MOS drive circuit is characterized by comprising a second NMOS transistor (NM 2), a third NMOS transistor (NM 3), and a clamp circuit (3) arranged between the second NMOS transistor (NM 2) and the third NMOS transistor (NM 3), wherein

The source of the second NMOS transistor (NM 2) is connected with the drain of the third NMOS transistor (NM 3) for generating an output control square wave, and

The clamping circuit (3) is used for limiting the high level of the output control square wave, and also comprises a power supply (VCC) for providing voltage for the power MOS driving circuit, and the power supply circuit (1) comprises a current limiting circuit (IDC), a first Zener diode (ZD 1), a first capacitor (C1), a first NPN transistor (NPN 1) and a second NPN transistor (NPN 2), wherein

-The positive terminal of the current limiting circuit (IDC) is connected to the power supply (VCC) and the negative terminal of the current limiting circuit (IDC) is connected to the cathode of the first zener diode (ZD 1);

-the cathode of the first zener diode (ZD 1) is connected to the base of the first NPN transistor (NPN 1) and the base of the second NPN transistor (NPN 2), and the anode of the first zener diode (ZD 1) is connected to ground;

the first capacitor (C1) is connected in parallel with the first zener diode (ZD 1);

the base of the first NPN transistor (NPN 1) is connected with the cathode of the first Zener diode (ZD 1), the collector of the first NPN transistor (NPN 1) is connected with the power supply (VCC), and the emitter of the first NPN transistor (NPN 1) is connected with the level conversion circuit (2), and

The base of the second NPN transistor (NPN 2) is connected with the cathode of the first Zener diode (ZD 1), the collector of the second NPN transistor (NPN 2) is connected with the power supply (VCC), and the emitter of the second NPN transistor (NPN 2) is connected with the level conversion circuit (2);

The level shifter circuit (2) comprises a level shifter (21), wherein the level shifter (21) is used for receiving an input control square wave and an input voltage of an emitter of the first NPN transistor (NPN 1), converting the input control square wave into a high level and a low level matched with the input voltage, and the level shifter (21) comprises a first input end (211), a second input end (212), a first output end (Q1) and a second output end (Q2), wherein

A first input (211) of the level shifter (21) is connected to an emitter of the first NPN transistor (NPN 1) for receiving the input voltage and a second input (212) of the level shifter (21) is for receiving the input control square wave, and

-A first output (Q1) and a second output (Q2) of the level shifter (21) are arranged to output a shifted level signal;

the level shift circuit (2) further comprises a PMOS transistor (PM) and a first NMOS transistor (NM 1), wherein

The drain of the PMOS transistor (PM) is connected with the drain of the first NMOS transistor (NM 1) and the gate of the second NMOS transistor (NM 2), the source of the PMOS transistor (PM) is connected with the emitter of the second NPN transistor (NPN 2), and the gate of the PMOS transistor (PM) is connected with the first output end (Q1) of the level converter (21) and the gate of the first NMOS transistor (NM 1);

-the gate of the first NMOS transistor (NM 1) is connected to the first output (Q1) of the level shifter (21), the drain of the first NMOS transistor (NM 1) is connected to the drain of the PMOS transistor (PM) and to the gate of the second NMOS transistor (NM 2), and the source of the first NMOS transistor (NM 1) is connected to ground;

The gate of the second NMOS transistor (NM 2) is connected to the drain of the PMOS transistor (PM) and the drain of the first NMOS transistor (NM 1), the drain of the second NMOS transistor (NM 2) is connected to the power source (VCC), and the source of the second NMOS transistor (NM 2) is connected to the drain of the third NMOS transistor (NM 3), and

-The gate of the third NMOS transistor (NM 3) is connected to the second output (Q2) of the level shifter (21), the drain of the third NMOS transistor (NM 3) is connected to the source of the second NMOS transistor (NM 2), and the source of the third NMOS transistor (NM 3) is connected to ground;

the clamping circuit (3) comprises a second capacitor (C2) and a second zener diode (ZD 2), wherein

A first end of the second capacitor (C2) is connected with an emitter of the second NPN transistor (NPN 2), and a second end of the second capacitor (C2) is connected with a source of the second NMOS transistor (NM 2), and

-The cathode of the second zener diode (ZD 2) is connected to the emitter of the second NPN transistor (NPN 2), and-the anode of the second zener diode (ZD 2) is connected to ground.

2. The power MOS drive circuit according to claim 1, further comprising a level shift circuit (2), wherein the second NMOS transistor (NM 2) and the third NMOS transistor (NM 3) are provided in the level shift circuit (2), and the level shift circuit (2) is configured to convert a received input control square wave into an output control square wave that can drive a power MOS switch.

3. The power MOS drive circuit according to claim 2, further comprising a power supply circuit (1), the power supply circuit (1) being connected to the level shift circuit (2) for providing an input voltage to the level shift circuit (2).