CN114171390A - Tunneling efficiency adjustable semi-floating gate transistor and preparation method thereof - Google Patents
Tunneling efficiency adjustable semi-floating gate transistor and preparation method thereof Download PDFInfo
- Publication number
- CN114171390A CN114171390A CN202111477722.2A CN202111477722A CN114171390A CN 114171390 A CN114171390 A CN 114171390A CN 202111477722 A CN202111477722 A CN 202111477722A CN 114171390 A CN114171390 A CN 114171390A
- Authority
- CN
- China
- Prior art keywords
- well region
- semi
- floating gate
- region
- control gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
Landscapes
- Non-Volatile Memory (AREA)
Abstract
本发明公开一种隧穿效率可调的半浮栅晶体管及其制备方法。该隧穿效率可调的半浮栅晶体管制备方法包括以下步骤：形成P阱区,进行第一次轻掺杂N型离子注入形成N阱区，以形成半浮栅晶体管的沟道杂质分布，N阱区位于P阱区上方；刻蚀形成U形槽，使U型槽贯穿N阱区；形成第一栅氧化层，在N阱区表面形成窗口，形成半浮栅，使其在窗口处与N阱区相接触；之后进行边缘刻蚀，使邻接窗口一侧的部分N阱区的表面露出，进行第二次重掺杂N型离子注入，在N阱区中形成N+掺杂区，以调控隧穿晶体管的隧穿效率；形成控制栅介质，使其覆盖半浮栅并延伸覆盖部分N+掺杂区，接着形成控制栅，使其覆盖控制栅介质；在控制栅两侧形成源区和漏区。
The invention discloses a semi-floating gate transistor with adjustable tunneling efficiency and a preparation method thereof. The method for preparing a semi-floating gate transistor with adjustable tunneling efficiency includes the following steps: forming a P well region, performing a first lightly doped N-type ion implantation to form an N well region, so as to form the channel impurity distribution of the semi-floating gate transistor, The N-well region is located above the P-well region; a U-shaped groove is formed by etching, so that the U-shaped groove runs through the N-well region; a first gate oxide layer is formed, a window is formed on the surface of the N-well region, and a semi-floating gate is formed so that it is at the window Contact with the N-well region; then perform edge etching to expose the surface of part of the N-well region adjacent to the window side, perform the second heavily doped N-type ion implantation, and form an N + doped region in the N-well region , to regulate the tunneling efficiency of the tunneling transistor; form a control gate dielectric to cover the semi-floating gate and extend to cover part of the N + doped region, and then form a control gate to cover the control gate dielectric; form on both sides of the control gate source and drain regions.
Description
Technical Field
The invention belongs to the technical field of semiconductor memories, and particularly relates to a semi-floating gate transistor with adjustable tunneling efficiency and a preparation method thereof.
Background
As device sizes become smaller, DRAM devices are currently facing more and more problems, such as DRAM devices requiring a 64ms refresh, and therefore the capacitance of the capacitor must be maintained above a certain value to ensure a sufficiently long charge retention time. However, as the feature size of integrated circuits is reduced, the fabrication of large capacitors has become more difficult and has made more than 30% of the fabrication cost. The semi-floating gate transistor is used as a novel storage device, is different from a common DRAM device with a 1T1C structure, and comprises a floating gate transistor and an embedded tunneling transistor (TFET), wherein the programming of carriers is completed by band-to-band tunneling of the carriers when the tunneling transistor is started, and the erasing of charges is completed by positive bias of a PN junction formed by the semi-floating gate and an N well region. It can be seen from the working principle that the doping concentration of the N-well region affects the tunneling efficiency of the tunneling transistor and further affects the programming efficiency and the read current of the semi-floating gate transistor.
On the other hand, the doping concentration of the N well region also depends on the impurity distribution and concentration of the channel of the semi-floating gate transistor, and affects the threshold voltage of the semi-floating gate device. Therefore, how to obtain proper TFET tunneling efficiency and threshold voltage of the semi-floating gate transistor through an appropriate nwell ion implantation process is the key to achieving good device performance.
Disclosure of Invention
The invention discloses a preparation method of a semi-floating gate transistor with adjustable tunneling efficiency, which comprises the following steps: forming a P well region in a device manufacturing region of a substrate, and then carrying out first light doping N-type ion implantation to form an N well region so as to form channel impurity distribution of a semi-floating gate transistor, wherein the N well region is positioned above the P well region; etching to form a U-shaped groove, and enabling the U-shaped groove to penetrate through the N well region; depositing a first gate oxide layer, then etching, forming a window on the surface of the N well region, and then forming a semi-floating gate to cover the first gate oxide layer, completely fill the U-shaped groove and be in contact with the N well region at the window; then proceed withEtching the edge to expose the surface of the N-well region adjacent to one side of the window, performing secondary heavy doping N-type ion implantation to form N-well region+The doping area is used for regulating and controlling the tunneling efficiency of the tunneling transistor; forming a control gate dielectric covering the semi-floating gate and extending over a portion of the N+Doping area, then forming control gate to cover the control gate medium; and forming a source region and a drain region on two sides of the control gate.
In the preparation method of the semi-floating gate transistor with adjustable tunneling efficiency, preferably, the semi-floating gate is P-type polycrystalline silicon, and the control gate is N-type polycrystalline silicon.
In the preparation method of the semi-floating gate transistor with adjustable tunneling efficiency, preferably, the dosage range of the first lightly doped N-type ion implantation is 8e12cm-2～8e13cm-2(ii) a The dose range of the second heavily doped N-type ion implantation is 1e14cm-2～5e14cm-2。
The invention also discloses a semi-floating gate transistor with adjustable tunneling efficiency, which comprises: a substrate having a P well region, an N well region disposed above the P well region, and a U-shaped groove penetrating the N well region and having an N region formed on one side thereof+A doped region; the first gate oxide layer is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region, and is provided with a window on one side; the semi-floating gate covers the first gate oxide layer, completely fills the U-shaped groove, and is contacted with the N well region at the window; a control gate dielectric covering the semi-floating gate and extending to cover a portion of the N+A doped region; a control gate overlying the control gate dielectric; a source region and a drain region respectively formed at both sides of the control gate, the N well region and the N+In the doped region.
In the tunneling efficiency-adjustable semi-floating gate transistor, preferably, the semi-floating gate is P-type polycrystalline silicon, and the control gate is N-type polycrystalline silicon.
In the tunneling efficiency-adjustable semi-floating gate transistor, preferably, the semi-floating gate is P-type polycrystalline silicon, and the control gate is N-type polycrystalline silicon.
In the half-floating gate transistor with adjustable tunneling efficiency of the present invention, preferably, the control gate dielectric includes a silicon oxide layer and a silicon nitride layer.
The invention balances the threshold voltage of the semi-floating gate transistor and the tunneling efficiency of the tunneling transistor in the process flow through two times of N well region ion implantation, and optimizes the performance of the device.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a semi-floating gate transistor with adjustable tunneling efficiency.
Fig. 2 to 9 are schematic structural diagrams of the steps of the preparation method of the semi-floating gate transistor with adjustable tunneling efficiency.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
Fig. 1 is a flow chart of a method for manufacturing a semi-floating gate transistor with adjustable tunneling efficiency. As shown in fig. 1, the method comprises the following steps:
step S1, depositing a hard mask 200 on the pad oxide layer and the nitride layer in the device fabrication region of the substrate, performing P-type ion implantation and related annealing to form a P-well 100, and performing a first dose within 8e12cm-2～8e13cm-2The N-well region 102 is formed by implantation of N-type ions with a lighter doping concentration and annealing, and the resulting structure is shown in fig. 2. The N well region ion implantation with lighter doping concentration is mainly used for forming channel impurity distribution of the semi-floating gate transistor.
Step S2, a U-shaped trench is formed by etching, so that the U-shaped trench penetrates through the N-well region 102, and then the hard mask layer 104 is removed, so that the structure is as shown in fig. 3.
Step S3, depositing a first gate oxide layer 103, and then performing etching to form a semi-floating gate window on the surface of the nwell region 102, where the resulting structure is shown in fig. 4. Next, a first polysilicon layer 104 of P-type with a certain thickness is deposited as a semi-floating gate and is subjected to Chemical Mechanical Polishing (CMP) so as to cover the first gate oxide layer 103 and completely fill the U-shaped trench, and is in contact with the nwell region 102 at the window, and the resulting structure is shown in fig. 5.
Step S4, a silicon nitride mask is deposited and edge etching is performed to remove a portion of the first polysilicon layer 104 and a portion of the first gate oxide layer 103 adjacent to one side of the semi-floating gate window, so that a portion of the surface of the nwell region 102 is exposed, and the resulting structure is as shown in fig. 6. Depositing a sacrificial oxide layer, and performing a second dose within 1e14cm-2～5e14cm-2By implanting N-type ions with higher doping concentration and annealing, N is formed in N well region 102+ Doping region 105, and removing the sacrificial oxide layer to obtain the structureShown at 7. And the second time of N well region ion implantation with heavier doping concentration is mainly used for regulating and controlling the tunneling efficiency of the tunneling transistor. The problem that the threshold voltage of the semi-floating gate transistor and the tunneling efficiency of the tunneling transistor are difficult to compromise is balanced in the process flow through two times of N well region ion implantation, so that the performance of the device is optimized in the process flow.
Step S5, depositing a silicon oxide layer 106 and a silicon nitride layer 107 with a certain thickness to form a control gate dielectric covering the first polysilicon layer 104 and extending to cover a portion of the N+A doped region 105. A second polysilicon layer 108 is then deposited overlying the control gate dielectric. Edge etching is performed to expose the substrate surface on both sides of the control gate, and the resulting structure is shown in fig. 8.
In step S6, spacers 109 are formed on both sides of the control gate. Then, N-type ion implantation is performed to form a source region 110 and a drain region 111, and N-type doping is formed on the second polysilicon layer 108 to be used as a control gate, so that the preparation of the semi-floating gate transistor with adjustable tunneling efficiency is completed, and the obtained structure is shown in fig. 9. Of course, the present invention is not limited to this, and the source region, the drain region, and the control gate may be formed by epitaxy or the like.
As shown in fig. 9, the half-floating gate transistor with adjustable tunneling efficiency includes: a substrate formed with a P well region 100, an N well region 102 and a U-shaped groove, wherein the N well region 102 is located above the P well region 100, the U-shaped groove penetrates the N well region 102, and the upper portion of one side of the N well region 102 is formed with an N+A doped region 105; the first gate oxide layer 103 is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region 102, and is provided with a window on one side; a semi-floating gate 104 which covers the first gate oxide layer 103 and completely fills the U-shaped groove, and is contacted with the N well region 102 at the window; the control gate dielectric comprises silicon oxide 106 and silicon nitride 107, covers the semi-floating gate 104 and extends over a portion of N+A doped region 105; a control gate 108 overlying the control gate dielectric; a source region 110 and a drain region 111, respectively formed on the N well region 102 and the N on both sides of the control gate+In the doped region 105.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (6)
1. A preparation method of a semi-floating gate transistor with adjustable tunneling efficiency is characterized in that,
the method comprises the following steps:
forming a P well region in a device manufacturing region of a substrate, and then carrying out first light doping N-type ion implantation to form an N well region so as to form channel impurity distribution of a semi-floating gate transistor, wherein the N well region is positioned above the P well region;
etching to form a U-shaped groove, and enabling the U-shaped groove to penetrate through the N well region;
depositing a first gate oxide layer, then etching, forming a window on the surface of the N well region, and then forming a semi-floating gate to cover the first gate oxide layer, completely fill the U-shaped groove and be in contact with the N well region at the window;
performing edge etching to expose the surface of the N-well region adjacent to one side of the window, performing secondary heavy doping N-type ion implantation to form N-well region+The doping area is used for regulating and controlling the tunneling efficiency of the tunneling transistor;
forming a control gate dielectric covering the semi-floating gate and extending over a portion of the N+Doping area, then forming control gate to cover the control gate medium;
and forming a source region and a drain region on two sides of the control gate.
2. The method of claim 1, wherein the tunneling-efficiency-adjustable semi-floating gate transistor is formed on a substrate,
the semi-floating gate is made of P-type polycrystalline silicon, and the control gate is made of N-type polycrystalline silicon.
3. The method of claim 1, wherein the tunneling-efficiency-adjustable semi-floating gate transistor is formed on a substrate,
the dosage range of the first lightly doped N-type ion implantation is 8e12cm-2～8e13cm-2；
The dose range of the second heavily doped N-type ion implantation is 1e14cm-2～5e14cm-2。
4. A semi-floating gate transistor with adjustable tunneling efficiency is characterized in that,
the method comprises the following steps:
a substrate having a P well region, an N well region disposed above the P well region, and a U-shaped groove penetrating the N well region and having an N region formed on one side thereof+A doped region;
the first gate oxide layer is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region, and is provided with a window on one side;
the semi-floating gate covers the first gate oxide layer, completely fills the U-shaped groove, and is contacted with the N well region at the window;
a control gate dielectric covering the semi-floating gate and extending to cover a portion of the N+A doped region;
a control gate overlying the control gate dielectric;
a source region and a drain region respectively formed at both sides of the control gate, the N well region and the N+In the doped region.
5. The tunneling efficiency tunable semi-floating gate transistor according to claim 4,
the semi-floating gate is made of P-type polycrystalline silicon, and the control gate is made of N-type polycrystalline silicon.
6. The tunneling efficiency tunable semi-floating gate transistor according to claim 4,
the control gate dielectric includes a silicon oxide layer and a silicon nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111477722.2A CN114171390A (en) | 2021-12-06 | 2021-12-06 | Tunneling efficiency adjustable semi-floating gate transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111477722.2A CN114171390A (en) | 2021-12-06 | 2021-12-06 | Tunneling efficiency adjustable semi-floating gate transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114171390A true CN114171390A (en) | 2022-03-11 |
Family
ID=80483385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111477722.2A Pending CN114171390A (en) | 2021-12-06 | 2021-12-06 | Tunneling efficiency adjustable semi-floating gate transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114171390A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05167080A (en) * | 1991-12-16 | 1993-07-02 | Fujitsu Ltd | Non-volatile semiconductor memory cell |
| US5554551A (en) * | 1994-11-23 | 1996-09-10 | United Microelectronics Corporation | Method of manufacture of an EEPROM cell with self-aligned thin dielectric area |
| US20150325663A1 (en) * | 2013-05-02 | 2015-11-12 | Fudan University | Semi-floating-gate device and its manufacturing method |
| CN107958907A (en) * | 2017-10-13 | 2018-04-24 | 上海集成电路研发中心有限公司 | A kind of half floating gate memory device and its manufacture method with U-shaped groove |
| CN109860191A (en) * | 2018-12-28 | 2019-06-07 | 上海集成电路研发中心有限公司 | A kind of semi-floating gate memory device and its manufacturing method |
| CN110416084A (en) * | 2019-07-10 | 2019-11-05 | 复旦大学 | Semi-floating gate transistor with high K/metal gate structure and preparation method thereof |
-
2021
- 2021-12-06 CN CN202111477722.2A patent/CN114171390A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05167080A (en) * | 1991-12-16 | 1993-07-02 | Fujitsu Ltd | Non-volatile semiconductor memory cell |
| US5554551A (en) * | 1994-11-23 | 1996-09-10 | United Microelectronics Corporation | Method of manufacture of an EEPROM cell with self-aligned thin dielectric area |
| US20150325663A1 (en) * | 2013-05-02 | 2015-11-12 | Fudan University | Semi-floating-gate device and its manufacturing method |
| CN107958907A (en) * | 2017-10-13 | 2018-04-24 | 上海集成电路研发中心有限公司 | A kind of half floating gate memory device and its manufacture method with U-shaped groove |
| CN109860191A (en) * | 2018-12-28 | 2019-06-07 | 上海集成电路研发中心有限公司 | A kind of semi-floating gate memory device and its manufacturing method |
| CN110416084A (en) * | 2019-07-10 | 2019-11-05 | 复旦大学 | Semi-floating gate transistor with high K/metal gate structure and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 王玮: "新型隧穿晶体管及半浮栅动态存储器的设计与仿真", 信息科技, vol. 1, no. 3, 15 March 2016 (2016-03-15), pages 137 - 330 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7399679B2 (en) | Narrow width effect improvement with photoresist plug process and STI corner ion implantation | |
| US8513103B2 (en) | Method for manufacturing vertical transistor having buried junction | |
| US11532637B2 (en) | Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region | |
| US7071515B2 (en) | Narrow width effect improvement with photoresist plug process and STI corner ion implantation | |
| US12074215B2 (en) | Semiconductor device and semiconductor device manufacturing method | |
| US6225659B1 (en) | Trenched gate semiconductor device and method for low power applications | |
| CN108807392B (en) | Flash memory and manufacturing method thereof | |
| US20030222306A1 (en) | Method of forming a semiconductor device in a semiconductor layer and structure thereof | |
| CN107958907B (en) | A kind of semi-floating gate memory device with U-shaped trench and its manufacturing method | |
| US5990515A (en) | Trenched gate non-volatile semiconductor device and method with corner doping and sidewall doping | |
| CN114256075A (en) | High-speed low-leakage split-gate type semi-floating gate transistor and preparation method thereof | |
| KR101133212B1 (en) | Semiconductor devices having source/drain regions disposed at both sides of a channel region and methods of forming the same | |
| US9806087B2 (en) | Low cost high performance EEPROM device | |
| CN114050159A (en) | Memory device and method of making the same | |
| JPH0715949B2 (en) | DRAM cell and manufacturing method thereof | |
| CN114141629B (en) | A window self-aligned split-gate semi-floating gate transistor and its manufacturing method | |
| CN114171390A (en) | Tunneling efficiency adjustable semi-floating gate transistor and preparation method thereof | |
| CN114203555B (en) | A semi-floating gate transistor with stable threshold voltage and a method for manufacturing the same | |
| US6917064B2 (en) | Trench capacitor and a method for manufacturing the same | |
| US11929410B2 (en) | Method for fabricating hydrogen treated surface of semiconductor device with buried gate | |
| US10707225B2 (en) | Semiconductor memory device and fabrication method thereof | |
| CN106549018B (en) | Cell contact structure | |
| CN114335188B (en) | A small-size memory device structure and its manufacturing method | |
| US20250294850A1 (en) | Memory device and manufacturing method thereof | |
| US7985998B2 (en) | Trench-type semiconductor device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |