CN114203634B - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an isolation region and a device region, the isolation region comprising a first region and a second region arranged along a second direction; forming a plurality of first fins and a plurality of second fins on the device region, the second fins having an isolation opening located on the isolation region, the isolation opening penetrating the second fins along the second direction; forming a plurality of first gate structures on the isolation region; removing the first gate structures on the first region and the second region using the first patterned layer as a mask to form a first opening; etching the first fin using the first patterned layer as a mask to form a second opening; and forming an isolation structure in the first opening and the second opening. The first opening and the second opening are both formed using the first patterned layer as a mask, which effectively reduces the number of photomasks, saves manufacturing costs, and also improves process efficiency.

Description

Method for forming semiconductor structure

Technical Field

The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure.

Background Art

As the integration of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as the size of transistors decreases dramatically, the thickness of the gate dielectric layer and the operating voltage cannot change accordingly, making it more difficult to suppress the short channel effect and increasing the channel leakage current of the transistor.

The gate of the Fin Field-Effect Transistor (FinFET) is a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewalls of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and disconnection of the circuit on both sides of the fin. This design can increase the control of the gate over the channel region, thereby effectively suppressing the short channel effect of the transistor. However, the Fin Field-Effect Transistor still has a short channel effect.

In addition, in order to further reduce the impact of the short channel effect on semiconductor devices and reduce channel leakage current, strained silicon technology has been introduced into the field of semiconductor technology. The method of strained silicon technology includes: forming grooves in the fins on both sides of the gate structure; and forming source and drain doping regions in the grooves by an epitaxial growth process.

In order to prevent the source and drain doping regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fin, and in order to reduce the area of the isolation layer and improve the integration of the formed semiconductor structure, the prior art introduces SDB (Single Diffusion Break) technology.

However, the existing methods still have many problems in the process of forming semiconductor structures.

Summary of the invention

The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively reduce the manufacturing cost of the semiconductor structure and also improve the process efficiency of forming the semiconductor structure.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an isolation region and a device region arranged along a first direction, the isolation region being located between adjacent device regions, the isolation region comprising a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; forming a plurality of first fins and a plurality of second fins on the device region, the first fins and the second fins being arranged in parallel along the second direction, the first fins also spanning over the isolation region, the second fins having an isolation opening located on the isolation region, the isolation opening penetrating the second fin along the second direction; forming a plurality of first fins on the isolation region, A first gate structure is provided, wherein the first gate structure spans the first fin and the second fin; a dielectric layer is formed on the substrate, wherein the dielectric layer covers the sidewalls of the first gate structure; a first patterned layer is formed on the first gate structure and the dielectric layer to expose the first gate structure located on the first region; the first patterned layer is used as a mask, and a first etching process is adopted to remove the first gate structure on the first region and the second region, thereby forming a first opening in the dielectric layer; the first patterned layer is used as a mask, and a second etching process is adopted to etch the first fin, thereby forming a second opening in the first fin; and an isolation structure is formed in the first opening and the second opening.

Optionally, the first etching process adopts an isotropic etching process, and the isotropic etching process includes a wet etching process.

Optionally, the parameters of the wet etching process include: the etching solution is a mixed solution of sulfuric acid and hydrogen peroxide, and the temperature of the etching solution is 80° C. to 180° C.

Optionally, the second etching process adopts an anisotropic etching process, and the anisotropic etching process includes a dry etching process.

Optionally, the parameters of the dry etching process include: the etching gas includes hydrogen bromide, chlorine and oxygen.

Optionally, in the process of forming the first gate structure, the method further includes: forming a plurality of second gate structures on the device region, wherein the second gate structures span the first fin and the second fin.

Optionally, before forming the first gate structure and the second gate structure, it also includes: forming a plurality of first source-drain doped layers in the first fin, the first source-drain doped layers are located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second fin, the first source-drain doped layers are located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and the second source-drain doped layers have second source-drain ions.

Optionally, the first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; and the second source-drain ions include P-type ions or N-type ions.

Optionally, before forming the first source-drain doped layer and the second source-drain doped layer, it also includes: forming a plurality of first dummy gate structures on the isolation region, the first dummy gate structure spanning the first fin and the second fin; forming a plurality of second dummy gate structures on the device region, the second dummy gate structure spanning the first fin and the second fin.

Optionally, the method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming the first source-drain doped layer in the first source-drain opening; and forming the second source-drain doped layer in the second source-drain opening.

Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source-drain doping layer, the second source-drain doping layer, the first pseudo-gate structure and the second pseudo-gate structure; and flattening the initial dielectric layer until the top surfaces of the first pseudo-gate structure and the second pseudo-gate structure are exposed to form the dielectric layer.

Optionally, the method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure and forming a first gate opening in the dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure and forming a second gate opening in the dielectric layer; and forming the second gate structure in the second gate opening.

Optionally, the method for forming the isolation structure includes: forming an initial isolation structure in the first opening and the second opening, and on the first gate structure and the dielectric layer; flattening the initial isolation structure until the top surface of the first gate structure and the dielectric layer is exposed, and forming the isolation structure in the first opening and the second opening.

Optionally, the material of the isolation structure includes silicon nitride.

Optionally, the first patterning layer includes: a first mask layer and a second mask layer located on the first mask layer.

Optionally, the material of the first mask layer includes silicon nitride.

Optionally, the material of the second mask layer includes silicon oxide.

Optionally, after forming the first opening and the second opening, the method further includes: removing the first patterned layer.

Optionally, the method for forming the second fin includes: forming a plurality of initial second fins arranged in parallel along the second direction on the substrate; forming a second patterned layer on the substrate to expose a portion of the initial second fins; and etching the initial second fins using the second patterned layer as a mask until the top surface of the substrate is exposed to form the second fins.

Optionally, after forming the first fin and the second fin, it also includes: forming an isolation layer on the substrate, the isolation layer covering part of the side walls of the first fin and the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the formation method of the technical solution of the present invention, by forming an isolation structure in the first opening and the second opening, it is possible to effectively prevent short circuits between the first source-drain doped layers formed in the first fin and short circuits between the second source-drain doped layers formed in the second fin, thereby achieving an isolation effect.

In addition, the first patterned layer exposes the top surface of the first gate structure located on the first region, and the first patterned layer is used as a mask to remove the first gate structure located on the first region and the second region of the isolation region by a first etching process, so as to form a first opening in the dielectric layer; the first patterned layer is continued to be used as a mask to etch the first fin by a second etching process, so as to form a second opening in the first fin, and the first opening exposes the second opening. The first opening and the second opening are both formed by using the first patterned layer as a mask, which effectively reduces the number of photomasks, saves the manufacturing cost, and also improves the manufacturing efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 3 are schematic diagrams of the structure of a semiconductor structure;

4 to 24 are schematic structural diagrams of various steps of an embodiment of a method for forming a semiconductor structure of the present invention.

DETAILED DESCRIPTION

As described in the background art, the existing methods still have many problems in the process of forming semiconductor structures, which will be described in detail below with reference to the accompanying drawings.

Please refer to Figures 1 to 3, Figure 1 is a top view of a semiconductor structure with a dielectric layer and an isolation layer omitted, Figure 2 is a cross-sectional schematic diagram of Figure 1 along the A-A direction, and Figure 3 is a cross-sectional schematic diagram of Figure 1 along the B-B direction; a semiconductor structure includes a substrate 100, the substrate 100 includes an isolation region B1, a first device region A1, and a second device region A2 arranged along a first direction X, the isolation region B1 is located between the first device region A1 and the second device region A2; a plurality of first fins 101 and a plurality of second fins 102 located on the substrate 100, the first fins 101 and the second fins 102 are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, the first fins 101 cross the isolation region B1 from the first device region A1 and extend to the second device region A2, the second fins 102 have isolation openings 103 therein, and the isolation openings 103 are provided therein. 3 penetrates the second fin 102 along the second direction Y, and the isolation opening 103 is located on the isolation area B1; a plurality of gate structures 104 are formed on the first device area A1 and the second device area A2, and the gate structure 104 spans the first fin 101 and the second fin 102; a dielectric layer 105 is located on the substrate 100, and the dielectric layer 105 covers the sidewalls of the gate structure 104; a first opening (not marked) is located in the dielectric layer 105 and the first fin 101, and the first opening extends along the second direction Y; a second opening (not marked) is located in the dielectric layer 105, and the second opening extends along the second direction Y, and the second opening exposes part of the sidewall and top surface of the second fin 102; a first isolation structure 106 is located in the first opening; and a second isolation structure 107 is located in the second opening.

In this embodiment, by forming the first isolation structure 106 and the second isolation structure 107, the short circuit between the first source-drain doped layers formed in the first fin 101 and the short circuit between the second source-drain doped layers formed in the second fin 102 can be effectively prevented, thereby achieving an isolation effect.

In this embodiment, the first fin 101 is used to form a PMOS transistor structure, and the second fin 102 is used to form an NMOS transistor structure. Since the PMOS transistor structure and the NMOS transistor structure have different stress requirements on the fin, the PMOS transistor structure requires the first fin 101 to provide compressive stress, and the compressive stress is generated by the first isolation structure 106 acting on the first fin 101, while the NMOS transistor structure requires the second fin 102 to provide tensile stress, and the tensile stress is generated by the second isolation structure 107 acting on the second fin 102. Since tensile stress and compressive stress are two different types of stress, the corresponding structural forms of the first isolation structure 106 and the second isolation structure 107 will also be different. In this embodiment, by setting the depths of the first opening and the second opening differently, the first isolation structure 106 and the second isolation structure 107 of different structural forms are formed, and the first isolation structure 106 acts on the first fin 101 to generate compressive stress, and the second isolation structure 107 acts on the second fin 102 to generate tensile stress.

However, since the depths of the first opening and the second opening are different, forming the first opening and the second opening of different depths usually requires two step-by-step production of photomasks. This not only increases the number of masks and increases production costs, but also reduces production efficiency by forming the first opening and the second opening in steps.

On this basis, the present invention provides a method for forming a semiconductor structure. By forming an isolation structure in the first opening and the second opening, it is possible to effectively prevent the short circuit between the first source-drain doped layer formed in the first fin and the short circuit between the second source-drain doped layer formed in the second fin, thereby achieving an isolation effect. In addition, the first patterned layer has a first patterned opening that exposes the top surface of the first gate structure located on the first region. The first patterned layer is used as a mask, and a first etching process is used to remove the first gate structure located on the first region and the second region of the isolation region, forming a first opening in the dielectric layer; the first patterned layer is continued to be used as a mask, and a second etching process is used to etch the first fin, forming a second opening in the first fin, and the first opening exposes the second opening. The first opening and the second opening are both formed using the first patterned layer as a mask, which effectively reduces the photomask, saves the manufacturing cost, and also improves the process efficiency.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

4 to 24 are schematic structural diagrams of a process for forming a semiconductor structure according to an embodiment of the present invention.

Please refer to Figure 4, a substrate 200 is provided, the substrate 200 includes an isolation region B1 and a device region A1 arranged along a first direction X, the isolation region B1 is located between adjacent device regions A1, and the isolation region B1 includes a first region I and a second region II arranged along a second direction Y, and the second direction Y is perpendicular to the first direction X.

In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Please refer to Figures 5 to 7, Figure 6 is a schematic cross-sectional view of Figure 5 along the C-C direction, and Figure 7 is a schematic cross-sectional view of Figure 5 along the D-D direction. A plurality of first fins 201 and a plurality of second fins 202 are formed on the device area A1, and the first fins 201 and the second fins 202 are arranged in parallel along the second direction Y. The first fins 201 also span across the isolation area B1, and the second fins 202 have an isolation opening 203 located on the isolation area B1, and the isolation opening 203 penetrates the second fins 202 along the second direction Y.

In this embodiment, the method for forming the second fin 202 includes: forming a plurality of initial second fins (not shown) arranged in parallel along the second direction Y on the substrate 200; forming a second patterned layer (not shown) on the substrate 200 to expose a portion of the initial second fins; etching the initial second fins using the second patterned layer as a mask until the top surface of the substrate 200 is exposed to form the second fins 202.

In this embodiment, the material of the first fin 201 and the second fin 202 is silicon; in other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Please refer to Figures 8 and 9, Figure 8 is consistent with the viewing direction of Figure 6, and Figure 9 is consistent with the viewing direction of Figure 7. An isolation layer 204 is formed on the substrate 200, and the isolation layer 204 covers part of the side walls of the first fin 201 and the second fin 202, and the top surface of the isolation layer 204 is lower than the top surface of the first fin 201 and the second fin 202.

In this embodiment, the method for forming the isolation layer 204 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing part of the initial isolation layer to form the isolation layer 204, wherein the top surface of the isolation layer 204 is lower than the top surfaces of the first fin and the second fin.

The material of the isolation layer 204 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 204 is silicon oxide.

After forming the isolation layer 204, the method further includes: forming a plurality of first source-drain doped layers in the first fin 201; forming a plurality of second source-drain doped layers in the second fin 202; forming a plurality of first gate structures on the isolation region B1, the first gate structures spanning the first fin 201 and the second fin 202; forming a plurality of second gate structures on the device region A1, the second gate structures spanning the first fin 201 and the second fin 202; and forming a dielectric layer on the substrate 200, the dielectric layer covering the sidewalls of the first gate structures. Please refer to FIGS. 10 to 17 for the specific formation process.

Please refer to Figures 10 and 11. Several first dummy gate structures 205 are formed on the isolation area B1, and the first dummy gate structure 205 spans the first fin 201 and the second fin 202. Several second dummy gate structures 206 are formed on the device area A1, and the second dummy gate structure 206 spans the first fin 201 and the second fin 202.

In this embodiment, the method for forming the first dummy gate structure 205 includes: forming a first dummy gate dielectric layer (not labeled) on the isolation layer 204; forming a first dummy gate layer (not labeled) on the first dummy gate dielectric layer; and forming a first sidewall (not labeled) on the first dummy gate layer and the sidewall of the first dummy gate dielectric layer.

In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer may also be silicon oxynitride.

In this embodiment, the material of the first dummy gate layer is polysilicon.

In this embodiment, the method for forming the second dummy gate structure 206 includes: forming a second dummy gate dielectric layer (not labeled) on the isolation layer 204; forming a second dummy gate layer (not labeled) on the second dummy gate dielectric layer; and forming a second sidewall (not labeled) on the second dummy gate layer and the sidewall of the second dummy gate dielectric layer.

In this embodiment, the material of the second dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the second dummy gate layer is also the same as that of the first dummy gate layer.

In the present embodiment, the first dummy gate structure 205 and the second dummy gate structure 206 are formed simultaneously. The first dummy gate structure 205 and the second dummy gate structure 206 are formed simultaneously through a global process, which can effectively improve production efficiency.

Please refer to Figures 12 and 13. The first fin 201 is etched using the first dummy gate structure 205 and the second dummy gate structure 206 as a mask to form a plurality of first source and drain openings (not marked) in the first fin 201; the second fin 202 is etched using the first dummy gate structure 205 and the second dummy gate structure 206 as a mask to form a plurality of second source and drain openings (not marked) in the second fin 202; the first source and drain doping layer 207 is formed in the first source and drain openings; and the second source and drain doping layer 208 is formed in the second source and drain openings.

In this embodiment, the method for forming the first source-drain doped layer 207 in the first source-drain opening includes: forming a first epitaxial layer (not marked) in the first source-drain opening using an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth process, and introducing first source-drain ions into the first epitaxial layer to form the first source-drain doped layer 207.

In this embodiment, the method for forming the second source-drain doped layer 208 in the second source-drain opening includes: forming a second epitaxial layer (not marked) in the second source-drain opening using an epitaxial growth process; in-situ doping the second epitaxial layer during the epitaxial growth process, and introducing second source-drain ions into the second epitaxial layer to form the second source-drain doped layer 208.

In this embodiment, the electrical types of the first source and drain ions are different from those of the second source and drain ions; the first source and drain ions are P-type ions, and the second source and drain ions are N-type ions. In other embodiments, the first source and drain ions may also be N-type ions, and the second source and drain ions may be P-type ions.

Please refer to Figures 14 and 15, an initial dielectric layer (not shown) is formed on the substrate 200, and the initial dielectric layer covers the first source-drain doping layer 207, the second source-drain doping layer 208, the first dummy gate structure 205 and the second dummy gate structure 206; the initial dielectric layer is planarized until the top surfaces of the first dummy gate structure 205 and the second dummy gate structure 206 are exposed, so as to form the dielectric layer 209.

In this embodiment, the material of the dielectric layer 209 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

Please refer to Figures 16 and 17, the first dummy gate structure 205 is removed, and a first gate opening (not marked) is formed in the dielectric layer 209; the first gate structure 210 is formed in the first gate opening; the second dummy gate structure 206 is removed, and a second gate opening is formed in the dielectric layer 209; and the second gate structure 211 is formed in the second gate opening.

In this embodiment, specifically, the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 205 are removed; the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 206 are removed.

In this embodiment, the first gate structure 210 includes: a first gate dielectric layer (not labeled), a first gate layer (not labeled) located on the first gate dielectric layer, and a first protective layer (not labeled) located on the first gate layer; the second gate structure 211 includes: a second gate dielectric layer (not labeled), a second gate layer (not labeled) located on the second gate dielectric layer, and a second protective layer (not labeled) located on the second gate layer.

In this embodiment, the material of the first gate dielectric layer and the second gate dielectric layer includes a high-K dielectric material.

The material of the first gate layer and the second gate layer includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the first gate layer and the second gate layer is tungsten.

In this embodiment, the first protective layer and the second protective layer are made of silicon nitride.

Referring to FIG. 18 and FIG. 19 , a first patterned layer exposing the first gate structure 210 located on the first region I is formed on the first gate structure 210 and the dielectric layer 209 .

In this embodiment, the method for forming the first patterned layer includes: forming an initial first patterned layer (not shown) on the first gate structure 210, the second gate structure 211 and the dielectric layer 209; forming a photoresist layer (not shown) on the initial first patterned layer, wherein the photoresist layer has a photoresist opening exposing a portion of the initial first patterned layer; etching the initial first patterned layer using the photoresist layer as a mask until the top surface of the first gate structure 210 located on the first region I is exposed to form the first patterned layer; after forming the first patterned layer, removing the photoresist layer.

In this embodiment, the first patterning layer includes: a first mask layer 212 and a second mask layer 213 located on the first mask layer 212 .

In this embodiment, the material of the first mask layer 212 is silicon nitride, and the material of the second mask layer 213 is silicon oxide.

20 and 21 , the first patterned layer is used as a mask and a first etching process is adopted to remove the first gate structure 210 on the first region I and the second region II, and a first opening 214 is formed in the dielectric layer 209 .

In this embodiment, the first etching process adopts an isotropic etching process, and the isotropic etching process includes a wet etching process. The parameters of the wet etching process include: the etching solution is a mixed solution of sulfuric acid and hydrogen peroxide, and the temperature of the etching solution is 80° C. to 180° C.

Referring to FIG. 22 , the first patterned layer is used as a mask and a second etching process is adopted to etch the first fin 201 , so as to form a second opening 215 in the first fin 201 .

In this embodiment, the second etching process adopts an anisotropic etching process, and the anisotropic etching process includes a dry etching process. The parameters of the dry etching process include: the etching gas includes hydrogen bromide, chlorine and oxygen.

Since the first patterned layer exposes the top surface of the first gate structure 210 located on the first region I, the first patterned layer is used as a mask, and the first etching process is adopted to remove the first gate structure 210 located on the first region I and the second region II of the isolation region B1, and a first opening 214 is formed in the dielectric layer 209; the first patterned layer is continued to be used as a mask, and the first fin 201 is etched by a second etching process, and a second opening 215 is formed in the first fin 201. The first opening 214 and the second opening 215 are both formed by using the first patterned layer as a mask, which effectively reduces the number of photomasks, saves the manufacturing cost, and also improves the process efficiency.

Please refer to FIG. 23 and FIG. 24 . After the first opening 214 and the second opening 215 are formed, the first patterned layer is removed; and an isolation structure 216 is formed in the first opening 214 and the second opening 215 .

By forming an isolation structure 216 in the first opening 214 and the second opening 215, short circuits between the first source-drain doped layers 207 formed in the first fin 201 and short circuits between the second source-drain doped layers 208 formed in the second fin 202 can be effectively prevented, thereby achieving an isolation effect.

In addition, since the structural morphology of the isolation structure 216 in the first region I and the second region II is different, the isolation structure 216 generates compressive stress on the first fin 201 and generates tensile stress on the second fin 202, thereby meeting the different stress requirements of the PMOS transistor structure and the NMOS transistor structure and improving the performance of the finally formed semiconductor structure.

In this embodiment, the method for forming the isolation structure 216 includes: forming an initial isolation structure (not shown) in the first opening 214 and the second opening 215, and on the first gate structure 210, the second gate structure 211 and the dielectric layer 209; flattening the initial isolation structure until the top surfaces of the first gate structure 210, the second gate structure 211 and the dielectric layer 209 are exposed, and forming the isolation structure 216 in the first opening 214 and the second opening 215.

In this embodiment, the isolation structure 216 is made of silicon nitride.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising: Providing a substrate, the substrate comprising an isolation region and a device region arranged along a first direction, the isolation region being located between adjacent device regions, the isolation region comprising a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; A plurality of first fins and a plurality of second fins are formed on the device region, wherein the first fins and the second fins are arranged in parallel along the second direction, the first fins also span over the isolation region, and the second fins have isolation openings located on the isolation region, and the isolation openings penetrate the second fins along the second direction; forming a plurality of first gate structures on the isolation region, wherein the first gate structures span the first fin and the second fin; forming a dielectric layer on the substrate, wherein the dielectric layer covers the sidewalls of the first gate structure; forming a first patterned layer on the first gate structure and the dielectric layer to expose the first gate structure located on the first region; Using the first patterned layer as a mask, a first etching process is used to remove the first gate structure on the first region and the second region, and a first opening is formed in the dielectric layer; Using the first patterned layer as a mask, etching the first fin by a second etching process to form a second opening in the first fin; An isolation structure is formed in the first opening and the second opening. 2 . The method for forming a semiconductor structure according to claim 1 , wherein the first etching process adopts an isotropic etching process, and the isotropic etching process includes a wet etching process. 3 . 3. The method for forming a semiconductor structure according to claim 2, characterized in that the parameters of the wet etching process include: the etching solution is a mixed solution of sulfuric acid and hydrogen peroxide, and the temperature of the etching solution is 80°C to 180°C. 4 . The method for forming a semiconductor structure according to claim 1 , wherein the second etching process adopts an anisotropic etching process, and the anisotropic etching process includes a dry etching process. 5 . The method for forming a semiconductor structure according to claim 4 , wherein the parameters of the dry etching process include: the etching gas includes hydrogen bromide, chlorine and oxygen. 6 . The method for forming a semiconductor structure according to claim 1 , wherein during the process of forming the first gate structure, the method further comprises: forming a plurality of second gate structures on the device region, wherein the second gate structures span the first fin and the second fin. 7. The method for forming a semiconductor structure as described in claim 6 is characterized in that, before forming the first gate structure and the second gate structure, it also includes: forming a plurality of first source-drain doped layers in the first fin, the first source-drain doped layers are located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second fin, the first source-drain doped layers are located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and the second source-drain doped layers have second source-drain ions. 8. The method for forming a semiconductor structure as described in claim 7 is characterized in that the first source and drain ions are of different electrical types from the second source and drain ions; the first source and drain ions include N-type ions or P-type ions; and the second source and drain ions include P-type ions or N-type ions. 9. The method for forming a semiconductor structure as described in claim 7 is characterized in that before forming the first source-drain doped layer and the second source-drain doped layer, it also includes: forming a plurality of first dummy gate structures on the isolation region, the first dummy gate structure spanning the first fin and the second fin; forming a plurality of second dummy gate structures on the device region, the second dummy gate structure spanning the first fin and the second fin. 10. The method for forming a semiconductor structure as described in claim 9 is characterized in that the method for forming the first source-drain doped layer and the second source-drain doped layer comprises: etching the first fin with the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin with the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming the first source-drain doped layer in the first source-drain opening; and forming the second source-drain doped layer in the second source-drain opening. 11. The method for forming a semiconductor structure as described in claim 10 is characterized in that the method for forming the dielectric layer comprises: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source-drain doping layer, the second source-drain doping layer, the first dummy gate structure and the second dummy gate structure; and planarizing the initial dielectric layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form the dielectric layer. 12. The method for forming a semiconductor structure as described in claim 9 is characterized in that the method for forming the first gate structure and the second gate structure comprises: removing the first dummy gate structure to form a first gate opening in the dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure to form a second gate opening in the dielectric layer; and forming the second gate structure in the second gate opening. 13. The method for forming a semiconductor structure as described in claim 1 is characterized in that the method for forming the isolation structure comprises: forming an initial isolation structure in the first opening and the second opening, and on the first gate structure and the dielectric layer; flattening the initial isolation structure until the top surfaces of the first gate structure and the dielectric layer are exposed, and forming the isolation structure in the first opening and the second opening. 14. The method for forming a semiconductor structure according to claim 1, wherein a material of the isolation structure comprises silicon nitride. 15 . The method for forming a semiconductor structure according to claim 1 , wherein the first patterned layer comprises: a first mask layer and a second mask layer located on the first mask layer. 16 . The method for forming a semiconductor structure according to claim 15 , wherein a material of the first mask layer comprises silicon nitride. 17 . The method for forming a semiconductor structure according to claim 15 , wherein a material of the second mask layer comprises silicon oxide. 18 . The method for forming a semiconductor structure according to claim 1 , further comprising: removing the first patterned layer after forming the first opening and the second opening. 19. The method for forming a semiconductor structure as described in claim 1 is characterized in that the method for forming the second fin comprises: forming a plurality of initial second fins arranged in parallel along the second direction on the substrate; forming a second patterned layer on the substrate to expose a portion of the initial second fins; etching the initial second fins using the second patterned layer as a mask until the top surface of the substrate is exposed to form the second fins. 20. The method for forming a semiconductor structure as described in claim 1 is characterized in that after forming the first fin and the second fin, it also includes: forming an isolation layer on the substrate, the isolation layer covers part of the side walls of the first fin and the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin.