CN114222081A - A low noise image sensor - Google Patents

Abstract

The invention discloses a low-noise image sensor, wherein pixel units are respectively manufactured on two round crystals to form a back-illuminated image sensor with three round crystals stacked, and the back-illuminated image sensor respectively comprises a photodiode round crystal, a pixel control round crystal and a logic control round crystal from top to bottom. The Photodiode (PD), transfer gate transistor (M1), floating diffusion (FD1) are fabricated on a separate photodiode wafer, the reset transistor (M2), source follower transistor (M3), row select transistor (M4) are fabricated on another pixel control wafer, and the floating diffusion (FD1) is connected to the gate of the source follower transistor (M3) by copper-copper interconnection. The conventional planar pixel unit is improved into a three-dimensional pixel unit, the size of each pixel unit is reduced while the area of a photodiode is kept unchanged, and the size (W/L) of a source follower transistor is increased.

Description

Low-noise image sensor

Technical Field

The present invention relates to an image sensor, and more particularly, to a low noise image sensor.

Background

CMOS image sensors are now widely used in imaging applications and even high-end applications.

The CMOS image sensor reduces readout noise by Correlated Double Sampling (CDS). Causing Random Telegraph Signal (RTS) noise, which increases as the size of the source follower transistors in the pixel cells decreases, especially in the context of decreasing scaling transistor sizes, where the transistor sizes of the individual transistors of the pixel cells are decreasing in area, and the source follower transistors are decreasing in size, resulting in increased RTS noise, thus becoming an important issue for low light level applications.

As shown in fig. 1a, 2, 4, and 6, in the conventional back-illuminated CMOS image sensor, a pixel unit is fabricated on a pixel array wafer, a logic circuit is fabricated on a logic control wafer, two wafers are bonded and stacked together, and a signal line is connected through a through-silicon via. As pixel sizes continue to shrink (pixel sizes are smaller than 0.64 microns) to meet the demand for larger pixel arrays (e.g., 1 hundred million pixels), the sizes of photodiodes and pixel control transistors are shrinking. Resulting in a decrease in pixel full well and an increase in Random Telegraph Signal (RTS) noise, affecting pixel performance.

In view of the above, the present invention is particularly proposed.

Disclosure of Invention

It is an object of the present invention to provide a low noise image sensor to solve the above technical problems in the prior art.

The purpose of the invention is realized by the following technical scheme:

the low-noise image sensor of the invention is characterized in that pixel units are respectively manufactured on two wafers to form a back-illuminated image sensor with three stacked wafers, wherein the three stacked wafers are respectively a photodiode wafer, a pixel control wafer and a logic control wafer from top to bottom.

Compared with the prior art, the low-noise image sensor provided by the invention has the advantages that on the structure of the traditional back-illuminated CMOS image sensor, the pixel units are respectively manufactured on the two round crystals which are respectively the photodiode round crystal from top to bottom, the image signal control round crystal and the analog signal control round crystal, and the back-illuminated image sensor with three round crystals stacked is commonly used. The pixel structure of the small-size low-noise image sensor is formed by keeping the area of the photodiode unchanged while the size of the pixel unit is reduced, and Random Telegraph Signal (RTS) noise is not increased, so that the dynamic range, the signal-to-noise ratio and the like are increased, and the performance of the small-size image sensor is optimized.

Drawings

FIG. 1a is a circuit diagram of a conventional CMOS image sensor in the prior art;

FIG. 1b is a circuit diagram of an image sensor according to an embodiment of the present invention;

the letters in the figures are abbreviated as customary in the art of circuit diagrams and refer to:

PD: photodiode

FD: floating diffusion node

FD 1: floating diffusion node using copper-copper interconnection

M1: pass gate transistor

M2: reset transistor

M3: source follower transistor

M4: row select transistor

FIG. 2 is a diagram illustrating a conventional image sensor in the prior art

FIG. 3 is a diagram of an image sensor structure according to an embodiment of the present invention

FIG. 4 is a top view of a pixel cell of a conventional CMOS image sensor

FIG. 5 is a top view of a pixel unit of an image sensor according to an embodiment of the present invention

FIG. 6 is a cross-sectional view of a conventional backside illuminated CMOS image sensor in the prior art

FIG. 7 is a cross-sectional view of a backside illuminated CMOS image sensor according to an embodiment of the present invention

In the figure:

101 Deep Trench Isolation (DTI), 102 Photodiode (PD), 103 transfer Transistor (TX), 104 reset transistor (RX), 105 Pixel Array Wafer (Pixel Array Wafer), 106 floating diffusion node (FD), 107 source follower transistor (SF), 108 row select transistor (SX), 109 photodiode Wafer (PD Wafer), 110 copper-copper interconnect (Cu-Cu Connect), 111 Pixel Control Wafer (Pixel Control Wafer), 112 Micro Lens (Micro Lens), 113 Color Filter (Color Filter), 114 Logic Control Wafer (Logic Wafer), 115 Shallow Trench Isolation (STI), 116 Gate Oxide (Gate Oxide), 117 dielectric Oxide layer (IMD Oxide), 118 Contact hole (Contact).

Detailed Description

The technical scheme in the embodiment of the invention is clearly and completely described below by combining the attached drawings in the embodiment of the invention; it is to be understood that the described embodiments are merely exemplary of the invention, and are not intended to limit the invention to the particular forms disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The terms that may be used herein are first described as follows:

the term "and/or" means that either or both can be achieved, for example, X and/or Y means that both cases include "X" or "Y" as well as three cases including "X and Y".

The terms "comprising," "including," "containing," "having," or other similar terms of meaning should be construed as non-exclusive inclusions. For example: including a feature (e.g., material, component, ingredient, carrier, formulation, material, dimension, part, component, mechanism, device, process, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product, or article of manufacture), is to be construed as including not only the particular feature explicitly listed but also other features not explicitly listed as such which are known in the art.

The term "consisting of … …" is meant to exclude any technical feature elements not explicitly listed. If used in a claim, the term shall render the claim closed except for the inclusion of the technical features that are expressly listed except for the conventional impurities associated therewith. If the term occurs in only one clause of the claims, it is defined only to the elements explicitly recited in that clause, and elements recited in other clauses are not excluded from the overall claims.

Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "secured," etc., are to be construed broadly, as for example: can be fixedly connected, can also be detachably connected or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms herein can be understood by those of ordinary skill in the art as appropriate.

The terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship that is indicated based on the orientation or positional relationship shown in the drawings for ease of description and simplicity of description only, and are not intended to imply or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting herein.

Details which are not described in detail in the embodiments of the invention belong to the prior art which is known to the person skilled in the art. Those not specifically mentioned in the examples of the present invention were carried out according to the conventional conditions in the art or conditions suggested by the manufacturer. The reagents or instruments used in the examples of the present invention are not specified by manufacturers, and are all conventional products available by commercial purchase.

The low-noise image sensor of the invention is characterized in that pixel units are respectively manufactured on two wafers to form a back-illuminated image sensor with three stacked wafers, wherein the three stacked wafers are respectively a photodiode wafer, a pixel control wafer and a logic control wafer from top to bottom.

And a copper-copper interconnection is arranged between the photodiode round crystal and the pixel control round crystal, and a through silicon through hole is arranged between the pixel control round crystal and the logic control round crystal.

The pixel unit includes: a Photodiode (PD), a transfer gate transistor (M1), a reset transistor (M2), a source follower transistor (M3), a row select transistor (M4), a floating diffusion node (FD 1);

the Photodiode (PD), the transfer gate transistor (M1), and the floating diffusion node (FD1) are formed on a separate photodiode wafer, the reset transistor (M2), the source follower transistor (M3), and the row select transistor (M4) are formed on another pixel control wafer, and the floating diffusion node (FD1) is connected to the gate of the source follower transistor (M3) via a copper-copper interconnect.

In summary, in the low noise image sensor according to the embodiments of the invention, the photodiode and the transfer transistor are fabricated on separate photodiode wafers. Other pixel control transistors (source follower transistor, reset transistor, row select transistor) are fabricated on another pixel control wafer and the floating diffusion node is connected to the source follower transistor gate by copper interconnect. The conventional planar pixel unit is improved into a three-dimensional pixel unit, the size of each pixel unit is reduced while the area of a photodiode is kept unchanged, and the size (W/L) of a source follower transistor is increased

The invention has the advantages that:

under the condition of keeping the area of the photodiode unchanged, the size of each pixel unit is reduced, so that more pixel arrays can be integrated into an image sensor chip.

The photodiode is independently manufactured on the photodiode wafer, so that shallow trench isolation can be avoided, the damage of the manufacturing process to silicon is avoided, and the generation of dark current is reduced.

The pixel control transistor is independently manufactured on the pixel control wafer, so that the source follower transistor can be kept to have larger size, and Random Telegraph Signal (RTS) noise caused by size reduction of the source follower is avoided.

In order to more clearly show the technical solutions and the technical effects provided by the present invention, the following detailed description is provided for the embodiments of the present invention with specific embodiments.

Example 1

As shown in fig. 1b, 3, 5 and 7, the present invention includes: deep Trench Isolation (DTI)101, Photodiode (PD)102, transfer Transistor (TX)103, reset transistor (RX)104, Pixel Array Wafer (Pixel Array Wafer)105, floating diffusion node (FD)106, source follower transistor (SF)107, row select transistor (SX)108, photodiode Wafer (PD Wafer)109, copper-copper interconnect (Cu-Cu Connect)110, Pixel Control Wafer (Pixel Control Wafer)111, microlens (Micro Lens)112, Color Filter (Color Filter)113, Logic Control Wafer (Logic Wafer)114, Shallow Trench Isolation (STI)115, Gate Oxide (Gate Oxide)116, dielectric Oxide layer (IMD Oxide)117, Contact hole (act) 118.

As shown in fig. 3, the pixel units are fabricated on two wafers respectively to form a back-illuminated image sensor with three stacked wafers, which are a photodiode wafer, a pixel control wafer and a logic control wafer from top to bottom.

And a copper-copper interconnection is arranged between the photodiode round crystal and the pixel control round crystal, and a through silicon through hole is arranged between the pixel control round crystal and the logic control round crystal.

As shown in fig. 1b, the pixel unit includes: a Photodiode (PD), a transfer gate transistor (M1), a reset transistor (M2), a source follower transistor (M3), a row select transistor (M4), a floating diffusion node (FD 1);

the Photodiode (PD), the transfer gate transistor (M1), and the floating diffusion node (FD1) are formed on a separate photodiode wafer, the reset transistor (M2), the source follower transistor (M3), and the row select transistor (M4) are formed on another pixel control wafer, and the floating diffusion node (FD1) is connected to the gate of the source follower transistor (M3) via a copper-copper interconnect.

As shown in fig. 5 and fig. 7, which are a top view of a pixel unit of an image sensor according to an embodiment of the present invention and a cross-sectional view of a back-illuminated CMOS image sensor according to an embodiment of the present invention, respectively, a detailed layout of a local detail of each component is shown, and a skilled person can perform layout and fabrication according to the schemes shown in fig. 5 and fig. 7; it can also be designed and manufactured according to the scheme and circuit given in fig. 1b and fig. 3.

The core of the invention is:

the pixel structure is formed by forming the photodiode and the transfer transistor on separate photodiode wafers. Other pixel control transistors (source follower transistor, reset transistor, row select transistor) are fabricated on another pixel control wafer and the floating diffusion node is connected to the source follower transistor gate by copper interconnect.

The conventional planar pixel unit is improved into a three-dimensional pixel unit, the size of each pixel unit is reduced while the area of a photodiode is kept unchanged, and the size (W/L) of a source follower transistor is increased.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Claims (3)

1. A low-noise image sensor is characterized in that pixel units are respectively manufactured on two wafers to form a back-illuminated image sensor with three wafers stacked, wherein the three wafers are respectively a photodiode wafer, a pixel control wafer and a logic control wafer from top to bottom.

2. A low noise image sensor according to claim 1, wherein a copper-copper interconnection is provided between the photodiode wafer and the pixel control wafer, and a through silicon via is provided between the pixel control wafer and the logic control wafer.

3. A low noise image sensor according to claim 2, wherein said pixel unit comprises: a Photodiode (PD), a transfer gate transistor (M1), a reset transistor (M2), a source follower transistor (M3), a row select transistor (M4), a floating diffusion node (FD 1);

the Photodiode (PD), the transfer gate transistor (M1), and the floating diffusion node (FD1) are formed on a separate photodiode wafer, the reset transistor (M2), the source follower transistor (M3), and the row select transistor (M4) are formed on another pixel control wafer, and the floating diffusion node (FD1) is connected to the gate of the source follower transistor (M3) via a copper-copper interconnect.

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