CN114256230A

CN114256230A - Semiconductor structure and forming method thereof

Info

Publication number: CN114256230A
Application number: CN202010997706.5A
Authority: CN
Inventors: 王洪岩
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-09-21
Filing date: 2020-09-21
Publication date: 2022-03-29

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate, the substrate comprising a first region and a second region; forming a first dielectric structure on the surface of the first region and the second region; A plurality of isolation openings extending into the substrate are formed in the first dielectric structure; an isolation structure material layer is formed in the isolation opening and on the surface of the first dielectric structure; and the isolation structure material layer is etched back until all parts are exposed. On the surface of the first dielectric structure, several isolation structures are formed, and the proportion of the first area is different from that of the second area; a second dielectric structure is formed on the surface of the first dielectric structure and the several isolation structures, and the surface of the second dielectric structure is higher than the surface of the first dielectric structure, and the material of the second dielectric structure is different from the material of the isolation structure. Thus, the performance and reliability of the semiconductor structure are improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the increase of integration level of semiconductor devices and the shrinking of critical dimensions of transistors, the design of three-dimensional structures such as Fin field effect transistors (Fin FETs) becomes a focus of attention in the art. The fin field effect transistor is an emerging multi-gate device and generally comprises a plurality of thin fins extending upwards and vertically from a substrate, channels of the fin field effect transistor are formed in the fins, a gate structure is formed on the fins, active regions and drain regions are formed in the fins on two sides of the gate structure, and adjacent fins are isolated through isolation structures.

With the continuous miniaturization of devices, in order to manufacture smaller and respectively denser fin portions, a new technology for manufacturing an isolation structure has appeared, for example, a manufacturing technology of a single diffusion isolation structure (SDB isolation structure) which is generally distributed in a length direction along the fin portion, and by removing some regions of the fin portion, one or more isolation trenches are formed in the fin portion, and after insulating materials such as silicon dioxide are filled in the trenches, the fin portion can be divided into a plurality of small fin portions, so that leakage current between two adjacent fin portions can be prevented, and bridging (source-drain bridge) between a source region and a drain region formed in the fin portion can also be avoided.

However, the performance and reliability of semiconductor devices still remain to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance and the reliability of the semiconductor structure.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; a first dielectric structure located on the surface of the first and second regions; a plurality of isolation openings in the first dielectric structure extending into the substrate; the isolation structures are positioned in the isolation openings, the surfaces of the isolation structures are lower than or level to the surface of the first medium structure, and the first area proportion is different from the second area proportion, the first area proportion is the proportion of the projection area of the isolation structures on the first area on the surface of the substrate to the substrate area of the first area, and the second area proportion is the proportion of the projection area of the isolation structures on the second area on the surface of the substrate to the substrate area of the second area; and the second medium structure is positioned on the surfaces of the first medium structure and the plurality of isolation structures, the surface of the second medium structure is higher than the surface of the first medium structure, and the material of the second medium structure is different from that of the isolation structures.

Optionally, the material of the first dielectric structure includes silicon oxide, and the material of the second dielectric structure includes silicon oxide.

Optionally, the material of the isolation structure includes silicon nitride.

Optionally, the method further includes: and the sacrificial layer is positioned on the surface of the second medium structure.

Optionally, the substrate includes a base and a plurality of fin structures located on the base and separated from each other, and the isolation structure further penetrates through the fin structures and extends into the base.

Optionally, the method further includes: and the isolation structures penetrate through at least 1 grid structure in the direction vertical to the extension direction of the grid structures.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate comprising a first region and a second region; forming a first medium structure on the surfaces of the first area and the second area; forming a plurality of isolation openings in the first dielectric structure, wherein the isolation openings extend into the substrate; forming a layer of isolating structure material in the isolating opening and on the surface of the first dielectric structure; etching back the isolation structure material layer until the surface of the first medium structure is exposed to form a plurality of isolation structures, wherein the proportion of a first area is different from that of a second area, the proportion of the first area is the proportion of the projection area of the isolation structures on the first area on the surface of the substrate to the area of the substrate of the first area, and the proportion of the second area is the proportion of the projection area of the isolation structures on the second area on the surface of the substrate to the area of the substrate of the second area; and forming a second medium structure on the surfaces of the first medium structure and the plurality of isolation structures, wherein the surface of the second medium structure is higher than the surface of the first medium structure, and the material of the second medium structure is different from that of the isolation structures.

Optionally, the method further includes: forming a sacrificial layer on the surface of the second medium structure; and flattening the sacrificial layer until the surface of the second medium structure is exposed.

Optionally, the method further includes: and after the isolation structure is formed and before the second dielectric structure is formed, continuing to etch back the isolation structure until the surface of the isolation structure is lower than the surface of the first dielectric structure.

Optionally, the method further includes: and flattening the second medium structure at the same time of or after the sacrifice layer is flattened until the surface of the second medium structure is lower than the bottom surface of the sacrifice layer or until the surface of the first medium structure is exposed.

Optionally, the material of the isolation structure includes silicon nitride.

Optionally, the material of the sacrificial layer includes silicon nitride.

Optionally, the process for forming the second dielectric structure includes: an atomic layer deposition process, or a combination of a flowable chemical vapor deposition process and an annealing process.

Optionally, the substrate includes a base and a plurality of fin structures located on the bases of the first region and the second region, the fin structures located on the first region further penetrate through the fin structures of the first region and extend into the base of the first region, and the isolation structures located on the second region further penetrate through the fin structures of the second region and extend into the base of the second region.

Optionally, the method further includes: before the isolation structures are formed, a plurality of grid structures crossing the fin structures are formed on the surface of the substrate, and in the vertical direction of the extension direction of the grid structures, the isolation structures penetrate through at least 1 grid structure.

Optionally, the forming method of the first dielectric structure includes: forming a lower first dielectric layer on the surface of the substrate, wherein the lower first dielectric layer is also positioned on the side wall surface of the grid structure; forming a middle layer first dielectric layer on the surface of the lower layer first dielectric layer and the top surface of the grid structure; and forming an upper first dielectric layer on the surface of the middle first dielectric layer.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the isolation structure material layer is etched back until the surface of the first medium structure is exposed to form a plurality of isolation structures, and the second medium structure which is different from the isolation structures in material and has a surface higher than the surface of the first medium structure is formed on the surfaces of the first medium structure and the isolation structures, so that on one hand, after the isolation opening is filled, the height difference of the surface of the isolation structure material layer on the isolation opening is reduced through the etching back, and therefore, the height difference transmitted to the surface of the second medium structure is smaller, further, the surface flatness of the semiconductor structure is improved, and the consistency of the thickness of the first medium structure and the thickness of the second medium structure in the first area and the second area is improved. On the other hand, when a sacrificial layer for buffering in the planarization process is formed on the surface of the second dielectric structure and the sacrificial layer is planarized later for better improving the planarity of the surface of the semiconductor structure, because the height difference of the surface of the second medium structure on the isolation opening is smaller, the sacrificial layer in the recess of the surface of the second medium structure formed by the height difference is less, so that the planarization process can be stopped more easily on the surface of the second medium structure in the first region or the second region, thereby reducing the height difference between the surface of the semiconductor structure in the first region and the surface of the semiconductor structure in the second region, improving the surface flatness of the semiconductor structure, and the consistency of the thickness of the first dielectric structure and the thickness of the second dielectric structure of the first region and the second region is improved, and further, the performance and the reliability of the semiconductor structure are improved.

Drawings

FIGS. 1-3 are schematic cross-sectional views of steps in a method of forming a semiconductor structure;

fig. 4 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background, the performance and reliability of the semiconductor devices in the prior art still remain to be improved. The analysis will now be described with reference to specific examples.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 to 3 are schematic cross-sectional views of steps of a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided, the substrate includes a first region I and a second region II, and the substrate 100 has a plurality of fin structures 101 separated from each other; forming a plurality of gate structures 110 and a dielectric structure 120 surrounding the gate structures 110 on the surface of the substrate 100, wherein the gate structures 110 cross over the fin structure 101, and the dielectric structure 120 is made of silicon oxide; an isolation opening 121 is formed in the dielectric structure 120 of the second region II, and in a direction perpendicular to the extending direction of the gate structure 110, the isolation opening 121 penetrates through the gate structure 110, and the isolation opening 121 further penetrates through the fin structure 101 of the second region II and extends into the substrate 100.

Referring to fig. 2, an isolation structure material layer 130 is formed in the isolation opening 121 and on the surface 122 of the dielectric structure 120, wherein the isolation structure material layer 130 is made of silicon nitride; a sacrificial layer 140 is formed on the surface of the isolation structure material layer 130, the sacrificial layer 140 provides a sacrificial margin for a planarization process for the subsequent planarization isolation structure material layer 130, and the sacrificial layer 140 is made of silicon nitride.

Referring to fig. 3, the sacrificial layer 140 and the isolation structure material layer 130 are planarized until the surface 122 of the dielectric structure 120 is exposed, so as to form an isolation structure 131 and provide a planar semiconductor structure surface for the subsequent formation process.

In the above embodiment, in the process of planarizing the sacrificial layer 140 and the isolation structure material layer 130, the Inhibitor (Inhibitor) in the polishing slurry can form a continuous and dense protective layer on the surface of the dielectric structure 120, so that the planarization process is stopped when the dielectric structure 120 is exposed. The larger the area fraction of the surface 122 of the dielectric structure 120, the easier it is to form the protective layer on the surface 122 of the dielectric structure 120, and thus the easier it is for the planarization process of the sacrificial layer 140 and the isolation structure material layer 130 to stop on the surface 122 of the dielectric structure 120.

However, since the isolation structures 131 are formed in the second region II and the isolation structures 131 are not formed in the first region I, the ratio of the area of the surface 122 of the dielectric structure 120 in the first region I to the total area of the surface of the first region I is larger than that in the second region II, so that the process of planarizing the sacrificial layer 140 and the isolation structure material layer 130 is easier to stop at the surface 122 of the dielectric structure 120 in the first region I and harder to stop at the surface 122 of the dielectric structure 120 in the second region II, resulting in a height difference between the surface of the semiconductor structure in the first region I and the surface of the semiconductor structure in the second region II.

Furthermore, in order to fill the isolation opening 121 of the second region II to form the isolation structure 131, the surface of the isolation structure material layer 130 of the second region II (shown as region a) and the surface of the sacrificial layer 140 of the second region II (shown as region B) are recessed, and the recessed portions are transferred downward when the sacrificial layer 140 and the isolation structure material layer 130 are planarized, so that the surface area of the isolation structure 131 exposed by the surface 122 of the second region II dielectric structure 120 is increased, thereby increasing the ratio of the area of the surface 122 of the first region I to the total area of the surface of the first region I and the difference between the area of the surface 122 of the second region II and the total area of the surface of the second region II, resulting in further increasing the height difference between the surface of the semiconductor structure of the first region I and the surface of the semiconductor structure of the second region II after the planarization.

Because the height difference exists between the surface of the semiconductor structure of the first area I and the surface of the semiconductor structure of the second area II, the consistency of the subsequent etching process for the first area I and the second area II is poor, and the pattern precision of the illumination layer formed on the surface of the semiconductor structure is poor, thereby causing the performance and the reliability of the semiconductor device to be poor.

In order to solve the technical problem, the invention provides a method for forming a semiconductor device, which includes etching back the isolation structure material layer until the surface of the first dielectric structure is exposed to form a plurality of isolation structures, then forming second dielectric structures on the surfaces of the first dielectric structure and the isolation structures, wherein the surface of the second dielectric structure is higher than the surface of the first dielectric structure, and the material of the second dielectric structure is different from that of the isolation structures, so that the performance and the reliability of the semiconductor structure are improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 4, a substrate is provided, the substrate including a first region I and a second region II.

In this embodiment, the substrate further includes a base 200, and a plurality of fin structures 201 located on the base 200 of the first region I and the second region II and separated from each other.

The material of the substrate comprises a semiconductor material.

In this embodiment, the substrate is made of silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

In this embodiment, before the gate structure is formed subsequently, an isolation dielectric layer 210 is formed on the surface of the substrate 200. The isolation dielectric layer 210 can insulate the adjacent fin structures 201 and the substrate 200 from other subsequently formed semiconductor devices.

And then, forming a first medium structure on the surfaces of the first region I and the second region II.

In this embodiment, the first dielectric structure includes: a lower first dielectric layer on the surface of the substrate 200, a middle first dielectric layer on the surface of the lower first dielectric layer, and an upper first dielectric layer on the surface of the middle first dielectric layer. Please refer to fig. 5 to 6 for a process of forming the first dielectric structure.

Referring to fig. 5, a lower first dielectric layer 231 is formed on the surface of the substrate 200.

In the present embodiment, the process for forming the lower first dielectric layer 231 includes at least one of a spin coating process, an oxidation process and a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

In this embodiment, the material of the lower first dielectric layer 231 includes silicon oxide.

In this embodiment, after the lower first dielectric layer 231 is formed, and before the subsequent formation of the intermediate first dielectric layer, a plurality of gate structures 220 crossing the fin structure 201 are formed on the surface of the substrate 200.

In this embodiment, the method for forming the gate structure 220 includes: before forming the lower first dielectric layer 231, forming a plurality of dummy gate structures (not shown) crossing the fin structures 201 on the surface of the substrate 200; after the dummy gate structure is formed, forming the lower first dielectric layer 231 on the surface of the substrate 200, wherein the lower first dielectric layer 231 covers the side wall surface of the dummy gate structure; removing the dummy gate structure, and forming a plurality of gate openings (not shown) in the lower first dielectric layer 231; forming a gate structure material layer in the gate opening and on the surface of the lower first dielectric layer 231; the gate structure material layer is planarized until the lower first dielectric layer 231 is exposed, and a plurality of gate structures 220 are formed in the gate openings.

In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) located on an inner wall surface of the gate opening; a work function layer (not shown) on the surface of the gate dielectric layer; and a gate electrode layer (not shown) located on the surface of the work function layer and filling the gate opening.

In the present embodiment, the material of the gate dielectric layer includes a high dielectric constant material (dielectric constant greater than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.

In this embodiment, the material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

In this embodiment, the material of the gate electrode layer includes a metal material, for example: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.

In this embodiment, the method for forming the dummy gate structure includes: forming a pseudo-gate material film covering the surface of the fin structure 201 on the substrate 200; and patterning the pseudo-gate material film until the surface of the substrate 200 is exposed, and forming a pseudo-gate structure crossing the fin structure 201 on the substrate 200, wherein the top surface of the pseudo-gate structure is higher than that of the fin structure 201.

In this embodiment, the method for forming a semiconductor structure further includes: after the dummy gate structure is formed and before the lower first dielectric layer 231 is formed, source-drain doped layers (not shown in the figure) are formed in the fin structures 201 on two sides of the dummy gate structure.

The forming method of the source-drain doping layer comprises the following steps: forming source and drain openings (not shown in the figure) in the fin structure 201 on two sides of the dummy gate structure; and forming a source-drain doped layer in the source-drain opening by adopting an epitaxial process.

In other embodiments, the method of forming the gate structure includes: forming a grid structure material layer covering the surface of the fin structure on the substrate; and patterning the grid structure material layer until the surface of the substrate is exposed, and forming a grid structure crossing the fin structure on the substrate, wherein the grid structure is made of polysilicon. And after the grid structure is formed, a lower layer first dielectric layer is formed on the surface of the substrate and the side wall surface of the grid structure.

Referring to fig. 6, after the gate structure 220 is formed, an intermediate first dielectric layer 232 is formed on the surface of the lower first dielectric layer 231 and on the top surface of the gate structure 220; an upper first dielectric layer 233 is formed on the surface of the middle first dielectric layer 232 to form a first dielectric structure 230.

In this embodiment, the process of forming the middle first dielectric layer 232 includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, the material of the middle first dielectric layer 232 includes silicon nitride.

In the present embodiment, the process of forming the upper first dielectric layer 233 includes at least one of a spin-on process and a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, the material of the upper first dielectric layer 233 includes silicon oxide.

Referring to fig. 7, isolation openings 240 are formed in the first dielectric structure 230 to extend into the substrate.

The isolation opening 240 provides space for subsequent formation of an isolation structure.

The ratio of the projected area of the isolation opening 240 on the first zone I to the substrate area of the first zone I and the ratio of the projected area of the isolation opening 240 on the second zone II to the substrate area of the second zone II are different.

Therefore, after a plurality of isolation structures are formed subsequently, the proportion of a first area is different from the proportion of a second area, the proportion of the first area is the proportion of the projection area of the isolation structure on the first area I on the substrate surface to the substrate area of the first area I, and the proportion of the second area II is the proportion of the projection area of the isolation structure on the second area II on the substrate surface to the substrate area of the second area II.

It should be noted that, in this embodiment, the first area ratio is smaller than the second area ratio, and for convenience of description, the first area I is not formed with the isolation opening 240, and the second area II is formed with a plurality of isolation openings 240 as an example. Accordingly, in this embodiment, no isolation structure is formed on the first region I, and a plurality of isolation structures are formed on the second region II.

In other embodiments, the first zone ratio may also be greater than the second zone ratio.

In other embodiments, a plurality of isolation openings and isolation structures may be formed on the first region and the second region, respectively, or a plurality of isolation openings and isolation structures may be formed on the first region, and a plurality of isolation openings and isolation structures may not be formed on the second region.

Specifically, in the present embodiment, the isolation opening 240 spans at least 1 gate structure 220, and the isolation opening 240 penetrates through the fin structure 201 and extends into the substrate 200.

In this embodiment, the method for forming the isolation opening 240 includes: forming an isolation opening mask layer (not shown) on the surface of the first dielectric structure 230, wherein the isolation opening mask layer exposes the surface of the upper first dielectric layer 233 on the partial surface of at least 1 gate structure 220; and etching the upper first dielectric layer 233, the middle first dielectric layer 232, the gate structure 220, the fin structure 201 and the substrate 200 by using the isolation opening mask layer as a mask until the isolation opening 240 is formed.

In this embodiment, the process of etching the upper first dielectric layer 233, the middle first dielectric layer 232, the gate structure 220, the fin structure 201, and the substrate 200 includes at least one of a dry etching process and a wet etching process.

Referring to fig. 8, a material layer 241 of an isolation structure is formed in the isolation opening 240 and on the surface of the first dielectric structure 230.

The layer 241 of isolation structure material provides material for the subsequent formation of isolation structures.

In the present embodiment, the process of forming the isolation structure material layer 241 includes a deposition process, such as at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In other embodiments, the process of forming the isolation structure material layer includes a spin coating process or the like.

In the present embodiment, the material of the isolation structure material layer 241 includes silicon nitride. Accordingly, the material of the subsequently formed isolation structure comprises silicon nitride.

In this embodiment, in order to fill the isolation opening 240 located in the second region II and having a larger depth, a height difference is easily generated in the isolation structure material layer 241 on the isolation opening 240 of the second region II (as shown in the area a in fig. 8).

Referring to fig. 9, the isolation structure material layer 241 is etched back until the surface of the first dielectric structure 230 is exposed, so as to form a plurality of isolation structures 242, and a first area ratio is different from a second area ratio, where the first area ratio is a ratio of a projection area of the isolation structures 242 on the first area I on the substrate surface to a substrate area of the first area I, and the second area ratio is a ratio of a projection area of the isolation structures 242 on the second area II on the substrate surface to a substrate area of the second area II.

The isolation structure 242 is formed by the back etching process, and on one hand, a buffer material layer aiming at the back etching process is not required to be formed on the surface of the isolation structure material layer 241, so that the process steps are reduced, and the manufacturing efficiency is improved. On the other hand, the stop position of the isolation structure material layer 241 during etching can be more accurately controlled, and the loss of the first dielectric structure 230 is reduced, so that the height difference between the surfaces of the first dielectric structure 230 in the first region I and the second region II is reduced, and the performance and the reliability of the semiconductor structure are improved.

In the present embodiment, the isolation structure 242 penetrates at least 1 gate structure 220 in a direction perpendicular to the extending direction of the gate structures 220.

It should be noted that, in this embodiment, since the isolation structure 242 is not formed on the first region I, the first region ratio is zero.

In the present embodiment, the isolation structure 242 located on the second region II further penetrates through the fin structure 201 of the second region II and extends into the substrate 200 of the second region II.

In other embodiments, when the isolation structure is located on the first region, the isolation structure further penetrates through the fin structure of the first region and extends into the base of the first region.

The process of etching back the isolation structure material layer 241 includes at least one of a dry etching process and a wet etching process.

In this embodiment, the isolation opening mask layer is etched back and removed while the isolation structure material layer 241 is etched back.

With continued reference to fig. 9, after the isolation structures 242 are formed and before the second dielectric structures are formed, the isolation structures 242 are etched back until the surface of the isolation structures 242 is lower than the surface of the first dielectric structures 230.

Since the etching back of the isolation structure 242 is continued until the surface of the isolation structure 242 is lower than the surface of the first dielectric structure 230, it can be ensured that the subsequently formed second dielectric structure is located in the isolation opening at the top of the isolation structure 242, and the material of the second dielectric structure at the isolation opening has a certain thickness, so that, when the second dielectric structure is subsequently planarized until the surface of the first dielectric structure 230 is exposed, it can be ensured that the surface of the isolation structure 242 is not exposed, thereby facilitating the process of planarizing the second dielectric structure to stop more easily on the surface of the first dielectric structure 230 in the first region I or the second region II.

In other embodiments, the isolation structure material layer is etched back until the surface of the first dielectric structure is exposed, and the isolation structure is not etched back after the isolation structure is formed.

In another embodiment, the isolation structure surface is flush with the first dielectric structure surface.

Referring to fig. 10, a second dielectric structure 250 is formed on the surfaces of the first dielectric structure 230 and the isolation structures 242, the surface of the second dielectric structure 250 is higher than the surface of the first dielectric structure 230, and the material of the second dielectric structure 250 is different from the material of the isolation structures 242.

The isolation structure material layer 241 is etched back until the surface of the first dielectric structure 230 is exposed to form a plurality of isolation structures 242, and the second dielectric structures 250 which are different from the isolation structures 242 and have surfaces higher than the surface of the first dielectric structure 230 are formed on the surfaces of the first dielectric structure 230 and the plurality of isolation structures 242, so that, on one hand, after the isolation opening 240 is filled with the isolation structures 230, the height difference of the surface of the isolation structure material layer 241 on the isolation opening 240 is reduced through the etch back, and therefore, the height difference transmitted to the surface of the second dielectric structure 250 is smaller, and further, the surface flatness of the semiconductor structure is improved, and the consistency of the thickness of the first dielectric structure 230 and the thickness of the second dielectric structure 250 of the first region I and the second region II is improved.

On the other hand, when a sacrificial layer for buffering in the planarization process is formed on the surface of the second dielectric structure 250 and planarized later for better improving the planarity of the surface of the semiconductor structure, because the level difference of the surface of the second dielectric structure 250 on the isolation opening 240 is smaller, there is less sacrificial layer in the recess (not shown) formed by the level difference on the surface of the second dielectric structure 250, so that the planarization process can be stopped more easily on the surface of the second dielectric structure 250 in the first region I or the second region II, therefore, the height difference between the surface of the semiconductor structure in the first region I and the surface of the semiconductor structure in the second region II is reduced, the surface flatness of the semiconductor structure is improved, and the consistency of the thickness of the first dielectric structure 230 and the thickness of the second dielectric structure 250 in the first region I and the second region II is improved.

Due to the fact that the surface flatness of the semiconductor structure is improved, and the consistency of the thicknesses of the first dielectric structure 230 and the second dielectric structure 250 of the first area I and the second area II is improved, the consistency of the subsequent etching process of the first area I and the second area II is improved, the pattern precision of an illumination layer formed on the surface of the semiconductor structure is improved, and therefore the performance and the reliability of the semiconductor structure are improved.

In the present embodiment, the material of the second dielectric structure 250 includes silicon oxide.

In the present embodiment, the process for forming the second dielectric structure 250 includes a flow chemical vapor deposition process (FCVD) and an annealing process.

By adopting the flowable chemical vapor deposition process, the flowability of the material of the second dielectric structure 250 can be improved when the second dielectric structure 250 is formed, so that the surface flatness of the second dielectric structure 250 in the first region I and the second region II can be better improved, and the performance and reliability of the semiconductor structure are improved.

The annealing process is a low-temperature annealing process, and the temperature range of the low-temperature annealing process is 200-700 ℃.

Due to the adoption of the low-temperature annealing process with lower temperature, namely the annealing process with the temperature range of 200-700 ℃, the influence of the annealing process on the work function layer material of the gate structure 220 is reduced, and the influence on the electrical property of a semiconductor structure device is reduced.

In other embodiments, the process of forming the second dielectric structure 250 comprises an atomic layer deposition process.

Referring to fig. 11, a sacrificial layer 260 is formed on the surface of the second dielectric structure 250.

The sacrificial layer 260 serves as a buffer layer in a subsequent planarization process.

In the present embodiment, the process of forming the sacrificial layer 260 includes a deposition process, such as at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In other embodiments, the process of forming the sacrificial layer is a spin-on process.

In this embodiment, the material of the sacrificial layer 260 is silicon nitride.

Because silicon nitride is used as the material of the sacrificial layer 260, on one hand, when the sacrificial layer 260 is subsequently planarized, the polishing slurry of the planarization process can remove the sacrificial layer 260 more quickly, so as to improve the process efficiency of the semiconductor structure; on the other hand, the planarization process can have a larger polishing rate difference between the sacrificial layer 260 and the second dielectric structure 250, so that it is easier to stop on the surface of the second dielectric structure 250, thereby improving the precision of the planarization process and improving the performance and reliability of the semiconductor structure.

Referring to fig. 12, the sacrificial layer 260 is planarized until the surface of the second dielectric structure 250 is exposed.

In this embodiment, the process of planarizing the sacrificial layer 260 includes a chemical mechanical polishing process. In the chemical mechanical polishing process, the polishing rate ratio of the sacrificial layer 260 to the second dielectric structure 250 is greater than 5: 1.

In the present embodiment, after the sacrificial layer 260 is planarized, the second dielectric structure 250 is planarized until the surface of the first dielectric structure 230 is exposed.

In other embodiments, the second dielectric structure is planarized while or after planarizing the sacrificial layer until the second dielectric structure surface is below the sacrificial layer bottom surface.

In another embodiment, the second dielectric structure is not planarized while or after planarizing the sacrificial layer.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 11, including: a substrate comprising a first region I and a second region II; a first dielectric structure 230 located at the surface of said first region I and second region II; a number of isolation openings 240 (shown in fig. 7) extending into the substrate within the first dielectric structure 230; a plurality of isolation structures 242 located in the isolation opening 240, wherein the surface of the isolation structures 242 is lower than or level with the surface of the first dielectric structure 230, and a first region ratio is different from a second region ratio, the first region ratio is a ratio of a projected area of the isolation structures 242 on the first region I on the substrate surface to a substrate area of the first region I, and the second region ratio is a ratio of a projected area of the isolation structures 242 on the second region II on the substrate surface to a substrate area of the second region II; and a second dielectric structure 250 located on the surfaces of the first dielectric structure 230 and the isolation structures 242, wherein the surface of the second dielectric structure 250 is higher than the surface of the first dielectric structure 230, and the material of the second dielectric structure 250 is different from the material of the isolation structures 242.

The material of the substrate comprises a semiconductor material.

In this embodiment, the substrate is made of silicon.

It should be noted that, in this embodiment, the first area ratio is smaller than the second area ratio, and for convenience of description, the first area I is not formed with the isolation opening 240, and the second area II is formed with a plurality of isolation openings 240 as an example. Accordingly, in the present embodiment, there is no isolation structure 242 on the first region I, and there are several isolation structures 242 on the second region II.

In other embodiments, there may be several isolation structures on the first and second regions, respectively, or there may be several isolation structures on the first region and no several isolation openings on the second region.

In this embodiment, the semiconductor structure further includes: a plurality of gate structures 220 located on the surface of the substrate 200 and crossing the fin structures 201.

Specifically, in the present embodiment, the isolation structure 242 located on the second region II further penetrates through the fin structure 201 of the second region II and extends into the substrate 200 of the second region II.

In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown), a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.

In other embodiments, the material of the gate structure comprises polysilicon.

In this embodiment, the first dielectric structure 230 includes: a lower first dielectric layer 231 located on the surface of the substrate 200 and the sidewall surface of the gate structure 220, an intermediate first dielectric layer 232 located on the surface of the lower first dielectric layer 231 and the top surface of the gate structure 220, and an upper first dielectric layer 233 located on the surface of the intermediate first dielectric layer 232.

In the present embodiment, the material of the isolation structure 242 includes silicon nitride.

In this embodiment, the semiconductor structure further includes a sacrificial layer 260 on the surface of the second dielectric structure 250.

Specifically, in the present embodiment, the surface of the isolation structure 242 is lower than the surface of the first dielectric structure 230.

In this embodiment, the semiconductor structure further includes: an isolation dielectric layer 210 located between the substrate 200 and the first dielectric structure 230, wherein the isolation dielectric layer 210 is also located on a portion of a sidewall surface of the fin structure 201.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first region and a second region;

a first dielectric structure located on the surface of the first and second regions;

a plurality of isolation openings in the first dielectric structure extending into the substrate;

the isolation structures are positioned in the isolation openings, the surfaces of the isolation structures are lower than or level to the surface of the first medium structure, and the first area proportion is different from the second area proportion, the first area proportion is the proportion of the projection area of the isolation structures on the first area on the surface of the substrate to the substrate area of the first area, and the second area proportion is the proportion of the projection area of the isolation structures on the second area on the surface of the substrate to the substrate area of the second area;

and the second medium structure is positioned on the surfaces of the first medium structure and the plurality of isolation structures, the surface of the second medium structure is higher than the surface of the first medium structure, and the material of the second medium structure is different from that of the isolation structures.

2. The semiconductor structure of claim 1, wherein the material of the first dielectric structure comprises silicon oxide and the material of the second dielectric structure comprises silicon oxide.

3. The semiconductor structure of claim 1, in which a material of the isolation structure comprises silicon nitride.

4. The semiconductor structure of claim 1, further comprising: and the sacrificial layer is positioned on the surface of the second medium structure.

5. The semiconductor structure of claim 1, wherein the substrate comprises a base and a plurality of mutually discrete fin structures on the base, and wherein the isolation structure further extends through the fin structures and into the base.

6. The semiconductor structure of claim 6, further comprising: and the isolation structures penetrate through at least 1 grid structure in the direction vertical to the extension direction of the grid structures.

7. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a first region and a second region;

forming a first medium structure on the surfaces of the first area and the second area;

forming a plurality of isolation openings in the first dielectric structure, wherein the isolation openings extend into the substrate;

forming a layer of isolating structure material in the isolating opening and on the surface of the first dielectric structure;

etching back the isolation structure material layer until the surface of the first medium structure is exposed to form a plurality of isolation structures, wherein the proportion of a first area is different from that of a second area, the proportion of the first area is the proportion of the projection area of the isolation structures on the first area on the surface of the substrate to the area of the substrate of the first area, and the proportion of the second area is the proportion of the projection area of the isolation structures on the second area on the surface of the substrate to the area of the substrate of the second area;

and forming a second medium structure on the surfaces of the first medium structure and the plurality of isolation structures, wherein the surface of the second medium structure is higher than the surface of the first medium structure, and the material of the second medium structure is different from that of the isolation structures.

8. The method of forming a semiconductor structure of claim 7, further comprising: forming a sacrificial layer on the surface of the second medium structure; and flattening the sacrificial layer until the surface of the second medium structure is exposed.

9. The method of forming a semiconductor structure of claim 8, further comprising: and after the isolation structure is formed and before the second dielectric structure is formed, continuing to etch back the isolation structure until the surface of the isolation structure is lower than the surface of the first dielectric structure.

10. The method of forming a semiconductor structure of claim 9, further comprising: and flattening the second medium structure at the same time of or after the sacrifice layer is flattened until the surface of the second medium structure is lower than the bottom surface of the sacrifice layer or until the surface of the first medium structure is exposed.

11. The method of forming a semiconductor structure of claim 7, wherein the material of the first dielectric structure comprises silicon oxide and the material of the second dielectric structure comprises silicon oxide.

12. The method of forming a semiconductor structure of claim 7, wherein a material of the isolation structure comprises silicon nitride.

13. The method of forming a semiconductor structure of claim 8, wherein a material of the sacrificial layer comprises silicon nitride.

14. The method of forming a semiconductor structure of claim 7, wherein the process of forming the second dielectric structure comprises: an atomic layer deposition process, or a combination of a flowable chemical vapor deposition process and an annealing process.

15. The method of claim 7, wherein the substrate comprises a base and a plurality of discrete fin structures on the bases of the first and second regions, wherein the isolation structure on the first region further extends through the fin structure of the first region and into the base of the first region, and wherein the isolation structure on the second region further extends through the fin structure of the second region and into the base of the second region.

16. The method of forming a semiconductor structure of claim 14, further comprising: before the isolation structures are formed, a plurality of grid structures crossing the fin structures are formed on the surface of the substrate, and in the vertical direction of the extension direction of the grid structures, the isolation structures penetrate through at least 1 grid structure.

17. The method of forming a semiconductor structure of claim 15, wherein the method of forming the first dielectric structure comprises: forming a lower first dielectric layer on the surface of the substrate, wherein the lower first dielectric layer is also positioned on the side wall surface of the grid structure; forming a middle layer first dielectric layer on the surface of the lower layer first dielectric layer and the top surface of the grid structure; and forming an upper first dielectric layer on the surface of the middle first dielectric layer.