CN114257258B

CN114257258B - Wireless radio frequency receiver and data detection method

Info

Publication number: CN114257258B
Application number: CN202111406268.1A
Authority: CN
Inventors: 门长有; 黄益地; 夏军虎
Original assignee: Aorui Technology Co ltd; Hangzhou Vango Technologies Inc
Current assignee: Aorui Technology Co ltd; Hangzhou Vango Technologies Inc
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2023-03-31
Anticipated expiration: 2041-11-24
Also published as: CN114257258A

Abstract

The invention provides a wireless radio frequency receiver, comprising: an analog front end circuit, four analog-to-digital converters (ADCs), and a digital baseband processor. The analog front end circuit comprises a first amplifier and a second amplifier, and the digital baseband processor comprises: a digital front end circuit, a digital Low Pass Filter (LPF) and a control circuit. The digital LPF low-pass filters an output signal of the third ADC to generate a narrow-wave digital signal. The control circuit dynamically adjusts the sampling frequency of the first ADC and the second ADC, the maximum output driving current value of the first amplifier and the second amplifier and the clock frequency of the digital front-end circuit according to the difference between the energy of the output signal of the fourth ADC and the energy of the narrow-wave digital signal in an adjusting mode.

Description

Wireless radio frequency receiver and data detection method

Technical Field

The present invention relates to Radio Frequency (RF) communication systems, and more particularly, to a RF receiver and a data detection method, which can operate in a battery-powered system for a long time.

Prior Art

In a low power consumption wireless radio frequency communication system applying deep sub-micron CMOS process technology, an Intermediate Frequency (IF) is one of the most popular high performance radio frequency architectures, and since the problems of 1/f noise (flicker noise) and direct current offset (DC offset) can be significantly reduced, the IF is very suitable for a low power narrowband wireless radio frequency communication system. On the other hand, in the digital IF wireless radio frequency communication system, IF stable high performance is to be achieved, it is preferable to perform I/Q image rejection (image rejection) and Adjacent/near-channel rejection (Adjacent-near channel rejection) in the digital domain, and in order to eliminate image interference and filter out of band (OOB) interference in the digital domain, the analog-to-digital converter (ADC) and the digital front end (front) circuit are operated at the oversampling frequency and clock frequency (clock rate), which are generally about twice as high as the frequency in the Zero-IF or Direct conversion mode. However, higher sampling and clock frequencies will result in increased power consumption, which is a significant departure from the design goals of low power consumption for systems.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a radio frequency receiver, which can effectively eliminate image interference and outer band interference, and achieve the objective of low power consumption.

According to an embodiment of the present invention, a radio frequency receiver is provided, which includes an analog front end circuit, a first analog-to-digital converter (ADC), a second ADC, a third ADC, a fourth ADC, and a digital baseband processor. The analog front-end circuit comprises a frequency reduction circuit, a first analog low-pass filter, a second analog low-pass filter, a first amplifier and a second amplifier. The digital baseband processor comprises a digital front-end circuit and a detection and control module; the detection and control module comprises a digital low-pass filter and a control circuit. The frequency reducing circuit is used for reducing the frequency of a first wireless radio frequency signal into a first analog intermediate frequency signal with an in-phase and a quadrature phase; the first low-pass filter and the second low-pass filter respectively perform low-pass filtering on the in-phase and quadrature-phase first analog intermediate-frequency signals to generate in-phase and quadrature-phase filtered intermediate-frequency signals; the first amplifier and the second amplifier amplify the in-phase and quadrature-phase filtered intermediate frequency signals into in-phase and quadrature-phase second analog intermediate frequency signals, respectively; the first analog-digital converter and the second analog-digital converter respectively perform analog-digital conversion on the in-phase and quadrature-phase second intermediate-frequency analog signals to generate in-phase and quadrature-phase first digital intermediate-frequency signals; the third analog-to-digital converter and the fourth analog-to-digital converter perform analog-to-digital conversion on the in-phase and quadrature-phase first analog intermediate frequency signals respectively to generate in-phase and quadrature-phase second digital intermediate frequency signals. The digital front-end circuit is used for carrying out frequency reduction and filtering operation on the in-phase and quadrature-phase first digital intermediate frequency signals so as to generate in-phase and quadrature-phase filtering base frequency signals; the digital low-pass filter is used for performing low-pass filtering on the output signal of the third analog-digital converter to generate a narrow-wave digital signal; the control circuit dynamically adjusts the sampling frequency of the first analog-to-digital converter and the second analog-to-digital converter, the maximum output driving current value of the first amplifier and the second amplifier and the clock frequency of the digital front-end circuit according to the difference between the energy of the output signal of the fourth analog-to-digital converter and the energy of the narrow-wave digital signal in an adjustment mode.

Another embodiment of the present invention provides a data detection method for a wireless radio frequency receiver, including: (1) Down-converting the first wireless radio frequency signal into a first analog intermediate frequency signal of in-phase and quadrature phase; (2) Low-pass filtering the in-phase and quadrature-phase first analog intermediate frequency signal to generate in-phase and quadrature-phase filtered intermediate frequency signals; (3) Amplifying the in-phase and quadrature-phase filtered intermediate frequency signals into in-phase and quadrature-phase second analog intermediate frequency signals by using a first amplifier and a second amplifier respectively; (4) Respectively carrying out analog-digital conversion on the in-phase and quadrature-phase second intermediate-frequency analog signals by using a first analog-digital converter (analog-digital converter) and a second analog-digital converter to generate in-phase and quadrature-phase first digital intermediate-frequency signals; (5) Respectively carrying out analog-digital conversion on the in-phase and quadrature-phase first analog intermediate frequency signals by using a third analog-digital converter and a fourth analog-digital converter so as to generate in-phase and quadrature-phase second digital intermediate frequency signals; (6) Performing frequency reduction and filtering operation on the in-phase and quadrature-phase first digital intermediate frequency signal by using a digital front-end circuit to generate in-phase and quadrature-phase filtered fundamental frequency signals; (7) Low-pass filtering the output signal of the third analog-to-digital converter to generate a narrow-wave digital signal; (8) Dynamically adjusting the sampling frequency of the first analog-to-digital converter and the second analog-to-digital converter, the maximum output driving current value of the first amplifier and the second amplifier and the clock frequency of the digital front-end circuit according to the difference between the energy of the output signal of the fourth analog-to-digital converter and the energy of the narrow-wave digital signal; and, (9) confirming the value of a specific field in the input packet.

The foregoing and other objects and advantages of the invention will be apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings and claims.

Drawings

Fig. 1A is a diagram illustrating an architecture of a wireless bluetooth receiver, according to an embodiment of the present invention.

FIG. 1B is a block diagram of a digital baseband processor, according to one embodiment of the present invention.

Fig. 2 shows a schematic diagram of a bluetooth packet format (packet format).

Fig. 3 illustrates an example of a high energy out-of-band interferer for the intended receive channel N and its nearby channels.

Fig. 4 illustrates an example of a low energy out-of-band interference signal for the intended receive channel N and its nearby channels.

Fig. 5 is a flow chart illustrating a preamble detection method according to an embodiment of the present invention.

Detailed Description

Reference throughout the specification to "a" and "the" singular forms of words such as "a" and "the" include both the singular and the plural, unless the specification expressly indicates otherwise. In the following description and in the claims, the terms used in the following description and in the claims are defined as follows, unless the context clearly dictates otherwise. Throughout the specification, circuit components having the same functions are given the same reference symbols.

One of the features of the present invention is to use a dynamic scaling frequency and current mechanism to reduce the operating frequency of the ADC and the digital front-end circuit and the maximum driving current capability of the Programmable Gain Amplifier (PGA) when detecting a low-energy out-of-band interference signal, and to increase the operating frequency of the ADC and the digital front-end circuit and the maximum driving current capability of the PGA when detecting a high-energy out-of-band interference signal. The invention can effectively reduce the battery power consumption of the wireless radio frequency receiver by utilizing the dynamic scaling frequency and current mechanism. Another feature of the present invention is that the energy detection ADC 151I/Q with low resolution is adopted, which not only reduces power consumption, but also helps to stabilize an Automatic Gain Control (AGC) loop.

For clarity and convenience of description, the following examples and embodiments are only illustrated by way of a wireless bluetooth receiver, but the application of the present invention is not limited thereto, and other wireless rf receivers currently existing or developed in the future can also be applied to the concept of the present invention.

Fig. 1A shows an architectural diagram of a wireless bluetooth receiver, according to one embodiment of the present invention. Referring to fig. 1A, the wireless bluetooth receiver 100 of the present invention includes an antenna 180, an analog front end circuit 10, two receiving ADCs 143I/Q, two energy detection ADCs 151I/Q, and a digital baseband processor 160. The analog front-end circuit 10 includes a Low Noise Amplifier (LNA) 110, a quadrature mixer (quadrature mixer) 120, two Low Pass Filters (LPF) 141I/Q, two PGAs 142I/Q, and a frequency synthesizer (frequency synthesizer) 130. The architecture of the wireless bluetooth receiver 100 consists of a single stage front end stage, and the LNA110 and the gain stage of the quadrature mixer 120 are combined into a single stage current mode Transconductance gain (Transconductance gain).

The digital baseband processor 160 includes a digital front end circuit 161, an energy detection and control module 162, a processing unit 163, and a storage medium 164. The processing unit 163 is connected to the digital front-end circuit 161, the energy detection and control unit 162 and the storage medium (storage medium) 164, and is used for controlling the operations of the digital front-end circuit 161, the energy detection and control module 162 and the storage medium 164. The storage medium 164 can be a memory such as a DRAM, an SRAM, a Flash, etc., the storage medium 164 stores a firmware (driver), and the processing unit 163 implements the preamble detection method of fig. 5 by executing the firmware in the storage medium 164. The frequency synthesizer 130 includes a voltage-controlled oscillator (VCO) 131 and a phase-locked loop (PLL) 132. The phase locked loop 132 outputs a control voltage V according to the phase difference between the reference clock REF and the feedback clock LO _ctrl The voltage-controlled oscillator 131 is then based on the control voltage V _ctrl And generates a local oscillation signal LO. The operation is cycled until the feedback clock LO and the reference clockThe phase-locked loop 132 performs the phase-locking operation when the frequency and the phase difference of the REF are substantially the same.

The quadrature mixer 120 includes two mixers 121I to 121Q and a phase shifter 123. The lna110 sets a voltage gain according to a setting g1 on the bus BR to amplify the RF signal from the antenna 180 to a corresponding voltage level. The phase shifter 123 receives the local oscillation signal LO, and shifts the phase by 0/90 degrees to generate an in-phase (in-phase) signal LO-I and a quadrature (quadrature) signal LO-Q. The mixer 121I mixes the output signal of the low noise amplifier 110 and the in-phase signal LO-I to generate an intermediate frequency (about several MHz) in-phase signal IF-I; the mixer 121Q mixes the output signal of the low noise amplifier 110 with the quadrature phase signal LO-Q to generate a quadrature phase signal IF-Q of the intermediate frequency. Then, after the two LPFs 141I/Q low-pass filter the in-phase signal IF-I and the quadrature-phase signal IF-Q of the intermediate frequency, the two PGAs 142I/Q amplify the output signals of the two LPFs 141I/Q to the corresponding voltage levels according to their own voltage gain values (set by g2 and g3, respectively). Finally, the two receiving ADCs 143I/Q are each provided with their own default sampling frequency f _S The two analog signals P-I and P-Q output by the two PGAs 142I/Q are sampled (set by C3 and C4, respectively) to convert the two analog signals P-I and P-Q into two digital signals RD-I and RD-Q, which are sent to the digital front end circuit 161.

The two energy detection ADCs 151I/Q are used to convert the two analog intermediate frequency signals IF-I and IF-Q into two digital intermediate frequency signals ID-I and ID-Q, and transmit the two digital intermediate frequency signals ID-I and ID-Q to the energy detection and control module 162 for energy detection of the narrow band signal and the wide band signal. The resolution (resolution) or the number of bits of the two energy detection ADCs 151I/Q is lower than that of the two reception ADCs 143I/Q, so that the power consumption is also lower, but the operation speed is faster, which is an indispensable part for performing the fast AGC. In one embodiment, the number of bits of the energy detection ADC 151I/Q is equal to 6 bits, and the number of bits of the receive ADC 143I/Q is equal to 10 bits. It should be noted that the number of bits of the energy detection ADCs 151I/Q and the receiving ADCs 143I/Q is only an example, and not a limitation to the present invention, and other numbers of bits may be selected for the energy detection ADCs 151I/Q and the receiving ADCs 143I/Q in practical implementation, provided that the number of bits of the energy detection ADCs 151I/Q must be lower than that of the receiving ADCs 143I/Q. Generally, the dynamic range of the low-resolution energy detection ADC 151I/Q is about 20-40 dB, which can effectively help the RFAGC (step S506 in fig. 5) and the IFAGC (step S508 in fig. 5) to quickly reach a steady state, and thus the preamble 21 in the bluetooth packet can be successfully detected within the preamble detection time (e.g. 8 microseconds (μ S) as shown in fig. 2).

The digital baseband processor 160 has four output buses (buses) BR, BI, BQ, and BC in common. Referring to fig. 1A-1B, the AGC unit 161d of the digital front-end circuit 161 outputs a setting g1 via the bus BR to set the voltage gain of the LNA110, and outputs two setting g2 and g3 via the buses BI and BQ to set the voltage gain of the two PGAs 142I/Q, respectively. The frequency and current control unit 162C of the energy detection and control module 162 outputs two setting values C1-C2 via the bus BC to set the maximum output driving current values I of the two PGAs 142I/Q, respectively _PGA And similarly, two set values C3-C4 are outputted through the bus BC to set the sampling frequency f of the two receiving ADCs 143I/Q, respectively _S 。

The digital front-end circuit 161 includes a numerically-controlled oscillator (NCO) 161a, a filter module 161b, an energy detection unit 161c, and an AGC unit 161d. The primary function of NCO 161a is to shift the frequency of two digital intermediate frequency signals RD-I and RD-Q into two baseband signals B-I and B-Q. The filter module 161B is used for filtering the two baseband signals B-I and B-Q to filter out the out-of-band interference signal and generate two in-band signals f-I and f-Q; in one embodiment, the filter module 161B1 comprises a cascaded integrator-comb filter (not shown) cascaded low pass filter (not shown), wherein the cascaded integrator-comb filter receives the two baseband signals B-I and B-Q, and the low pass filter generates the two in-band signals f-I and f-Q. According to the formula of energy

The energy detecting unit 161c calculates the energy of the two signals RD-I and RD-Q, respectivelyDetection value Pr _I And Pr _Q Energy detection values Pf of the two signals f-I and f-Q _I And Pf _Q And energy detection values Pi of the two signals ID-I and ID-Q _I And Pi _Q Where N represents the total number of signal sample points x (N). Finally, the AGC unit 161d detects the value Pr according to the six energy detection values _I And Pr _Q 、Pf _I And Pf _Q 、Pi _I And Pi _Q Three setting values g1, g2, g3 are generated, and the voltage gain values of the LNAs 110, the PGAs 142I and the PGAs 142Q are set through three buses BR, BI, BQ, respectively.

From the circuit of FIGS. 1A-1B, the energy detection value Pi of the signal ID-I/ID-Q _I And Pi _Q The energy detection values Pr of the signals RD-I and RD-Q are only related to the magnitude of the output voltage of the LNA110 _I And Pr _Q And energy detection values Pf of the signals f-I and f-Q _I And Pf _Q It is related to the output voltage level of the LNA110 and the two PGAs 142I/Q. Therefore, after the bluetooth receiver 100 is started, first, the AGC unit 161d is based on Pi _I And Pi _Q The setting value g1 is dynamically adjusted to change the voltage gain value of the LNA110, so that the LNA110 finally operates in an operating range close to full load and the ADC 151I/Q is prevented from entering a saturation state (referred to as "RFAGC" (step S506 in fig. 5)); after the RFAGC enters the steady state or determines the setting value g1, the AGC unit 161d further detects the value Pr according to the energy _I And Pr _Q And Pf _I And Pf _Q The two setting values g 2-g 3 are dynamically adjusted to change the voltage gain values of the two PGAs 142I/Q, so that the two PGAs 142I/Q operate in the working range close to full load, and the ADC 143I/Q is prevented from entering the saturation state (referred to as "IFAGC" (step S508 in fig. 5)).

The energy detection and control module 162 includes an LPF 162a, an energy detection unit 162b, and a frequency and current control unit 162c. The LPF 162a low-pass filters the digital intermediate frequency signal ID-I to generate a filtered signal f'. Since the receiver is a wireless bluetooth receiver, the cutoff (cutoff) frequency of LPF 162a is 1M or 2M hertz (Hz); if the RF receiver of the present invention is applied to other communication bands, the cut-off of the LPF 162aThe stop frequency can be adjusted accordingly. According to the energy formula of the energy detecting unit 161c, the energy detecting unit 162b calculates the narrow-band energy detecting value Pn of the filtered signal f' and the wide-band energy detecting value Pw of the digital intermediate-frequency signal ID-Q, respectively. Finally, the frequency and current control unit 162C compares the difference between the narrow-band power detection value Pn and the wide-band power detection value Pw to dynamically adjust five setting values C1 to C5, wherein two setting values C1 to C4 are output through the bus BC to set the maximum output driving current values I of the two PGAs 142I/Q, respectively _PGA And sampling frequency f of two receiving ADCs 143I/Q _S And outputs a set value C5 to adjust the clock frequency f of the digital front-end circuit 161 _DEF . In the embodiment of fig. 1B, the LPF 162a is disposed at the output end of the ADC 151I and the energy detection unit 162B calculates the narrow-band energy detection value Pn of the filtered signal f' and the wide-band energy detection value Pw of the digital intermediate-frequency signal ID-Q, respectively, which is an example and not a limitation of the present invention. In another embodiment, the LPF 162a is disposed at the output end of the ADC 151Q, so the energy detection unit 162b can calculate the narrow-band energy detection value Pn of the output signal of the LPF 162a and the wide-band energy detection value Pw of the digital intermediate-frequency signal ID-I, respectively. In one embodiment, the two energy detection units 161 c-162 b, the frequency and current control unit 162c and the AGC unit 161d are implemented by a state machine (state machine), respectively.

In one embodiment, if the difference between the two energy detection values Pn and Pw is greater than or equal to the threshold value TH, indicating that the surrounding environment has high energy out-of-band interference signals, as shown in fig. 3, the frequency and current control unit 162C generates two corresponding setting values C1-C2 to respectively increase the maximum output driving current values of the two PGAs 142I/Q to I/Q _PGA1 And two corresponding set values C3-C4 are generated to increase the sampling frequency of the two receiving ADCs 143I/Q to f _S1 And generates a corresponding setting value C5 to increase the clock frequency of the digital front-end circuit 161 to f _DEF1 (ii) a On the contrary, if the difference between the two energy detection values Pn and Pw is smaller than the threshold value TH, which indicates that the surrounding environment has only low energy out-of-band interference signals, as shown in the example of fig. 4, the frequency and driving control module 162 generates two corresponding setting values C1-C2 to respectively reduceThe maximum output driving current value to I of two lower PGA142I/Q _PGA0 And two corresponding set values C3-C4 are generated to respectively reduce the sampling frequency of the two receiving ADCs 143I/Q to f _S0 And generates a corresponding setting value C5 to lower the clock frequency of the digital front-end circuit 161 to f _DEF0 . Wherein, I _PGA1 ＝Ni×I _PGA0 、f _S1 ＝Nf×f _S0 And f _DEF1 ＝Nf×f _DEF0 (ii) a Ni =2 or 4, and Nf =2, 4 or 8.

Fig. 2 shows a schematic diagram of a bluetooth packet format. As shown in fig. 2, the bluetooth packet includes the following four fields (fields): a preamble 21, an access address 22, a Protocol Data Unit (PDU) 23, and a Cyclic Redundancy Check (CRC) 24. Wherein, the preamble 21 includes 1 to 2 octets (octets); the access address 22 comprises 4 octets, the protocol data unit 23 comprises 2-257 octets and the CRC 24 comprises 3 octets. The preamble 21 is used for the bluetooth receiver to identify the start of the bluetooth packet for synchronization (synchronization) purpose. For example, in listening mode, the wireless bluetooth receiver 100 is enabled to detect the preamble 21. Note that the detection time D of the preamble 21 is only 8 microseconds, and the bluetooth receiver 100 must complete the reception of the RFAGC, IFAGC and the acknowledgement preamble within 8 microseconds after the start-up.

Fig. 5 shows a flow diagram of a preamble detection method according to an embodiment of the invention. Referring to fig. 5, the following describes the processing unit 163 of the wireless bluetooth receiver 100 performing the preamble detection method in the listening mode as follows.

Step S502: the wireless bluetooth receiver 100 is enabled.

Step S504: and performing initialization setting. Initialization settings include, but are not limited to, (1) initial sampling frequency f to be received by ADC 143I/Q _S0 And an initial clock frequency f of the digital front-end circuit 161 _DEF0 Set at a lower operating frequency and (2) set the initial output drive current value I of PGA142I/Q _PGA0 Set at a lower current level to save power consumption, e.g., the initial sampling frequency of the receiving ADC 143I/Qf _S0 And an initial clock frequency f of the digital front-end circuit 161 _DEF0 Set to Nyquist frequency f _NYQ 1 to 2 times of the total weight of the composition. In one embodiment, before the ADC 143I/Q, the PGA142I/Q and the digital front-end circuit 161 start to operate, the energy detection and control module 162 outputs two initial setting values C1-C2 via the bus BC to set the initial output driving current values I of the two PGAs 142I/Q, respectively _PGA0 ＝I _B0 Two initial set values C3-C4 are output through the bus BC to set the initial sampling frequency f of the two receiving ADCs 143I/Q respectively _S0 ＝2×f _NYQ And setting the initial clock frequency f of the digital front-end circuit 161 by the initial setting value C5 _DEF0 ＝2×f _NYQ . For a general Bluetooth receiver, f _S0 And f _DEF0 In the frequency range of about 4 to 6MHz, and I _B0 The current value of (a) ranges from about 50 to 100A. In addition, a flag F is set _RF Set equal to an initial value, e.g., 0.

Step S506: the voltage gain of the LNA110 is automatically gain controlled (i.e., RFAGC). Specifically, the AGC unit 161d detects the energy Pi based on the intermediate frequency signals ID-I and ID-Q _I And Pi _Q The setting g1 is dynamically adjusted to change the voltage gain value of the LNA110, eventually causing the LNA110 to operate in a nearly full operating range and preventing the ADC 151I/Q from entering a saturation state. Note that the RFAGC must reach a steady state within 2 microseconds (about 1/4 × D, where D represents the total length of the preamble detection time, as shown in fig. 2) after the wireless bluetooth receiver 100 is powered on. When the RFAGC reaches the steady state, the system will use the flag F _RF Set to a state value (different from the initial value described above), e.g., 1.

Step S507: judgment flag F _RF Is set to the state value 1. If yes, the RFAGC reaches a stable state, and the step S508 is skipped; otherwise, it indicates that the RFAGC has not reached the stable state, and returns to step S506.

Step S508: the voltage gain of the PGA142I/Q is automatically gain controlled (i.e., IFAGC). When the process proceeds to this step, the setting value g1 and the voltage gain value of the LNA110 are fixed, and the AGC unit 161d detects the gain according to the energyMeasured value Pf _I And Pr _I Dynamically adjusting the setting value g2 to change the voltage gain value of the PGA142I, so that the PGA142I operates in a working range close to full load, and the ADC 143I is prevented from entering a saturation state; in addition, the AGC unit 161d also detects the value Pf according to the energy _Q And Pr _Q The setting value g3 is dynamically adjusted to change the voltage gain value of the PGA142Q, so that the PGA142Q operates in a working range close to full load, and the ADC 143Q is prevented from entering a saturation state. Note that the IFAGC should reach a steady state within 3 microseconds (or about (3/8) × D) after the RFAGC ends.

Step S510: the ADC 151I/Q, LPF 162a, and power detection unit 162b are used to detect the power of in-band and out-of-band signals. Referring to fig. 1A-1B, the digitally filtered signal f' is a narrowband signal (the analog IF-I signal is generated by the ADC 151I and the LPF 162 a) compared to the digital signal ID-Q being a wideband signal (the analog IF-Q signal is generated by the ADC 151Q and is not filtered at all). According to the above energy formula, the energy detection unit 162b calculates the narrow band energy detection value Pn of the filtered signal f' and the wide band energy detection value Pw of the digital intermediate frequency signal ID-Q, respectively. This step is performed simultaneously with step S506, i.e., the energy detection of the in-band and out-of-band signals is performed simultaneously when performing the RFAGC.

Step S511: judgment flag F _RF Is set to the state value 1. If yes, the RFAGC reaches a stable state, and the step S512 is skipped; otherwise, it indicates that the rf agc has not reached the stable state, and returns to step S510.

Step S512: it is determined whether the difference between the two energy detection values Pw and Pn (i.e., (Pw-Pn)) is greater than or equal to a threshold value TH. If yes, indicating that the surrounding environment has a high-energy out-of-band interference signal, and jumping to step S514; otherwise, it indicates that there is no out-of-band interference signal with high energy in the surrounding environment, and the step S516 is skipped without changing the initial setting values C1 to C5 of step S504. It should be noted that the threshold TH is programmable and adjustable, and is set to 3dB at initialization, which means that the out-of-band energy detection value is 2 times the in-band energy detection value. It should be noted that after the RFAGC reaches the steady state (i.e. the flag F) _RF Set to the above state value 1) within 1 microsecond (or about (1/8) × D), this step must be completed to confirm whether there is a high-energy out-of-band interferer in the surrounding environment.

Step S514: the sampling frequency of the ADC 143I/Q, the clock frequency of the digital front-end circuit 161, and the maximum amount of output drive current of the PGA142I/Q are increased. In order to accommodate the out-of-band interference signal, the sampling frequency of the receiving ADC 143I/Q and the clock frequency of the digital front-end circuit 161 need to be increased, so that the filter module 161b operates at a higher clock frequency to filter the out-of-band interference signal, and in addition, the maximum output driving current of the PGA142I/Q needs to be increased in response to the increase of the sampling frequency of the ADC 143I/Q. In one embodiment, the frequency and current control unit 162C modifies the two setting values C1C 2 to increase the maximum output driving current value I of the two PGAs 142I/Q, respectively _PGA1 ＝2×I _B0 Correcting two set values C3-C4 to respectively increase the sampling frequency f of two receiving ADCs 143I/Q _S1 ＝16×f _NYQ And correcting the setting value C5 to increase the clock frequency f of the digital front-end circuit 161 _DEF1 ＝16×f _NYQ Wherein the sampling frequency f is _S1 And clock frequency f _DEF1 In the range of about 32 to 48MHz, and I _PGA1 In the range of about 100 to 200A. Since the preamble detection time is limited, the step S514 must be completed within 2 μ S, which includes (1) setting the time of the ADC 143I/Q, the digital front-end circuit 161, and the PGA142I/Q with the correction values C1 to C5, and (2) reaching the steady state after the PGA 142I/142Q, the digital front-end circuit 161, and the ADC 143I/143Q are set. In addition, according to fig. 2, the steps S508 and S514 are performed within 5 microseconds (or about (5/8) × D) after the wireless bluetooth receiver 100 is activated (step S502).

Step S516: the value of the preamble is confirmed. Since the preamble detection time is limited, the step S516 must be completed within 3 microseconds (or about (3/8) × D) after the end of the steps S508 and S514. The process is terminated after the completion of this step.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; it is intended that all such equivalent changes and modifications be included within the scope of the present disclosure without departing from the spirit thereof.

Claims

1. A wireless radio frequency receiver, comprising:

an analog front end circuit comprising:

the frequency reduction circuit is used for converting the first wireless radio frequency signal into a first analog intermediate frequency signal with an in-phase and a quadrature phase;

a first analog low-pass filter and a second analog low-pass filter, which respectively perform low-pass filtering on the in-phase and quadrature-phase first analog intermediate frequency signals to generate in-phase and quadrature-phase filtered intermediate frequency signals; and

a first amplifier and a second amplifier for amplifying the in-phase and quadrature-phase filtered intermediate frequency signals into in-phase and quadrature-phase second analog intermediate frequency signals, respectively;

a first analog-to-digital converter and a second analog-to-digital converter, which respectively perform analog-to-digital conversion on the in-phase and quadrature-phase second intermediate-frequency analog signals to generate in-phase and quadrature-phase first digital intermediate-frequency signals;

a third analog-to-digital converter and a fourth analog-to-digital converter for performing analog-to-digital conversion on the in-phase and quadrature-phase first analog intermediate frequency signals, respectively, to generate in-phase and quadrature-phase second digital intermediate frequency signals; and

a digital baseband processor, comprising:

the digital front-end circuit is used for carrying out frequency reduction and filtering operation on the in-phase and quadrature-phase first digital intermediate frequency signals so as to generate in-phase and quadrature-phase filtering base frequency signals; and

the detection and control module comprises:

a digital low-pass filter for low-pass filtering the output signal of the third analog-to-digital converter to generate a narrow-band digital signal; and

a control circuit for controlling the second ADC to convert the energy of the output signal of the second ADC into the energy of the narrow-band digital signal,

and dynamically adjusting the sampling frequency of the first analog-digital converter and the second analog-digital converter, the maximum output driving current value of the first amplifier and the second amplifier and the clock frequency of the digital front-end circuit.

2. The wireless radio frequency receiver of claim 1, wherein the first and second analog-to-digital converters have a greater number of bits than the third and fourth analog-to-digital converters.

3. The wireless radio frequency receiver of claim 1,

when the difference is smaller than a critical value, the control circuit sets the sampling frequency of the first analog-digital converter and the second analog-digital converter as a first sampling frequency, sets the maximum output driving current value of the first amplifier and the second amplifier as a first current value and sets the clock frequency of the digital front-end circuit as a first clock frequency;

when the difference is greater than or equal to the critical value, the control circuit sets the sampling frequency of the first analog-digital converter and the second analog-digital converter as a second sampling frequency, sets the maximum output driving current value of the first amplifier and the second amplifier as a second current value and sets the clock frequency of the digital front-end circuit as a second clock frequency;

the second sampling frequency is greater than the first sampling frequency, the second current value is greater than the first current value, and the second clock frequency is greater than the first clock frequency.

4. The wireless rf receiver of claim 1, wherein the analog front-end circuit further comprises a third amplifier, an output of the third amplifier being connected to an input of the frequency down-conversion circuit for amplifying a second wireless rf signal from an antenna into the first wireless rf amplified signal; wherein, the digital front-end circuit includes:

and an automatic gain control unit for performing automatic gain control on the voltage gain of the third amplifier according to the energy of the in-phase and quadrature-phase second digital intermediate frequency signals in the first mode.

5. The wireless radio frequency receiver of claim 4, wherein the digital front end circuit further comprises:

a digital controlled oscillator for down-converting the in-phase and quadrature-phase first digital intermediate frequency signals into the in-phase and quadrature-phase baseband signals; and

a filter module for filtering the in-phase and quadrature-phase baseband signals to generate in-phase and quadrature-phase filtered baseband signals;

the automatic gain control unit performs automatic gain control on the voltage gain of the first amplifier and the voltage gain of the second amplifier according to the energy of the first digital intermediate frequency signal in the in-phase and the quadrature phase and the energy of the filtered baseband signal in the in-phase and the quadrature phase in a second mode, wherein the second mode is performed after the first mode.

6. The radio frequency receiver of claim 5, wherein the detection and control module further comprises:

an energy detection unit for detecting the energy of the output signal of the fourth adc and the energy of the narrow-band digital signal in an estimation mode;

the control circuit determines the difference between the energy of the output signal of the fourth analog-digital converter and the energy of the narrow-wave digital signal in a judgment mode; and

wherein the determining mode is performed after the estimating mode and the first mode.

7. The RF receiver of claim 6 wherein the RF receiver is a wireless Bluetooth receiver, and the first mode and the estimation mode are simultaneously enabled when detecting a preamble of a Bluetooth packet in the listening mode, the determination mode is entered to determine the difference between the energy of the output signal of the fourth ADC and the energy of the narrow-band digital signal within a first predetermined time after the third amplifier reaches a steady state, the second mode and the adjustment mode are completed within a second predetermined time, and the value of the preamble of the Bluetooth packet is determined within a third predetermined time.

8. The radio receiver of claim 7 wherein the first predetermined time is equal to (1/8) xD, the second predetermined time is (5/8) xD after the radio receiver is powered on, and the third predetermined time is (3/8) xD after the second mode and the tuning mode are completed, wherein D represents a total detection time length of the preamble of the Bluetooth packet.

9. A data detection method is suitable for a wireless radio frequency receiver, and the method comprises the following steps:

(1) Down-converting a first wireless radio frequency signal into a first analog intermediate frequency signal with an in-phase and a quadrature phase;

(2) Low-pass filtering the in-phase and quadrature-phase first analog IF signal to generate in-phase and quadrature-phase filtered IF signals;

(3) Amplifying the in-phase and quadrature-phase filtered intermediate frequency signals into in-phase and quadrature-phase second analog intermediate frequency signals by using a first amplifier and a second amplifier respectively;

(4) Respectively carrying out analog-digital conversion on the in-phase and quadrature-phase second intermediate-frequency analog signals by using a first analog-digital converter and a second analog-digital converter so as to generate in-phase and quadrature-phase first digital intermediate-frequency signals;

(5) Respectively carrying out analog-digital conversion on the in-phase and quadrature-phase first analog intermediate frequency signals by using a third analog-digital converter and a fourth analog-digital converter so as to generate in-phase and quadrature-phase second digital intermediate frequency signals;

(6) Performing frequency reduction and filtering operation on the in-phase and quadrature-phase first digital intermediate frequency signal by using a digital front-end circuit to generate in-phase and quadrature-phase filtering base frequency signals;

(7) Low-pass filtering the output signal of the third analog-to-digital converter to generate a narrow-wave digital signal;

(8) Dynamically adjusting the sampling frequency of the first analog-to-digital converter and the second analog-to-digital converter, the maximum output driving current value of the first amplifier and the second amplifier and the clock frequency of the digital front-end circuit according to the difference between the energy of the output signal of the fourth analog-to-digital converter and the energy of the narrow-wave digital signal; and

(9) The value of a specific field in the incoming packet is confirmed.

10. The method of claim 9, wherein prior to step (1), further comprising:

(a) And amplifying a second radio frequency signal from an antenna into the first radio frequency amplified signal through the third amplifier.

11. The method of claim 10, wherein before step (8) and after step (7), further comprising:

(b) Performing automatic gain control on the voltage gain of the third amplifier according to the energy of the in-phase and quadrature-phase second digital intermediate frequency signals; and

(c) Detecting the energy of the output signal of the fourth analog-digital converter and the energy of the narrow-wave digital signal;

wherein, the step (b) and the step (c) are started to be executed simultaneously.

12. The method of claim 11, wherein prior to steps (3), (4) and (5), further comprising:

(d) Setting the sampling frequency of the first analog-digital converter and the second analog-digital converter, the output driving current value of the first amplifier and the second amplifier and the initial value of the clock frequency of the digital front-end circuit.

13. The method of claim 11, wherein after step (b), further comprising:

(e) And performing automatic gain control on the voltage gains of the first amplifier and the second amplifier according to the energy of the output signals of the first analog-digital converter and the second analog-digital converter and the energy of the in-phase and quadrature-phase filtered baseband signals.

14. The method of claim 13, wherein after steps (b) and (c) and before step (8), further comprising:

(f) An amount of difference between the energy of the output signal of the fourth analog-to-digital converter and the energy of the narrow-wave digital signal is determined.

15. The method of claim 14 wherein the RF receiver is a Bluetooth wireless receiver, the incoming packet is a Bluetooth packet, the specific field is a preamble, wherein step (f) is performed within a first predetermined time after the third amplifier of step (b) reaches steady state, and wherein steps (e) and (8) are performed within a second predetermined time and step (9) is performed within a third predetermined time.

16. The method of claim 15, wherein the first predetermined time is equal to (1/8) xd, the second predetermined time is (5/8) xd after the radio frequency receiver is powered on, and the third predetermined time is (3/8) xd after steps (e) and (8) are completed, where D represents a total detection time of the preamble of the bluetooth packet.

17. The method of claim 9, wherein the first and second adcs have a higher bit count than the third and fourth adcs.

18. The method of claim 9, wherein step (8) further comprises:

when the difference is smaller than a critical value, setting the sampling frequency of the first analog-digital converter and the second analog-digital converter to be equal to a first sampling frequency, the maximum output driving current value of the first amplifier and the second amplifier to be equal to a first current value and the clock frequency of the digital front-end circuit to be equal to a first clock frequency; and

when the difference is greater than or equal to the critical value, setting the sampling frequency of the first analog-digital converter and the second analog-digital converter to be equal to a second sampling frequency, the maximum output driving current value of the first amplifier and the second amplifier to be equal to a second current value and the clock frequency of the digital front-end circuit to be equal to a second clock frequency;