CN114267741A

CN114267741A - Trench gate semiconductor device and manufacturing method thereof

Info

Publication number: CN114267741A
Application number: CN202010972194.7A
Authority: CN
Inventors: 卢汉汉; 吴海平
Original assignee: BYD Semiconductor Co Ltd
Current assignee: BYD Semiconductor Co Ltd
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2022-04-01

Abstract

The invention belongs to the field of electric elements, and particularly relates to a trench gate semiconductor device and a manufacturing method thereof, wherein the trench gate semiconductor device comprises a semiconductor substrate, a gate electrode region and an insulated gate dielectric layer, a trench is arranged on the semiconductor substrate, and the insulated gate dielectric layer is positioned between the gate electrode region and the semiconductor substrate; the insulating gate dielectric layer sequentially comprises a tunneling layer for tunneling charges under a strong electric field, a storage layer for capturing holes and a blocking layer for preventing the charges from further tunneling to the gate electrode area along the direction from the semiconductor substrate to the gate electrode area. In the invention, because of the three layers of structures with different functions of the insulated gate dielectric layer, the insulated gate dielectric layer can be charged with additional positive charges, thereby eliminating the problem of increased threshold voltage of a device caused by thickening of the insulated gate dielectric layer. Meanwhile, the effect that the threshold voltage of the device cannot be increased while the dielectric layer of the insulated gate is thickened to reduce the electric field intensity and improve the long-term reliability of the device is achieved.

Description

Trench gate semiconductor device and manufacturing method thereof

Technical Field

The invention belongs to the field of electric elements, and particularly relates to a trench gate semiconductor device and a manufacturing method thereof.

Background

Silicon carbide (SiC) is a new generation wide bandgap semiconductor material, and has excellent material characteristics such as a critical breakdown electric field 10 times that of silicon, high saturation drift rate, high thermal conductivity and the like, so that the performance of a power electronic device based on the SiC material is far superior to that of a Si-based material, and the SiC material has a wide application prospect particularly in high voltage and high power. The trench gate SiC MOSFET has a lower on-resistance than a planar gate, and is a development direction of SiC MOSFETs in the future. The cross-sectional structure of the conventional trench gate SiC MOSFET is shown in fig. 1j, and mainly includes a substrate region, an epitaxial region, a well region, a contact region, a source region, an insulated gate dielectric layer, a gate electrode region, an insulated dielectric isolation layer, a source electrode region, and a drain electrode region.

As shown in fig. 1a to 1j, the manufacturing method for forming the structure includes:

s1, as shown in fig. 1a, providing a substrate region 101 of a first conductivity type and an epitaxial region 102 of the first conductivity type;

s2, as shown in fig. 1b, forming a well region 103 of the second conductivity type on the epitaxial region 102 of the first conductivity type by epitaxy or ion implantation;

s3, as shown in fig. 1c, forming a contact region 104 of the second conductivity type on the well region 103 of the second conductivity type by selective region high temperature ion implantation;

s4, as shown in fig. 1d, forming a source region 105 of the first conductivity type by selective area high temperature ion implantation;

s5, as shown in figure 1e, depositing a mask layer, forming a mask 106 for etching the groove by photoetching and dry etching the etching area of the mask layer, forming a groove 107 by dry etching, and removing the mask;

s6, as shown in fig. 1f, forming an insulated gate dielectric layer 108 inside the trench 107 by high temperature thermal oxidation;

s7, as shown in fig. 1g, depositing polysilicon in the trench, removing the polysilicon on the surface, and reserving the polysilicon in the trench to form the gate electrode region 109;

s8, as shown in fig. 1h, depositing an insulating medium over the gate electrode region 109, and removing a portion of the insulating medium by photolithography to form an insulating medium isolation layer 110 and a contact hole portion 111;

s9, as shown in FIG. 1i, depositing a source electrode region 112 above the insulating medium isolation layer 110;

s10, as shown in fig. 1j, a drain region 113 is deposited under the substrate region 101 of the first conductivity type.

At present, in practical application, the electric field intensity borne by an insulated gate dielectric layer in a SiC MOSFET is generally high, which easily causes the reliability of the insulated gate dielectric to be reduced and even the insulated gate dielectric to be directly broken down. For the trench gate structure, at the corner of the bottom of the trench, since the electric field is more concentrated, this phenomenon is more likely to occur, thereby severely restricting the development of the trench gate SiC MOSFET. In the manufacturing method in the prior art, the electric field intensity born by the insulated gate dielectric layer can be reduced by thickening the insulated gate dielectric layer, and the long-term reliability of the product is improved. However, since the threshold voltage of the MOS device is proportional to the thickness of the insulated gate dielectric layer, thickening the insulated gate dielectric layer may cause the threshold voltage of the SiC MOSFET to be too large, which may adversely affect the practical application.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the problem that the threshold voltage of a SiC MOSFET is larger due to the thickening of an insulated gate dielectric layer of the existing trench gate semiconductor device, the trench gate semiconductor device and the manufacturing method thereof are provided.

In order to solve the above technical problem, in one aspect, the present invention provides a trench gate semiconductor device, including a semiconductor substrate, a gate electrode region and an insulated gate dielectric layer, wherein a trench for accommodating the gate electrode region is disposed on the semiconductor substrate, and the insulated gate dielectric layer is located between the gate electrode region and the semiconductor substrate;

the insulating gate dielectric layer sequentially comprises a tunneling layer for tunneling charges, a storage layer for capturing holes and a blocking layer for preventing the charges from further tunneling to the gate electrode area along the direction from the semiconductor substrate to the gate electrode area; the tunneling layer is formed on an inner wall of the trench, and the barrier layer is in contact with the gate electrode region.

Alternatively, the tunneling layer, the memory layer, and the blocking layer may be sequentially stacked in a direction from the semiconductor substrate to the gate electrode region, and the blocking layer may have a thickness greater than that of the tunneling layer and the memory layer.

Optionally, the total thickness of the insulated gate dielectric layer is greater than 0.07 um.

Optionally, the tunneling layer is made of silicon dioxide and has a thickness of 0.001-0.1 um;

the storage layer is silicon nitride or Ti_xZr_ySi_zO, the thickness is 0.001-0.05 um;

the barrier layer is silicon dioxide, and the thickness is 0.01-50 um.

Optionally, a width of the storage layer forbidden band is smaller than a width of the tunneling layer forbidden band and a width of the blocking layer forbidden band.

Optionally, the trench gate semiconductor device further includes a source electrode region, a drain electrode region, a well region, a contact region, and a source region, and the well region, the contact region, and the source region are disposed on both sides of the trench;

the well region is arranged on the semiconductor substrate and is in contact with the groove;

the contact region and the source region are disposed on the well region, and the source region is disposed adjacent to and in contact with the trench.

Optionally, the well region and the contact region are of a second conductivity type, the source region is of a first conductivity type, the source electrode region and the contact region are electrically coupled, and the source electrode region and the source region are electrically coupled.

Optionally, the trench gate semiconductor device further comprises an insulating dielectric isolation layer located between the gate electrode region and the source electrode region.

Optionally, the semiconductor substrate is of a first conductivity type, the semiconductor substrate includes a substrate region and an epitaxial region formed on the substrate region, the substrate region is disposed on the drain electrode region, and the drain electrode region is electrically coupled with the substrate region of the semiconductor substrate.

In another aspect, the present invention provides a method for manufacturing a trench gate semiconductor device, including the steps of:

s1, etching a groove on the semiconductor substrate of the first conduction type;

s2, forming a tunneling layer in the insulated gate dielectric layer in the groove;

s3, forming a storage layer in the insulated gate dielectric layer on the tunneling layer;

s4, forming a barrier layer in the insulated gate dielectric layer on the storage layer;

and S5, depositing polysilicon in the groove to form a gate electrode region.

Optionally, before etching the trench, a well region of the second conductivity type, a contact region of the second conductivity type and a source region of the first conductivity type on the well region are formed on the semiconductor substrate.

Optionally, two contact regions are doped and formed on the well region, the source region is formed between the contact regions at two ends, the end of the source region extends into the contact regions, the trench is etched and formed in the coverage area of the source region, and the bottom of the trench extends into the semiconductor substrate.

Optionally, after forming the gate electrode region, removing a part of the insulating gate dielectric layer outside the trench, forming an insulating dielectric isolation layer and a source electrode region above the gate electrode region, and forming a drain electrode region on the surface of the semiconductor substrate, wherein the insulating dielectric isolation layer is located between the source electrode region and the gate electrode region.

Optionally, the thickness of the source electrode region is 0.1-20 μm, the thickness of the drain electrode region is 0.1-20 μm, and the thickness of the insulating medium isolation layer is 0.1-3 μm;

furthermore, the thickness of the source electrode area is 1-10 μm, and the thickness of the drain electrode area is 0.5-10 μm.

Optionally, the doping concentration of the well region is 10¹⁶～10¹⁸cm^-3The thickness is 0.5-50 um, and the doping concentration of the contact region is 10¹⁸～10²¹cm^-3The thickness is 0.2-50 um, and the doping concentration of the source region is 10¹⁸～10²¹cm^-3The thickness is 0.2-50 um;

furthermore, the thickness of the well region is 0.5-10 μm, the thickness of the contact region is 0.2-10 μm, and the thickness of the source region is 0.2-10 μm.

Optionally, the etching depth of the trench is 0.5 to 50 μm, the etching width of the trench is 0.1 to 50 μm, and further, the etching depth of the trench is 0.5 to 10 μm, and the etching width of the trench is 0.1 to 10 μm.

Optionally, in step S5, the polysilicon is heavily doped with a doping concentration of 10¹⁸～10²⁵cm^-3The sheet resistance of the polysilicon is less than 100 omega/□.

Optionally, the semiconductor substrate comprises a substrate region and an epitaxial region formed on the substrate region, and the doping concentration of the epitaxial region is 10¹³～10¹⁷cm^-3The thickness is 6 to 500 μm, and further, the thickness of the epitaxial region is 6 to 50 μm.

In an embodiment of the invention, the tunneling layer is capable of tunneling charges of the semiconductor substrate under a strong electric field, the memory layer is located between the tunneling layer and the blocking layer, and the memory layer contains a certain amount of defects capable of trapping holes. Under the action of a strong electric field, holes of the semiconductor substrate overcome a potential barrier between the semiconductor substrate and the tunneling layer, tunnel into the storage layer and are captured by defects in the storage layer. The blocking layer is located between the storage layer and the gate electrode region and can prevent charges that have entered the storage layer from further tunneling to the gate electrode region and thus being stored in the storage layer.

Due to the three layers of structures with different functions of the insulated gate dielectric layer, the insulated gate dielectric layer can carry extra positive charges, and therefore the problem of increase of threshold voltage of a device caused by thickening of the insulated gate dielectric layer is solved. The structure can simultaneously ensure that the extra positive charge in the insulated gate dielectric layer keeps stable when the trench gate semiconductor device works normally, resists voltage and does not apply gate voltage, so that the threshold voltage of the device keeps stable.

Drawings

FIGS. 1a-1j are cross-sectional views of stages in a method of fabricating a trench-gate semiconductor device as provided by the prior art;

fig. 2a-2l are cross-sectional views of stages in a method of fabricating a trench-gate semiconductor device, in accordance with an embodiment of the present invention.

The reference numerals in the specification are as follows:

101. a substrate region; 102. an epitaxial region; 103. a well region; 104. a contact zone; 105. a source region; 106. masking; 107. a trench; 108. an insulated gate dielectric layer; 109. a gate electrode region; 110. an insulating dielectric isolation layer; 111. a contact hole portion; 112. a source electrode region; 113. a drain electrode region;

201. a substrate region; 202. an epitaxial region; 203. a well region; 204. a contact zone; 205. a source region; 206. masking; 207. a trench; 208. a tunneling layer; 209. a storage layer; 210. a barrier layer; 211. a gate electrode region; 212. an insulating dielectric isolation layer; 213. a contact hole portion; 214. a source electrode region; 215. and a drain electrode region.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 2a to 2l, in one aspect, an embodiment of the present invention provides a trench gate semiconductor device, which includes a semiconductor substrate, a gate electrode region 211, and an insulated gate dielectric layer, where a trench 207 is disposed on the semiconductor substrate for accommodating the gate electrode region 211, the insulated gate dielectric layer is located between the gate electrode region 211 and the semiconductor substrate, and the insulated gate dielectric layer has an insulating function, so as to achieve insulation between the gate electrode region 211 and the semiconductor substrate. The insulating gate dielectric layer sequentially comprises a tunneling layer 208, a storage layer 209 and a blocking layer 210, wherein the tunneling layer 208 is used for tunneling charges under a strong electric field, the storage layer 209 is used for capturing holes, the blocking layer 210 is used for preventing the charges from further tunneling to the gate electrode region 211, the tunneling layer 208 is formed on the inner wall of the trench 207, and the blocking layer 210 is in contact with the gate electrode region 211.

In the prior art, the electric field intensity can be effectively reduced by increasing the thickness of the insulated gate dielectric layer, so that the long-term reliability of the trench gate semiconductor device is improved, however, for the trench gate semiconductor device, the threshold voltage is in direct proportion to the thickness of the insulated gate dielectric layer, and the larger the threshold voltage is, the larger the voltage required for conducting the semiconductor device is, which is not beneficial to practical application.

In the present invention, the insulated gate dielectric layer is a thickened dielectric layer having a three-layer structure, and includes the tunneling layer 208, the storage layer 209 and the blocking layer 210, wherein the tunneling layer 208 is located at the bottom, that is, a layer close to the semiconductor substrate, and the tunneling layer 208 can be used for tunneling charges of the semiconductor substrate under a strong electric field. The storage layer 209 is located between the tunneling layer 208 and the blocking layer 210, and the storage layer 209 contains a certain amount of defects capable of trapping holes. The barrier layer 210 is located on top, i.e. a layer close to the gate electrode region 211, and can prevent further tunneling of charges that have entered the storage layer 209 to the gate electrode region 211.

In the insulating gate dielectric layer, the width of the storage layer 209 forbidden band is smaller than the widths of the tunneling layer 208 and the blocking layer 210 forbidden band, and is located between the two forbidden bands, so that a hole and electron barrier is formed between the storage layer 209 and the tunneling layer 208 and the blocking layer 210 on the two sides.

When a large negative gate voltage (e.g., -50 to-100V) is applied, a strong electric field directed from the semiconductor substrate to the gate electrode region 211 will be generated in the insulated gate dielectric layer. Under the action of a strong electric field, the holes of the semiconductor substrate overcome the potential barrier between the semiconductor substrate and the tunneling layer 208 and tunnel into the storage layer 209, and are captured by the defects therein. Since the blocking layer 210 is present between the storage layer 209 and the gate electrode region 211, holes cannot further tunnel to the gate electrode region 211 and are thus stored in the storage layer 209. The absolute value of this negative gate voltage is much larger than the positive gate voltage (e.g., 15-18V) for proper operation of the semiconductor device, so that a sufficiently large electric field can be generated to cause holes to tunnel into the memory layer 209.

When the absolute value of the negative gate voltage is close to or less than the positive gate voltage for normal operation, due to the thickness of the tunneling layer 208, the negative gate voltage will not generate a large enough electric field to allow holes to pass through the tunneling layer 208 into the storage layer 209. When no grid voltage is applied, the energy band of the three-layer structure of the insulated grid dielectric layer is nearly level because no electric field exists. Since the tunneling layer 208 and the blocking layer 210 have a certain thickness and a potential barrier exists between the two and the storage layer 209, the trapped holes will be confined in the storage layer 209 and hardly escape, and thus continue to remain in the storage layer 209.

After the chip is manufactured, a large negative gate voltage (e.g., -50V to-100V) is applied to the trench gate semiconductor device for a certain time, so that holes in the semiconductor substrate tunnel into the storage layer 209 and are stored therein. Due to the limited number of defects in the storage layer 209, hole trapping reaches saturation after a certain time. Therefore, the insulated gate dielectric layer obtains a certain amount of extra positive charges, the threshold voltage of the semiconductor device is reduced due to the positive charges in the insulated gate dielectric layer, and the increase of the threshold voltage of the semiconductor device caused by thickening of the insulated gate dielectric layer can be counteracted.

When the trench gate semiconductor device normally works, because the applied positive gate voltage (e.g. 15-18V) is not large enough, a large enough electric field cannot be generated to tunnel the holes in the storage layer 209 back into the semiconductor substrate, and therefore, the threshold voltage of the trench gate semiconductor device will be kept stable during the working process.

When no gate voltage is applied, the trapped holes will continue to remain in the storage layer 209 due to the existence of the potential barriers on both sides of the storage layer 209 and the fact that the tunneling layer 208 and the blocking layer 210 have a certain thickness, so that the threshold voltage of the trench gate semiconductor device will also remain stable, and the problem of threshold voltage increase caused by the addition of the insulated gate dielectric layer in the prior art is solved.

In the invention, due to the three layers of structures with different functions of the insulated gate dielectric layer, the insulated gate dielectric layer can be charged with additional positive charges, so that the problem of increase of the threshold voltage of a device caused by thickening of the insulated gate dielectric layer is solved. The structure can simultaneously ensure that the extra positive charge in the insulated gate dielectric layer keeps stable when the trench gate semiconductor device works normally and gate voltage is not applied, so that the threshold voltage of the device keeps stable.

In an embodiment, the semiconductor substrate is of a first conductivity type, the semiconductor substrate includes a substrate region 201 and an epitaxial region 202 formed on the substrate region 201, and both the substrate region 201 and the epitaxial region 202 are of the first conductivity type. The first conductivity type is either N-type or P-type. The substrate region 201 is disposed on the drain electrode region 215, the drain electrode region 215 is electrically coupled to the semiconductor substrate, and the trench 207 is disposed on the epitaxial region 202.

In an embodiment, the tunneling layer 208, the storage layer 209, and the blocking layer 210 are sequentially stacked along a direction from the semiconductor substrate to the gate electrode region 211. In order to ensure the blocking effect of the blocking layer 210, substrate holes are not further tunneled to the gate electrode region 211 and are stored in the storage layer 209, and the thickness of the blocking layer 210 is greater than the thickness of the tunneling layer 208 and the storage layer 209.

In the process of withstanding the voltage of the trench gate semiconductor device, the electric field generated by the large drain voltage cannot cause the holes trapped in the storage layer 209 to tunnel to the gate electrode region 211 due to the large thickness of the blocking layer 210. And the hole trapping is saturated, no more holes are trapped by the storage layer 209 during the withstand voltage process, so that the threshold voltage of the trench gate semiconductor device is kept stable during the withstand voltage process. In addition, the thickness of the insulated gate dielectric layer is larger, so that the electric field intensity is ensured to be lower, and the reliability of the semiconductor device is improved.

In one embodiment, the total thickness of the insulated gate dielectric layer is greater than 0.07 um.

In an embodiment, the tunneling layer 208 is silicon dioxide with a thickness of 0.001 to 0.1um, and the tunneling layer 208 is generally formed by thermal oxidation, chemical vapor deposition or atomic layer deposition.

The memory layer 209 is silicon nitride or Ti_xZr_ySi_zO or other materials capable of capturing holes, the thickness of the material is 0.001-0.05 um, wherein the ratio of x, y and z is not limited and can be selected according to actual conditions. The memory layer 209 may be formed by chemical vapor deposition or atomic layer deposition. By adjusting the thickness and the element ratio of the storage layer 209, the number of defects in the storage layer 209 and the types of capturable carriers can be adjusted, so that the number of extra charges obtained by the insulated gate dielectric layer is controlled, and the increase of the threshold voltage of the device caused by thickening the insulated gate dielectric layer can be accurately counteracted.

The barrier layer 210 is silicon dioxide and has a thickness of 0.01-50 um. The barrier layer 210 may be formed by chemical vapor deposition or atomic layer deposition. By adjusting the thicknesses of the tunneling layer 208, the storage layer 209 and the blocking layer 210, the total thickness of the insulating gate dielectric layer is larger than 0.07um, so that the threshold voltage of the device is not increased while the gate dielectric layer is thickened to reduce the electric field intensity and improve the long-term reliability of the device.

In an embodiment, the trench-gate semiconductor device further includes a source electrode region 214, a drain electrode region 215, a well region 203, a contact region 204, and a source region 205, and the well region 203, the contact region 204, and the source region 205 are disposed on two sides of the trench 207. The well region 203 is disposed on the epitaxial region 202 of the semiconductor substrate, and the well region 203 is in contact with an outer wall of the trench 207. The contact region 204 and the source region 205 are disposed on the well region 203, the source region 205 is disposed near the trench 207 and contacts with an outer wall of the trench 207, and the contact region 204 is connected to the source region 205 and is located outside the source region 205.

In an embodiment, the well region 203 and the contact region 204 are of the second conductivity type, the source region 205 is of the first conductivity type, the source electrode region 214 is electrically coupled to the contact region 204, and the source electrode region 214 is electrically coupled to the source region 205. The first conductivity type is N-type, and the second conductivity type is P-type. Or the first conduction type is P type, and the second conduction type is N type.

In an embodiment, the trench-gate semiconductor device further comprises an insulating dielectric isolation layer 212, the insulating dielectric isolation layer 212 is located between the gate electrode region 211 and the source electrode region 214 to achieve electrical isolation between the gate electrode region 211 and the source electrode region 214, contact hole portions 213 are provided at both sides of the insulating dielectric isolation layer 212, the contact hole portions 213 are located between the semiconductor substrate and the source electrode region 214, and the source electrode region 214 is electrically coupled with the contact region 204 via the contact hole portions 213.

On the other hand, as shown in fig. 2a to 2l, the present invention provides a method for manufacturing a trench gate semiconductor device, comprising the steps of:

s1, etching a groove 207 on the semiconductor substrate of the first conduction type;

s2, forming a tunneling layer 208 in the insulated gate dielectric layer in the groove 207;

s3, forming a storage layer 209 in the insulated gate dielectric layer on the tunneling layer 208;

s4, forming a barrier layer 210 in the insulated gate dielectric layer on the storage layer 209;

s5, depositing polysilicon in the trench 207 to form the gate electrode region 211.

In this embodiment, the tunneling layer 208, the storage layer 209, and the blocking layer 210 are sequentially deposited in the trench 207, so as to form the insulated gate dielectric layer with a certain thickness, and the insulated gate dielectric layer is thickened to reduce the electric field intensity, thereby improving the long-term reliability of the semiconductor device.

The tunneling layer 208 is located at the bottom of the trench 207, and can be used for tunneling charges in the substrate region 201 of the semiconductor substrate under a strong electric field. The storage layer 209 is located above the tunneling layer 208, the storage layer 209 contains a certain amount of defects capable of trapping holes, and the holes in the substrate region 201 can overcome the potential barrier between the semiconductor substrate and the tunneling layer 208 under the action of a strong electric field, tunnel into the storage layer 209, are trapped by the defects therein, and are stored in the storage layer 209. The blocking layer 210 is located above the storage layer 209 such that holes cannot further tunnel to the gate electrode region 211 and are thus stored in the storage layer 209.

After the hole capture reaches saturation, the insulated gate dielectric layer obtains a certain amount of extra positive charges, and the positive charges in the insulated gate dielectric layer can reduce the threshold voltage of the semiconductor device, so that the increase of the threshold voltage of the semiconductor device caused by the thickening of the insulated gate dielectric layer can be counteracted, and the threshold voltage cannot be increased while the insulated gate dielectric layer is thickened.

In an embodiment, as shown in fig. 2a, the semiconductor substrate includes a substrate region 201 and an epitaxial region 202 disposed on the substrate region 201, and an epitaxial parameter of the epitaxial region 202 is related to a withstand voltage requirement of the semiconductor device. Generally, the higher the withstand voltage requirement, the lower the epitaxial doping concentration, and the thicker the epitaxial thickness. The doping concentration of the epitaxial region 202 is 10¹³～10¹⁷cm^-3The thickness is 6 to 500 μm, and preferably, the thickness of the epitaxial region 202 is 6 to 50 μm.

Epitaxial is commonly known to mean growing a layer of single crystal material on single crystal substrate region 201 having the same lattice arrangement as substrate region 201, and epitaxial region 202 may be a homoepitaxial layer or a heteroepitaxial layer. There are many methods for implementing epitaxial growth, including molecular beam epitaxy, ultra-high vacuum chemical vapor deposition, atmospheric and reduced pressure epitaxy, etc., and conventional operations and methods in the art are used for implementing epitaxy, which are not described herein again.

In an embodiment, as shown in fig. 2b, before etching the trench 207, a well region 203 of a second conductivity type is formed on the epitaxial region 202 of the semiconductor substrate by epitaxy or ion implantation, and the doping concentration of the well region 203 is 10¹⁶～10¹⁸cm^-3The thickness is 0.5 to 50 μm, and preferably, the thickness of the well region 203 is 0.5 to 10 μm.

The basic principle of ion implantation is: the ion beam with a certain magnitude is incident into the epitaxial region 202, and a series of physical and chemical interactions between the ion beam and atoms or molecules in the epitaxial region 202 occur, so that the incident ions gradually lose energy and finally stay in the epitaxial region 202, and the surface composition, structure and performance of the epitaxial region 202 are changed, thereby optimizing the performance or obtaining some new excellent performance. Methods and operations for ion implantation are well known in the art and will not be described in detail herein.

As shown in fig. 2c and 2d, a selection region is formed on the well region 203 by photo development, and a contact region 204 of the second conductivity type and a source region 205 of the first conductivity type are formed by ion implantation. The doping concentration of the contact region 204 is 10¹⁸～10²¹cm^-3The thickness is 0.2 to 50 μm, and preferably, the thickness of the contact region 204 is 0.2 to 10 μm. The doping concentration of the source region 205 is 10¹⁸～10²¹cm^-3The thickness is 0.2 to 50 μm, and preferably, the thickness of the source region 205 is 0.2 to 10 μm.

In an embodiment, two contact regions 204 are doped in the selection region on the well region 203, a selection region is formed on the well region 203, and the selection regions on the contact regions 204 at two ends, the source region 205 is formed by ion implantation, the source region 205 is formed between the two contact regions 204, the end of the source region 205 extends into the contact region 204, and the bottom of the source region 205 is located on the well region 203.

In one embodiment, as shown in fig. 2e, the specific operation of step S1 is to deposit a mask 206 over the contact region 204 and the source region 205, form the mask 206 region shown in the figure by photolithography and dry etching, form a selective region by photolithography and development, etch the trench 207 in the coverage area of the source region 205, and extend the bottom of the trench 207 into the epitaxial region 202 of the semiconductor substrate. The etching depth of the trench 207 is 0.5 to 50 μm, and the etching width is 0.1 to 50 μm. Preferably, the etching depth of the trench 207 is 0.5 to 10 μm, and the width is 0.1 to 10 μm. After the trench 207 is formed, the mask 206 is removed, and the mask 206 may be silicon dioxide or silicon nitride with a thickness of 0.1-3 um.

In an embodiment, the specific operation of step S2 is to perform a high temperature thermal oxidation on the semiconductor device after the trench 207 is etched, as shown in fig. 2f, form the tunneling layer 208 on the inner wall of the trench 207 by the high temperature thermal oxidation, and simultaneously, the surface layers of the contact region 204 and the source region 205 outside the trench 207 are also covered by the tunneling layer 208. Besides thermal oxidation, the tunneling layer 208 may also be formed by a chemical vapor deposition or atomic layer deposition method, and the tunneling layer 208 may be generally made of silicon dioxide and has a thickness of 0.001-0.1 um.

In one embodiment, as shown in fig. 2g, the specific operation of step S3 is to form the memory layer 209 on the tunneling layer 208 of the semiconductor device obtained in step S2, wherein the memory layer 209 completely covers the tunneling layer 208, i.e. the tunneling layer 208 inside the trench 207 and outside the trench 207 is covered by the memory layer 209. The memory layer 209 may be silicon nitride or Ti_xZr_ySi_zO and other materials capable of capturing holes are formed by a chemical vapor deposition or atomic layer deposition method, the thickness of the storage layer 209 is 0.001-0.05 um, wherein the ratio of x, y and z is not limited and is selected according to actual conditions.

By adjusting the thickness and the element ratio of the storage layer 209, the number of defects in the storage layer 209 and the types of capturable carriers can be adjusted, so that the number of extra charges obtained by the insulated gate dielectric layer is controlled, and the increase of the threshold of the device caused by thickening the insulated gate dielectric layer can be accurately counteracted. Specifically, the carriers are divided into electrons and holes, defects for capturing carriers in the memory layer 209 are also divided into two types, one type is for capturing holes, the other type is for capturing electrons, the defect type and the defect density are related to materials and element ratios, the defect type and different trap densities can be changed by adjusting the element ratios and the materials, in addition, the thicker the memory layer 209 is, the larger the number of defects in the memory layer 209 is, the more carriers can be captured, the more the amount of extra charges obtained by the insulated gate dielectric layer is, and therefore, the amount of extra charges obtained by the insulated gate dielectric layer can be controlled by adjusting the thickness of the memory layer 209.

In one embodiment, as shown in fig. 2h, the operation of step S4 is to form the barrier layer 210 on the memory layer 209 of the semiconductor device obtained in step S3, and the barrier layer 210 completely covers the memory layer 209, i.e., the memory layer 209 inside the trench 207 and outside the trench 207 are covered by the barrier layer 210. The barrier layer 210 may be silicon dioxide, and is formed by a chemical vapor deposition or atomic layer deposition method, and the thickness of the barrier layer 210 is 0.01 to 50um, and preferably, the thickness is 0.04 to 10 um.

The thickness of the blocking layer 210 is larger than the thickness of the tunneling layer 208 and the thickness of the storage layer 209, which ensures that the blocking layer 210 can completely block such that holes cannot further tunnel into the gate electrode region 211 and thus are stored in the storage layer 209. By adjusting the thicknesses of the tunneling layer 208, the storage layer 209 and the blocking layer 210, the total thickness of the insulated gate dielectric layer is larger than 0.07um, the electric field intensity of the insulated gate dielectric layer is low, and the reliability of the semiconductor device is improved.

In an embodiment, the specific operation of step S5 is that after the insulated gate dielectric layer with a multilayer structure is formed in the trench 207, polysilicon needs to be deposited in the trench 207 and also formed on the surface of the insulated gate dielectric layer outside the trench 207, and at this time, a dry plasma etching process needs to be used to perform a patterned etching on the polysilicon to remove the polysilicon on the surface of the semiconductor device, as shown in fig. 2i, the gate electrode region 211 is formed by the polysilicon remaining in the trench 207. The insulating gate dielectric layer is located between the gate electrode region 211 and the semiconductor substrate for insulation.

The polysilicon is typically heavily doped with a doping concentration of 10¹⁸～10²⁵cm^-3The sheet resistance of polysilicon is less than 100 Ω/□ (ohms per square).

In an embodiment, after forming the gate electrode region 211, a portion of the insulated gate dielectric layer outside the trench 207 is removed to expose the contact region 204 and the source region 205 under the insulated gate dielectric layer, so that the surface of the semiconductor device is flat, that is, the upper surface of the gate electrode region 211 in the trench 207 and the surface of the contact region 204 (or the surface of the source region 205) are flush. Then, an insulating dielectric isolation layer 212 and a source electrode region 214 are formed over the gate electrode region 211, and a drain electrode region 215 is formed at the surface of the semiconductor substrate, the insulating dielectric isolation layer 212 being located between the source electrode region 214 and the gate electrode region 211.

After removing a portion of the insulating gate dielectric layer outside the trench 207, an insulating dielectric is deposited over the gate electrode region 211, while an insulating dielectric is deposited on the surface of the contact region 204 and the source region 205 of the semiconductor device. As shown in fig. 2j, after removing a part of the insulating medium by photolithography and etching, an insulating medium isolation layer 212 and a contact hole portion 213 are formed, wherein the insulating medium isolation layer 212 covers the gate electrode region 211, the contact hole portions 213 are disposed on both sides of the insulating medium isolation layer 212, and the contact hole portions 213 are actually regions where the insulating medium is etched away.

The insulating medium isolation layer 212 is made of silicon dioxide or silicon nitride and is 0.1-3 um thick.

In one embodiment, as shown in fig. 2k, the source electrode region 214 is aluminum, and specifically, aluminum particles are obtained by sputtering an aluminum target material, and the aluminum particles are deposited on the surface of the insulating dielectric isolation layer 212 and the contact hole portion 213 to form the source electrode region 214. The thickness of the source electrode region 214 is 0.1-20 μm, preferably 1-10 μm, and more preferably 3-8 μm.

The insulating medium is located between the gate electrode region 211 and the source electrode region 214 for realizing electrical insulation between the gate electrode region 211 and the source electrode region 214, and preventing the gate electrode region 211 and the source electrode region 214 from contacting and short-circuiting.

In one embodiment, as shown in fig. 2l, the drain electrode region 215 is silver, and specifically, silver particles are obtained by sputtering a silver target material, and the silver particles are deposited on the surface of the substrate of the semiconductor substrate to form the drain electrode region 215. The thickness of the drain electrode region 215 is 0.1-20 μm, preferably 0.5-10 μm, and more preferably 1-5 μm.

The present invention will be further illustrated by the following examples.

Example 1

In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹³cm^-3The thickness is 6 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁶cm^-3The thickness is 0.5 μm, and the doping concentration of the P + contact region 204 is 10¹⁸cm^-3The thickness is 0.2 μm, and the doping concentration of the N + source region 205 is 10¹⁸cm^-3The thickness is 0.2 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 0.5um, and the width of the groove 207 is 0.1 um;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.02 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, with a thickness of 0.02 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209, wherein the thickness is 0.04 um;

s7, depositing polycrystalline silicon in the groove 207, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 211 by the polycrystalline silicon reserved in the groove 207;

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 0.1 um;

s9, depositing and forming a source electrode region 214 with the thickness of 0.1 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 0.1 μm.

Example 2

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁷cm^-3The thickness is 500 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁸cm^-3The thickness is 50 μm, and the doping concentration of the P + contact region 204 is 10²¹cm^-3The thickness is 50 μm, and the doping concentration of the N + source region 205 is 10²¹cm^-3The thickness is 50 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 50 μm, and the width of the groove 207 is 50 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.05 μm;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 50 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 3 um;

s9, depositing and forming a source electrode region 214 with the thickness of 20 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 20 microns.

Example 3

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁵cm^-3The thickness is 280 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁷cm^-3The thickness is 25 μm, and the doping concentration of the P + contact region 204 is 10¹⁹cm^-3The thickness is 25 μm, and the doping concentration of the N + source region 205 is 10²⁰cm^-3The thickness is 24 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 26 μm, and the width of the groove 207 is 25 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.1 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, with a thickness of 0.001 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 24 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 1.5 um;

s9, depositing and forming a source electrode region 214 with the thickness of 10 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 10 mu m.

Example 4

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁴cm^-3The thickness is 20 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁷cm^-3The thickness is 46 μm, and the doping concentration of the P + contact region 204 is 10²⁰cm^-3The thickness is 12 μm, and the doping concentration of the N + source region 205 is 10¹⁹cm^-3The thickness is 42 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 8 μm, and the width of the groove 207 is 20 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.001 μm;

s5, forming the storage layer 209 with a thickness of 0.005um on the surface of the tunneling layer 208;

s6, forming the barrier layer 210 on the surface of the memory layer 209 with a thickness of 0.01 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 2.6 um;

s9, depositing and forming a source electrode region 214 with the thickness of 5 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 8 μm.

Example 5

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁶cm^-3The thickness is 100 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁶cm^-3The thickness is 3 μm, and the doping concentration of the P + contact region 204 is 10¹⁸cm^-32 μm thick, and the doping concentration of the N + source region 205 is 10²¹cm^-3The thickness is 48 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 30 μm, and the width of the groove 207 is 32 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.01 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, wherein the thickness of the storage layer is 0.002 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 12 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 0.5 um;

s9, depositing and forming a source electrode region 214 with the thickness of 2 μm above the insulating medium isolation layer 212;

and S10, depositing a drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 18 μm.

Example 6

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁷cm^-3The thickness is 12 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁸cm^-3The thickness is 35 μm, and the doping concentration of the P + contact region 204 is 10¹⁹cm^-3The thickness is 36 μm, and the doping concentration of the N + source region 205 is 10²⁰cm^-3The thickness is 5 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 15 μm, and the width of the groove 207 is 12 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.06 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, wherein the thickness is 0.05 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 35 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 1 um;

s9, depositing and forming a source electrode region 214 with the thickness of 15 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 3 μm.

Example 7

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁷cm^-3The thickness is 50 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁶cm^-3The thickness is 30 μm, and the doping concentration of the P + contact region 204 is 10¹⁸cm^-3The thickness is 8 μm, and the doping concentration of the N + source region 205 is 10¹⁸cm^-3The thickness is 12 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 42 μm, and the width of the groove 207 is 5 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.08 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, wherein the thickness is 0.008 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 20 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 2 um;

s9, depositing and forming a source electrode region 214 with the thickness of 8 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness is 15 mu m.

Example 8

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹³cm^-3The thickness is 30 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁸cm^-3The thickness is 40 μm, and the doping concentration of the P + contact region 204 is 10¹⁹cm^-3The thickness is 20 μm, and the doping concentration of the N + source region 205 is 10¹⁹cm^-3The thickness is 8 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 20 μm, and the width of the groove 207 is 42 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, with a thickness of 0.01 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 6 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 2.3 um;

s9, depositing and forming a source electrode region 214 with the thickness of 1 μm above the insulating medium isolation layer 212;

and S10, depositing a drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 12 μm.

Example 9

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁴cm^-3The thickness is 200 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁷cm^-3The thickness is 42 μm, and the doping concentration of the P + contact region 204 is 10²⁰cm^-3The thickness is 15 μm, and the doping concentration of the N + source region 205 is 10¹⁹cm^-3The thickness is 40 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 4 μm, and the width of the groove 207 is 35 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.03 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, with a thickness of 0.006 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 3 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 1.8 um;

s9, depositing and forming a source electrode region 214 with the thickness of 18 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 5 μm.

Example 10

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁵cm^-3The thickness is 24 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁸cm^-3The thickness is 8 μm, and the doping concentration of the P + contact region 204 is 10²⁰cm^-3The thickness is 30 μm, and the doping concentration of the N + source region 205 is 10²⁰cm^-3The thickness is 36 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 46 μm, and the width of the groove 207 is 2 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.008 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, wherein the thickness is 0.004 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 16 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 2.2 um;

s9, depositing and forming a source electrode region 214 with the thickness of 0.5 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 1 μm.

Example 11

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁷cm^-3The thickness is 35 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁶cm^-3The thickness is 12 μm, and the doping concentration of the P + contact region 204 is 10¹⁸cm^-3The thickness is 40 μm, and the doping concentration of the N + source region 205 is 10¹⁸cm^-3The thickness is 30 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 38 μm, and the width of the groove 207 is 8 μm;

s4, forming the tunneling layer 208 on the inner wall of the trench 207, with a thickness of 0.005 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, with a thickness of 0.012 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 30 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 1.2 um;

s9, depositing and forming a source electrode region 214 with the thickness of 12 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 0.8 μm.

Example 12

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁶cm^-3The thickness is 46 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁷cm^-3The thickness is 20 μm, and the doping concentration of the P + contact region 204 is 10¹⁹cm^-345 μm thick, and the doping concentration of the N + source region 205 is 10¹⁸cm^-3The thickness is 1 μm;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 34 μm, and the width of the groove 207 is 16 μm;

s5, forming the storage layer 209 with a thickness of 0.016um on the surface of the tunneling layer 208;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 40 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 0.8 um;

s9, depositing and forming a source electrode region 214 with the thickness of 0.8 μm above the insulating medium isolation layer 212;

and S10, depositing a drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 16 μm.

Example 13

S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 10¹⁵cm^-3The thickness is 400 mu m;

s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a P + contact region 204 and an N + source region 205 on the surface selection region of the well region 203 through ion implantation, wherein the doping concentration of the P-type well region 203 is 10¹⁷cm^-338 μm thick, and the doping concentration of the P + contact region 204 is 10¹⁸cm^-3The thickness is 33 μm, and the doping concentration of the N + source region 205 is 10¹⁹cm^-3The thickness is 18 mu m;

s3, forming a selection area at the N + source area 205 through illumination development, and performing dry etching to form a groove 207, wherein the etching depth of the groove 207 is 2 μm, and the width of the groove 207 is 46 μm;

s5, forming the storage layer 209 on the surface of the tunneling layer 208, with a thickness of 0.03 um;

s6, forming the barrier layer 210 on the surface of the storage layer 209 with a thickness of 45 um.

s8, depositing an insulating medium, and forming an insulating medium isolation layer 212 and a contact hole part 213 after removing part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolation layer 212 is 0.2 um;

s9, depositing and forming a source electrode region 214 with the thickness of 16 μm above the insulating medium isolation layer 212;

and S10, depositing and forming the drain electrode region 215 on the surface of the substrate, wherein the thickness of the drain electrode region is 0.5 mu m.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A trench gate semiconductor device is characterized by comprising a semiconductor substrate, a gate electrode region and an insulated gate dielectric layer, wherein a trench for accommodating the gate electrode region is arranged on the semiconductor substrate, and the insulated gate dielectric layer is positioned between the gate electrode region and the semiconductor substrate;

2. The trench-gate semiconductor device of claim 1, wherein the tunneling layer, the memory layer, and the blocking layer are sequentially stacked in a direction from the semiconductor substrate to the gate electrode region, and the blocking layer has a thickness greater than that of the tunneling layer and the memory layer.

3. The trench-gate semiconductor device of claim 1 wherein the total thickness of the insulated gate dielectric layer is greater than 0.07 um.

4. The trench-gate semiconductor device of claim 1 or 2,

the tunneling layer is made of silicon dioxide and has a thickness of 0.001-0.1 um;

the barrier layer is silicon dioxide, and the thickness is 0.01-50 um.

5. The trench-gate semiconductor device of claim 1, wherein a width of the storage layer bandgap is less than a width of the tunneling layer bandgap and a width of the barrier layer bandgap.

6. The trench-gate semiconductor device of claim 1 further comprising a source electrode region, a drain electrode region, a well region, a contact region, and a source region, wherein the well region, the contact region, and the source region are disposed on both sides of the trench;

the well region is arranged on the semiconductor substrate and is in contact with the outer wall of the groove;

the contact region and the source region are disposed on the well region, and the source region is disposed adjacent to the trench and in contact with an outer wall of the trench.

7. The trench-gate semiconductor device of claim 6 wherein the well region and the contact region are of a second conductivity type, the source region is of a first conductivity type, the source electrode region and the contact region are electrically coupled, and the source electrode region and the source region are electrically coupled.

8. The trench-gate semiconductor device of claim 6 further comprising an insulating dielectric isolation layer located between the gate electrode region and the source electrode region.

9. The trench-gate semiconductor device of claim 6 wherein the semiconductor substrate is of the first conductivity type, the semiconductor substrate comprising a substrate region and an epitaxial region formed on the substrate region, the substrate region being disposed on the drain electrode region, the drain electrode region being electrically coupled to the substrate region of the semiconductor substrate.

10. The method of manufacturing a trench gate semiconductor device according to any of claims 1 to 9, comprising the steps of:

and S5, depositing polysilicon in the groove to form a gate electrode region.

11. The method of manufacturing a trench-gate semiconductor device of claim 10 wherein, prior to etching the trench, a well region of the second conductivity type is formed on the semiconductor substrate, and a contact region of the second conductivity type and a source region of the first conductivity type are located over the well region.

12. The method of claim 11, wherein the well region is doped with two contact regions, the source region is formed between the two contact regions, ends of the source region extend into the contact regions, the trench is etched in a region covering the source region, and a bottom of the trench extends into the semiconductor substrate.

13. The method of claim 10, wherein after forming the gate electrode region, removing a portion of the insulating gate dielectric layer outside the trench, forming an insulating dielectric isolation layer and a source electrode region over the gate electrode region, and forming a drain electrode region on a surface of the semiconductor substrate, the insulating dielectric isolation layer being located between the source electrode region and the gate electrode region.

14. The method for manufacturing a trench gate semiconductor device according to claim 13, wherein the thickness of the source electrode region is 0.1 to 20 μm, the thickness of the drain electrode region is 0.1 to 20 μm, and the thickness of the insulating dielectric isolation layer is 0.1 to 3 μm;

15. The method of claim 11 wherein said well region has a doping concentration of 10¹⁶～10¹⁸cm^-3The thickness is 0.5-50 um, and the doping concentration of the contact region is 10¹⁸～10²¹cm^-3The thickness is 0.2-50 um, and the doping concentration of the source region is 10¹⁸～10²¹cm^-3The thickness is 0.2-50 um;

16. The method for manufacturing a trench gate semiconductor device according to claim 10, wherein the trench has an etching depth of 0.5 to 50 μm and an etching width of 0.1 to 50 μm, and further wherein the trench has an etching depth of 0.5 to 10 μm and an etching width of 0.1 to 10 μm.

17. The method of manufacturing a trench-gate semiconductor device of claim 10 wherein in step S5, the polysilicon is heavily doped with a doping concentration of 10¹⁸～10²⁵cm^-3The sheet resistance of the polysilicon is less than 100 omega/□.

18. The method of manufacturing a trench-gate semiconductor device of claim 10 wherein the semiconductor substrate comprises a substrate region and an epitaxial region formed on the substrate region, the epitaxial region having a doping concentration of 10¹³～10¹⁷cm^-3The thickness is 6-500 μm, and further the thickness of the epitaxial regionThe degree is 6 to 50 μm.