CN114284340A - Enhanced gallium nitride HEMT device and preparation method thereof - Google Patents
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Abstract
一种增强型氮化镓HEMT器件及其制备方法，属于HEMT器件制备技术领域，该HEMT器件中的异质结构包括沟道层和势垒层，沟道层和势垒层之间由上而下依次设置有半导体插入层Ⅰ和沟道控制层；沟道控制层的上方通过刻蚀形成凹栅区，凹栅区与势垒层的上表面覆盖有钝化层，栅极设置在凹栅区的钝化层上表面，源极和漏极分别穿过钝化层形成在沟道层的上表面，本发明的有益效果是，本发明在凹槽栅制作时实现了蚀刻自停止，实现了最优的沟道控制，增强了整体的极化效应，提高了二维电子气浓度，提升了器件的性能。
An enhancement mode gallium nitride HEMT device and a preparation method thereof belong to the technical field of HEMT device preparation. The heterostructure in the HEMT device includes a channel layer and a barrier layer, and the channel layer and the barrier layer are from top to A semiconductor insertion layer I and a channel control layer are arranged in sequence at the bottom; a recessed gate region is formed above the channel control layer by etching, the upper surface of the recessed gate region and the potential barrier layer is covered with a passivation layer, and the gate is arranged on the recessed gate The upper surface of the passivation layer in the region, the source electrode and the drain electrode are respectively formed on the upper surface of the channel layer through the passivation layer. The optimal channel control is enhanced, the overall polarization effect is enhanced, the two-dimensional electron gas concentration is increased, and the performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of HEMT device preparation, in particular to an enhanced gallium nitride HEMT device and a preparation method thereof.
Background
p-type gate GaN HEMT devices are commercialized as early as 2010, but the threshold voltage and the range of the borne gate voltage of the devices are small, so that great challenges are brought to the packaging of transistors, and high doping of a p-type layer is difficult to realize.
In order to solve the above problems, a method currently adopted includes: 1) f, ion implantation process: although this process is simple, it has a series of problems such as unstable threshold voltage and poor reliability. 2) And (3) thinning the thickness of the barrier layer: the method can reduce the two-dimensional electron gas concentration of the conducting channel and realize the enhancement type GaN HEMT device, but the method achieves the purpose of enhancing the device by sacrificing the two-dimensional electron gas density of all areas of the device, the resistance between a source and a drain is increased, and the forward characteristic of the device is poor. 3) The cascode technology: the technology is a technology for cascading a low-voltage silicon metal oxide semiconductor field effect transistor and a depletion mode GaN HEMT, and is a cascode structure in which a grid electrode of the GaN HEMT is connected with a source electrode of the silicon metal oxide semiconductor field effect transistor. The grid electrode, the source electrode and the drain electrode of the whole device respectively correspond to the grid electrode and the source electrode of the silicon metal oxide semiconductor field effect transistor and the drain electrode of the depletion type GaN HEMT. The GaN HEMT device with the structure has higher requirement on the packaging technology and larger volume due to the introduction of the silicon-based device. 4) Groove gate process: the difficulty of the process structure lies in the preparation of the groove, which is mainly plasma etching at present, the etching depth is in a nanometer range, and a chemical etching method is also reported, but because the chemical property of the GaN/AlGaN material is stable, the chemical etching is carried out by other auxiliary modes, such as illumination or high-temperature oxidation.
The groove grid can reduce the distance between the grid and the two-dimensional electronic gas layer, and the control capability of the grid is improved, so that the groove grid is a promising process technology for the enhancement type GaN HEMT device. However, the recessed gate technology also has inherent technical difficulties, and when the recessed gate is manufactured, because the epitaxial structure of the AlGaN/GaN HEMT is multi-layer, the etching rate of each layer is different, the depth of the recessed gate is difficult to control through etching time, and instability of threshold voltage and transconductance is also caused. Moreover, various etching methods can form a damage layer on the interface of the bottom of the gate, and can reduce the mobility. Therefore, how to optimize the etching process, precisely control the etching depth, reduce the influence of the etching damage on the device characteristics, and ensure the etching rate and good morphology while reducing the etching damage is the key point of the current research on the groove etching process. However, the current mainstream process route is to control the etching depth by a circular etching method, but the accurate control to the nanometer level is still not realized.
Disclosure of Invention
In order to solve the technical problems, the invention provides an enhanced gallium nitride HEMT device and a preparation method thereof, which can realize etching self-stop during groove gate manufacturing, realize optimal channel control, enhance the integral polarization effect, improve the concentration of two-dimensional electron gas and improve the performance of the device.
In order to achieve the purpose, the technical scheme adopted by the invention for solving the technical problems is as follows: the enhancement type gallium nitride HEMT device comprises a heterostructure, and a source electrode, a drain electrode and a grid electrode which are connected with the heterostructure, wherein the heterostructure comprises a channel layer and a barrier layer, and a semiconductor insertion layer I and a channel control layer are sequentially arranged between the channel layer and the barrier layer from top to bottom;
and a recessed gate region is formed above the channel control layer by etching, the upper surfaces of the recessed gate region and the barrier layer are covered with a passivation layer, the gate is arranged on the upper surface of the passivation layer of the recessed gate region, and the source electrode and the drain electrode respectively penetrate through the passivation layer to be formed on the upper surface of the channel layer.
The channel layer is made of gallium nitride, and the thickness of the channel layer is 100-200 nm.
The barrier layer is made of Alx1Ga1-x1N, wherein x1 is more than or equal to 0.1 and less than or equal to 0.3, and the thickness of the barrier layer is 20-30 nm.
The semiconductor insertion layer I is made of AlN, and the thickness of the semiconductor insertion layer I is 1-3 nm.
The channel control layer is made of Alx2Ga1-x2And N, wherein x2 is more than or equal to 0.1 and less than or equal to 0.3, and the thickness of the channel control layer is 2-4 nm.
The passivation layer is made of silicon nitride, and the thickness of the passivation layer is 100-120 nm.
The heterostructure further comprises a semiconductor insertion layer II arranged between the channel layer and the channel control layer, the semiconductor insertion layer II is made of AlN, and the thickness of the semiconductor insertion layer II is 1-3 nm.
The device also comprises a substrate, wherein a buffer layer is arranged between the substrate and the channel layer;
the buffer layer is made of a composite material of the substrate and the buffer layer, wherein the composite material of the substrate comprises any one or a combination of more than two of silicon, sapphire, silicon carbide, gallium nitride and aluminum nitride, and the composite material of the buffer layer comprises one or a combination of two of gallium nitride and aluminum nitride.
A preparation method of an enhanced gallium nitride HEMT device comprises the following steps:
step 1: growing a buffer layer on the substrate, and sequentially growing a channel layer, a semiconductor insertion layer II, a channel control layer, a semiconductor insertion layer I and a barrier layer on the buffer layer;
step 2: defining a gate region by adopting a photoetching process;
and step 3: starting etching from the upper surface of the barrier layer, and stopping etching at the bottom end of the semiconductor insertion layer I to obtain a concave gate region;
and 4, step 4: forming a passivation layer on the upper surfaces of the concave gate region and the barrier layer;
and 5: starting etching from the upper surface of the passivation layer, and stopping etching at the bottom end of the semiconductor insertion layer II to obtain deposition grooves respectively matched with the source electrode and the drain electrode;
step 6: and depositing metal in the corresponding deposition grooves to form a source electrode and a drain electrode, and depositing metal on the upper surface of the passivation layer of the recessed gate region to form a gate electrode.
The specific method of the step 3 is as follows: firstly, chlorine-based gas dry etching is adopted to remove the barrier layer on the top of the gate region, and then fluorine-based gas dry etching is adopted to remove the semiconductor insertion layer I.
The invention has the beneficial effects that:
1. according to the invention, a sandwich structure of a semiconductor insert layer I, a channel control layer and a semiconductor insert layer II is formed between a channel layer and a barrier layer, and due to the existence of the semiconductor insert layer I and the semiconductor insert layer II, the self-stop of etching can be realized in a subsequent photoetching definition gate region, an etched gate region and an etched source drain region, the effect of accurately controlling the depth of a gate and a source drain can be realized, and meanwhile, the two-dimensional electron gas concentration and the performance of a device can not be influenced.
2. According to the invention, the semiconductor insertion layer I is arranged between the channel layer and the barrier layer to serve as an etching barrier layer, so that the etching stop position of the concave gate region can be accurately controlled, the gate can realize optimal channel control through the channel control layer below the semiconductor insertion layer I, the piezoelectric polarization effect and the spontaneous polarization effect of the barrier layer with the thicker upper layer cannot be influenced by the thinner semiconductor insertion layer I, the spontaneous polarization direction of the semiconductor insertion layer I is consistent with the piezoelectric polarization direction of the barrier layer, the integral polarization effect is enhanced, the two-dimensional electron gas concentration is improved, and the performance of the device is improved.
3. The semiconductor insert layer II is arranged between the channel layer and the channel control layer, so that the etching stop position of the source and drain regions can be accurately controlled, the scattering effect of the barrier layer is reduced, and the electron mobility of two-dimensional electron gas generated on one side of the channel layer can be further improved.
4. The method comprises the steps of removing the barrier layer on the top of the gate region by chlorine-based gas dry etching, removing the semiconductor insertion layer I by fluorine-based gas dry etching, and generating AlF after etching3The etching self-stop can be realized by the mask effect, the etching efficiency is improved in the whole etching process, and the effects of accurately controlling the depth of the grid electrode to be in a nanometer level and protecting the lower channel control layer are realized.
In conclusion, the invention realizes etching self-stop when the groove gate is manufactured, realizes optimal channel control, enhances the integral polarization effect, improves the two-dimensional electron gas concentration and improves the performance of the device.
Drawings
The contents of the expressions in the various figures of the present specification and the labels in the figures are briefly described as follows:
FIG. 1 is a schematic structural view of an enhanced gallium nitride HEMT device in accordance with the present invention;
FIG. 2 is a process flow diagram of the present invention;
the labels in the above figures are: 1. the semiconductor device comprises a substrate, 2 parts of a buffer layer, 3 parts of a channel layer, 4 parts of a semiconductor insertion layer II, 5 parts of a channel control layer, 6 parts of a semiconductor insertion layer I, 7 parts of a barrier layer, 8 parts of a passivation layer, 9 parts of a grid electrode, 10 parts of a source electrode and 11 parts of a drain electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and the following embodiments are used for illustrating the present invention and are not intended to limit the scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The specific implementation scheme of the invention is as follows: as shown in fig. 1, an enhancement type gallium nitride HEMT device comprises a heterostructure, and a source electrode, a drain electrode and a gate electrode connected with the heterostructure, wherein the heterostructure comprises a channel layer and a barrier layer, a semiconductor insertion layer i and a channel control layer are sequentially arranged between the channel layer and the barrier layer from top to bottom, a concave gate region is formed above the channel control layer through etching, passivation layers cover the upper surfaces of the concave gate region and the barrier layer, the gate electrode is arranged on the upper surface of the passivation layer of the concave gate region, and the source electrode and the drain electrode respectively penetrate through the passivation layers to be formed on the upper surface of the channel layer. According to the invention, the semiconductor insertion layer I is arranged between the channel layer and the barrier layer and is used as an etching barrier layer, so that the etching stop position of the recessed gate region can be accurately controlled, and the optimal channel control can be realized through the channel control layer below the semiconductor insertion layer I on the grid.
Specifically, the semiconductor insertion layer I is made of AlN with the thickness of 1-3 nm, and the barrier layer is made of Alx1Ga1-x1N, wherein x1 is more than or equal to 0.1 and less than or equal to 0.3, the thickness of the barrier layer is 20-30 nm, the barrier layer has the effect that the existence of the two-dimensional electron gas is mainly influenced by the barrier layer, and the aluminum component and the thickness of the barrier layer influence the polarization electric field so as to influence the concentration of the two-dimensional electron gas. The aluminum gallium nitride has strong spontaneous polarization effect, the piezoelectric polarization effect is caused by the stress caused by lattice mismatching at the contact interface with the gallium nitride, the piezoelectric polarization effect and the spontaneous polarization effect of the barrier layer with thicker upper layer cannot be influenced by the thinner semiconductor insertion layer I, and the spontaneous polarization direction of the semiconductor insertion layer IThe polarization direction of the piezoelectric material is consistent with that of the barrier layer, the integral polarization effect is enhanced, the two-dimensional electron gas concentration is improved, and the performance of the device is improved.
Specifically, the channel layer is composed of gallium nitride, and the thickness of the channel layer is 100-200 nm. The channel layer is the key for generating two-dimensional electron gas, and the two-dimensional electron gas is generated through spontaneous polarization effect and piezoelectric polarization effect at the interface of the channel control layer and the channel layer. The two-dimensional electron gas is generated on one side of the channel layer, and the channel layer does not contain impurities, so that the scattering effect is small, and the electron mobility can be improved.
Specifically, the constituent material of the channel control layer therein is Alx2Ga1-x2And N, wherein x2 is more than or equal to 0.1 and less than or equal to 0.3, the thickness of the channel control layer is 2-4 nm, and a nm-level aluminum gallium nitride layer is reserved below the concave gate region, so that the optimal regulation and control effect of the gate on the channel can be realized.
Specifically, the passivation layer is made of silicon nitride, is 100-120 nm thick and plays a role in gate dielectric and passivation.
In addition, the heterostructure further comprises a semiconductor insertion layer II arranged between the channel layer and the channel control layer, the semiconductor insertion layer II is made of AlN, the thickness of the semiconductor insertion layer II is 1-3 nm, the etching stop position of the source and drain region can be accurately controlled, the scattering effect of the barrier layer is reduced, and the electron mobility of two-dimensional electron gas generated on one side of the channel layer can be further improved.
Specifically, the device further comprises a substrate, the substrate is made of any one or a combination of more than two of silicon, sapphire, silicon carbide, gallium nitride and aluminum nitride and used for growing epitaxial materials on the substrate, a buffer layer is arranged between the substrate and the channel layer, the buffer layer is made of one or a combination of two of gallium nitride and aluminum nitride, and the buffer layer can balance stress and reduce defects of the channel layer.
According to the invention, a sandwich structure of a semiconductor insert layer I, a channel control layer and a semiconductor insert layer II is formed between a channel layer and a barrier layer, and due to the existence of the semiconductor insert layer I and the semiconductor insert layer II, the self-stop of etching can be realized in a subsequent photoetching definition gate region, an etched gate region and an etched source drain region, the effect of accurately controlling the depth of a gate and a source drain can be realized, and meanwhile, the two-dimensional electron gas concentration and the performance of a device can not be influenced.
The preparation method of the enhanced gallium nitride HEMT device comprises the following steps:
step 1: an epitaxial layer is grown on a substrate. The epitaxial layer comprises a buffer layer, a channel layer, a semiconductor insertion layer II, a channel control layer, a semiconductor insertion layer I and a barrier layer which are sequentially grown from bottom to top.
Specifically, the epitaxial layer is grown on the substrate by using MOCVD, and the preparation method specifically comprises the following steps: 1) substrate pretreatment: h with the pressure of the reaction cavity maintained at 100-200 mbar at 900-1100 DEG C2Treating the substrate at high temperature for 10-20 minutes in the atmosphere, and then maintaining the pressure of the reaction cavity at 400-600 mbar of NH at 300-500 DEG C3Nitriding for 3-5 minutes in the atmosphere; 2) growing a buffer layer: at 500-600 ℃, maintaining the pressure of a reaction cavity at 100-300 mbar, growing an AlN buffer layer with the thickness of 10-20 nm on the substrate, and then growing a GaN buffer layer with the thickness of 1-3 mu m under the conditions of the same temperature and pressure intensity; 3) growing a channel layer: under the temperature of 900-1100 ℃, the pressure of a reaction cavity is maintained at 100-300 mbar, and undoped GaN with the thickness of 100-200 nm is continuously grown; 4) growing a semiconductor insertion layer II: controlling the pressure of the reaction chamber to be 100-300 mbar, controlling the temperature to be 900-1100 ℃, growing AlN on the non-doped GaN, and controlling the thickness to be 1-3 nm; 5) growing a channel control layer: controlling the temperature at 900-1100 ℃, maintaining the pressure of a reaction cavity at 100-300 mbar, continuously growing the AlGaN material with the thickness of 2-4 nm, wherein the doping concentrations of related elements are respectively Alx2Ga1-x2N, wherein x2 is more than or equal to 0.1 and less than or equal to 0.3; 6) growing a semiconductor insertion layer I: controlling the pressure of the reaction chamber at 100-300 mbar, controlling the temperature at 900-1100 ℃, and growing AlN on the AlGaN layer with the thickness of 1-3 nm; 7) growth barrier layer: controlling the pressure of the reaction chamber at 100-300 mbar, controlling the temperature at 900-1100 ℃, and growing AlGaN material with the thickness of 20-30 nm on the semiconductor insertion layer I, wherein the doping concentrations of related elements are respectively Alx1Ga1-x1N, wherein x1 is more than or equal to 0.1 and less than or equal to 0.3.
Step 2: and defining a gate region by adopting an oxidation photoetching process. Covering a mask on the surface of the barrier layer to expose the gate region to be etched.
And step 3: forming a recessed gate region. Etching from the upper surface of the barrier layer, removing the barrier layer on the top of the gate region by chlorine-based gas dry etching, removing the semiconductor insertion layer I by fluorine-based gas dry etching, and generating AlF after etching3The etching self-stop can be realized by the mask effect, and the etching is stopped at the bottom end of the semiconductor insertion layer I to obtain the concave gate region.
And 4, step 4: and after removing the mask, forming a passivation layer on the upper surfaces of the concave gate region and the barrier layer.
And 5: and forming a deposition groove matched with the source electrode and the drain electrode. Etching from the upper surface of the passivation layer, removing the barrier layer, the semiconductor insertion layer I and the channel control layer by chlorine-based gas dry etching, removing the semiconductor insertion layer II by fluorine-based gas dry etching, and generating AlF after etching3The etching self-stop can be realized by the mask effect, and the etching is stopped at the bottom end of the semiconductor insertion layer II to obtain deposition grooves respectively matched with the source electrode and the drain electrode;
step 6: and depositing corresponding metal in the corresponding deposition groove to form a source electrode and a drain electrode, depositing corresponding metal on the upper surface of the passivation layer of the concave gate region to form a gate electrode, and subsequently passivating and protecting the electrode layer.
In conclusion, the invention realizes etching self-stop when the groove gate is manufactured, realizes optimal channel control, enhances the integral polarization effect, improves the two-dimensional electron gas concentration and improves the performance of the device.
While the foregoing is directed to the principles of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
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| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 241000 1803, building 3, service outsourcing park, Wuhu high tech Industrial Development Zone, Anhui Province Applicant after: Anhui Changfei Advanced Semiconductor Co.,Ltd. Address before: 241000 1803, building 3, service outsourcing park, high tech Industrial Development Zone, Yijiang District, Wuhu City, Anhui Province Applicant before: WUHU QIDI SEMICONDUCTOR Co.,Ltd. |
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| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: No. 82 Limin East Road, Matang Street, Yijiang District, Wuhu City, Anhui Province 241000 Applicant after: Anhui Changfei Advanced Semiconductor Co.,Ltd. Address before: 1803, Building 3, Service Outsourcing Park, High tech Industrial Development Zone, Wuhu City, Anhui Province Applicant before: Anhui Changfei Advanced Semiconductor Co.,Ltd. Country or region before: China |