CN114284390A - Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof - Google Patents
Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof Download PDFInfo
- Publication number
- CN114284390A CN114284390A CN202111586437.4A CN202111586437A CN114284390A CN 114284390 A CN114284390 A CN 114284390A CN 202111586437 A CN202111586437 A CN 202111586437A CN 114284390 A CN114284390 A CN 114284390A
- Authority
- CN
- China
- Prior art keywords
- network transmission
- metal bump
- transmission line
- capacitor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Light Receiving Elements (AREA)
Abstract
The invention relates to a vertical incidence ultra-wideband integrated photoelectric detector chip and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: manufacturing a capacitor lower electrode and a bias network transmission line on a carrier; manufacturing a capacitor dielectric layer; forming a matching resistor, an impedance matching network transmission line and a capacitor upper electrode on the capacitor dielectric layer; forming a metal bump; manufacturing a micro lens on a substrate on the back of the diode chip; and welding the diode chip on the carrier in a flip-chip welding mode. In the invention, the control of parasitic parameters is realized and the bandwidth of the detector is improved by the monolithic integration of the bias network and the impedance matching network; coupling redundancy and responsivity are improved by integrating the micro lens on the back surface, and the influence of polarization loss is avoided; all indexes can reach or exceed the performance index level of the current mainstream waveguide type detector, and the method has positive significance for the design and manufacture of the ultra-wideband photoelectric detector.
Description
Technical Field
The invention belongs to the technical field of semiconductor photodiodes, and relates to a vertical incidence ultra-wideband integrated photoelectric detector chip and a manufacturing method thereof.
Background
In fiber optic communication systems, photodetector chips are used to convert information-carrying optical signals into information-carrying electrical signals for subsequent circuit processing of the information. Depending on the type of incident light, the light source can be classified into a vertical incidence type and a side illumination type.
With the continuous improvement (more than or equal to 50GHz) of the requirements of high-speed optical fiber communication systems, ultra-fast pulse measurement, millimeter wave systems, THz technologies and the like on the speed of photoelectric detector chips, in order to solve the problem of mutual restriction between speed and efficiency, the conventional high-speed detector with the frequency of more than 50GHz completely adopts a side incidence and evanescent wave coupling mode, and the index can reach the level that the bandwidth is more than or equal to 67GHz and the responsivity is more than or equal to 0.6A/W. However, compared with the conventional P-I-N type photodetector with vertical incidence, the side-incident type photodetector has the advantages of complex manufacturing process, high difficulty, low fiber coupling efficiency, high polarization influence and high manufacturing cost. On the other hand, the side incident structure cannot obtain a two-dimensional detector array, thereby limiting the application space of the photodiode chip.
The vertical incidence P-I-N type photoelectric detector is the simplest and reliable detector structure, but the detector is difficult to simultaneously consider high efficiency and high bandwidth. How to manufacture a high-performance detector by using a simple structure and a simple manufacturing process is the basis for further optimizing the detector and is also the requirement for more practical development. The performance of a detector chip of a traditional vertical incidence structure is limited by the following factors, and the requirements of high speed, high responsivity and high saturation cannot be met simultaneously:
1) bandwidth: discrete elements such as a capacitor and a resistor bring larger parasitic parameters, and the bandwidth of the device is influenced.
2) Responsivity: the ultra-high speed detector requires an extremely small active region, the diameter is usually less than or equal to 10 μm and less than the diameter (16 μm) of a light spot emitted by an optical fiber, so that complete coupling cannot be realized, and the responsivity of a chip is low.
3) Saturated optical power: the active area is very small, the dissipation power is very large (hundreds of milliwatts), and the chip thermal failure is easily caused.
Disclosure of Invention
In view of the above, the present invention provides a vertical incidence ultra-wideband integrated photodetector chip and a method for manufacturing the same, aiming at overcoming the defects of the existing high-speed photodetector in practical application, and solving the problems of complex manufacturing process, high difficulty, low optical fiber coupling efficiency, large polarization influence, and poor performance of the vertical incidence high-speed photodiode chip, such as bandwidth, responsivity, and saturation optical power.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for manufacturing a vertical incidence ultra-wideband integrated photoelectric detector chip comprises the following steps:
s1, manufacturing two capacitor lower electrodes on a carrier, and respectively forming a first bias network transmission line and a second bias network transmission line at two ends of each capacitor lower electrode;
s2, manufacturing a capacitance dielectric layer on the carrier;
s3, defining first contact holes on the capacitance dielectric layer at positions corresponding to the first bias network transmission lines respectively through a photoetching process, and defining second contact holes at positions corresponding to the second bias network transmission lines respectively through a photoetching process;
s4, forming a matching resistor, an impedance matching network transmission line and two capacitor upper electrodes on the capacitor dielectric layer; the matching resistor is respectively connected with the upper electrodes of the two capacitors through an impedance matching network transmission line;
s5, thinning and polishing the carrier to 100-150 mu m;
s6, forming a first metal bump connected with the matching resistor and a second metal bump connected with the first bias network transmission line through the first contact hole;
s7, manufacturing a micro lens corresponding to the active area of the diode chip on the substrate on the back of the diode chip;
and S8, welding the diode chip on the carrier in a flip-chip welding mode, so that the first metal bump is connected with the P pole of the diode chip in a welding mode, and the second metal bump is connected with the N pole of the diode chip in a welding mode.
Further, the carrier material is silicon carbide, aluminum nitride, diamond or graphene.
Further, the step S1 includes:
s101, taking a carrier, and depositing the carrier with the thickness of
The SiNx dielectric film is used as a dielectric film layer;
and S102, evaporating or sputtering by adopting a stripping process to form two capacitor lower electrodes on the dielectric film layer, respectively forming a first bias network transmission line protruding inwards at one end of each capacitor lower electrode, and respectively forming a second bias network transmission line protruding outwards at the other end of each capacitor lower electrode.
Further, in the step S2, a layer of PECVD is deposited on the carrier to a thickness of
The silicon nitride SiNx dielectric film is used as a capacitor dielectric layer, and the capacitor dielectric layer covers the capacitor lower electrode, the first bias network transmission line and the second bias network transmission line.
Further, the step S4 includes:
s401, forming a matching resistor on the capacitor dielectric layer by evaporation or sputtering through a stripping process;
s402, forming an impedance matching network transmission line and two capacitor upper electrodes by adopting an electroplating process, wherein the two capacitor upper electrodes are respectively positioned above the two capacitor lower electrodes; the impedance matching network transmission line comprises a first impedance matching network transmission line and two second impedance matching network transmission lines symmetrically arranged on two sides of the first impedance matching network transmission line, one end of the first impedance matching network transmission line is connected with the middle part of the matching resistor and then extends into a position between the two first contact holes, the two second impedance matching network transmission lines are respectively connected with one end of the matching resistor, and the two second impedance matching network transmission lines are also respectively connected with an electrode on a capacitor.
Further, the step S7 includes:
s71, taking a wafer with a diode chip; thinning and polishing the wafer to 100-200 μm by adopting a chemical mechanical polishing mode;
s72, defining a micro-lens position on the back of the diode chip by adopting a double-sided photoetching mode, and aligning the micro-lens position with the active area position of the diode chip;
s73, defining the shape of the micro lens by a photoetching process, and transferring the shape of the micro lens to the substrate on the back of the diode chip by adopting dry etching;
s74, depositing SiNx, SiO2 or SiNxOy as an anti-reflection antireflection film on the diode chip by adopting plasma enhanced chemical vapor deposition PECVD;
and S75, scribing the wafer to form a single diode chip.
Further, the micro lens is a diffraction type micro lens or a refraction type micro lens.
A vertical incidence ultra-wideband integrated photoelectric detector chip comprises a carrier and a diode chip which are connected in a flip-chip welding mode, wherein a dielectric film layer is arranged on the carrier, two capacitor lower electrodes are symmetrically arranged on the dielectric film layer, a first bias network transmission line protruding inwards is formed at one end of each capacitor lower electrode, a second bias network transmission line protruding outwards is formed at the other end of each capacitor lower electrode, and a capacitor dielectric layer covers the capacitor lower electrodes, the first bias network transmission lines and the second bias network transmission lines; the capacitor comprises a capacitor dielectric layer, a capacitor upper electrode, a capacitor lower electrode, a first impedance matching network transmission line, a second impedance matching network transmission line, a first metal bump, a second metal bump, a third metal bump, a fourth metal bump, a fifth metal bump, a sixth metal bump, a seventh metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth bump, a sixth metal, a fifth metal, a sixth metal; and a micro lens corresponding to the active area of the diode chip is manufactured on the substrate on the back of the diode chip, the P pole of the diode chip is in welding connection with the first metal bump, and the N pole of the diode chip is in welding connection with the second metal bump.
Further, the carrier material is silicon carbide, aluminum nitride, diamond or graphene.
Further, the dielectric film layer is thick
The SiNx dielectric film, the capacitor dielectric layer is thick
And a silicon nitride SiNx dielectric film.
In the invention, the control of parasitic parameters is realized and the bandwidth of the detector is improved by the monolithic integration of the bias network and the impedance matching network; coupling redundancy and responsivity are improved by integrating the micro lens on the back surface, and the influence of polarization loss is avoided; the heat dissipation of the chip is enhanced by the flip chip bonding mode, the large saturation optical power is realized, and all indexes can reach or exceed the performance index level of the current mainstream waveguide type detector. The high-performance photoelectric detector is manufactured by adopting a simple vertical incidence structure, a new design idea of the high-speed photoelectric detector is developed, and the design and the manufacture of the ultra-wideband photoelectric detector are of positive significance; the method can be widely applied to structural designs of a back-illuminated Positive-Intrinsic-Negative (PIN) structure and an Avalanche Photodiode (APD).
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a flow chart of a method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip according to a preferred embodiment of the present invention.
Fig. 2 is a schematic diagram of the capacitor bottom electrode and the bias network transmission line after being fabricated on the carrier.
Fig. 3 is a schematic diagram of fig. 2 after a first contact hole and a second contact hole are opened.
Fig. 4 is a schematic diagram of the carrier after forming a matched resistor on the capacitor dielectric layer.
Fig. 5 is a schematic diagram of the carrier after forming the impedance matching network transmission line and the capacitive top electrode.
Fig. 6 is a schematic diagram of the carrier after the first metal bump, the second metal bump and the fifth metal bump are manufactured.
Fig. 7 is a front view of the carrier after the first metal bump, the second metal bump and the fifth metal bump are manufactured.
Fig. 8 is a schematic diagram of a micro-lens fabricated on the substrate on the back side of the diode chip.
Fig. 9 is a schematic view of the carrier and diode chip before flip-chip bonding.
Fig. 10 is a schematic view after flip-chip bonding of the carrier and the diode chip.
In the figure: 100. the semiconductor device comprises a carrier, 110, a dielectric film layer, 120, a capacitor lower electrode, 121, a first bias network transmission line, 122, a second bias network transmission line, 130, a capacitor dielectric layer, 131, a first contact hole, 132, a second contact hole, 140, a matching resistor, 150, a capacitor upper electrode, 151, a first impedance matching network transmission line, 152, a second impedance matching network transmission line, 161, a first metal bump, 162, a second metal bump, 163, a third metal bump, 200, a diode chip, 201, a fourth metal bump, and 210, a micro lens.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
As shown in fig. 1, a preferred embodiment of the method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip of the present invention comprises the following steps:
as shown in fig. 1, a preferred embodiment of the method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip of the present invention comprises the following steps:
s1, as shown in fig. 2, two capacitance lower electrodes 120 are fabricated on the carrier 100, and a first bias network transmission line 121 and a second bias network transmission line 122 are respectively formed at two ends of each capacitance lower electrode 120, and the capacitance lower electrodes 120, the first bias network transmission line 121, and the second bias network transmission line 122 form a bias network. The material of the carrier 100 is preferably silicon carbide, aluminum nitride, diamond or graphene. This step may include the following substeps:
s101, taking a carrier 100, and depositing the carrier 100 with the thickness of
The SiNx dielectric film as the dielectric film layer 110;
s102, two capacitor lower electrodes 120 are formed on the dielectric film layer 110 through evaporation or sputtering by adopting a stripping process, a first bias network transmission line 121 protruding inwards is formed at one end of each capacitor lower electrode 120, and a second bias network transmission line 122 protruding outwards is formed at the other end of each capacitor lower electrode 120. The capacitive bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122 are made of titanium, platinum, chromium, gold, titanium alloy, platinum alloy, chromium alloy or gold alloy. The capacitor in this embodiment is powered downThe material of the pole 120, the first bias network transmission line 121 and the second bias network transmission line 122 is preferably titanium/platinum/gold, and the thickness is preferably titanium/platinum/gold
S2, forming a capacitor dielectric layer 130 on the carrier 100. The specific method comprises the following steps:
depositing a thickness of PECVD on the carrier 100 by plasma enhanced chemical vapor deposition
A silicon nitride SiNx dielectric film is used as the capacitor dielectric layer 130, and the capacitor dielectric layer 130 covers the capacitor bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122. The thickness of the capacitor dielectric layer 130 in this embodiment is preferably
S3, as shown in fig. 3, defining first contact holes 131 at positions on the capacitor dielectric layer 130 corresponding to each of the first bias network transmission lines 121 by photolithography, the positions of the two first contact holes 131 corresponding to the positions of the two N-poles of the diode chip 200; a second contact hole 132 is defined at a position corresponding to each second bias network transmission line 122 by a photolithography process.
S4, forming a matching resistor 140, an impedance matching network transmission line and two capacitor upper electrodes 150 on the capacitor dielectric layer 130; the matching resistor 140 is connected to two capacitor top electrodes 150 through an impedance matching network transmission line. This step may include the following substeps:
s401, as shown in FIG. 4, a matching resistor 140 is formed on the capacitor dielectric layer 130 by evaporation or sputtering through a stripping process; the material of the matching resistor 140 is preferably titanium, chromium, nickel, a titanium alloy, a chromium alloy, a nickel alloy, or a silicon alloy. In the present embodiment, the material of the matching resistor 140 is preferably CrSi with a thicknessPreferably, it is
S402, as shown in fig. 5, an impedance matching network transmission line and two upper capacitor electrodes 150 are formed by an electroplating process, and the two upper capacitor electrodes 150 are located above the two lower capacitor electrodes 120, respectively. The materials used for the impedance matching network transmission line and the two capacitor top electrodes 150 are gold, copper, tin, gold alloy, copper alloy, tin alloy, etc. In this embodiment, the material used for the impedance matching network transmission line and the two capacitive upper electrodes 150 is preferably Au, and the thickness of the impedance matching network transmission line and the two capacitive upper electrodes 150 is preferably 1 μm to 2.5 μm.
Before the electroplating process of the step is carried out, a metal seed layer for electroplating can be formed by adopting an electron beam, thermal evaporation or sputtering process, wherein the metal seed layer is made of chromium, gold, nickel, chromium alloy, gold alloy or nickel alloy; the material of the metal seed layer in the embodiment is preferably CrAu, and the thickness is preferably CrAu
After the electroplating process of step S6, the exposed portions of the metal seed layer are removed.
The impedance matching network transmission line comprises a first impedance matching network transmission line 151 and two second impedance matching network transmission lines 152 symmetrically arranged on two sides of the first impedance matching network transmission line 151, one end of the first impedance matching network transmission line 151 is connected with the middle part of the matching resistor 140 and then extends into a position between the two first contact holes 131, the two second impedance matching network transmission lines 152 are respectively connected with one end of the matching resistor 140, and the two second impedance matching network transmission lines 152 are also respectively connected with a capacitor upper electrode 150. The matching resistor 140, the first impedance matching network transmission line 151 and the two second impedance matching network transmission lines 152 form an impedance matching network.
S5, thinning and polishing the carrier 100 to 100-150 μm by adopting a chemical mechanical polishing mode.
S6, as shown in fig. 6 and 7, forming the first metal bump 161 connected to the matching resistor 140 and the second metal bump 162 connected to the first bias network transmission line 121 through the first contact hole 131 again by using the electroplating process; the first metal bump 161 is preferably disposed at one end of the first impedance matching network transmission line 151 extending between the two first contact holes 131, so that the first metal bump 161 is located between the two second metal bumps 162, and the position of the first metal bump 161 corresponds to the position of the P-pole of the diode chip 200.
In this embodiment, a plurality of third metal bumps 163 are also formed by electroplating to increase the bonding points of the flip chip bonding. The materials used for the first metal bump 161, the second metal bump 162 and the third metal bump 163 are gold, copper, tin, gold alloy, copper alloy, tin alloy, etc. In the present embodiment, the material used for the first metal bump 161, the second metal bump 162 and the third metal bump 163 is preferably Au, and the thickness is preferably 5 μm to 10 μm.
At this time, a fourth metal bump 201 may be further formed on the diode chip 200 at a position corresponding to each third metal bump 163, so as to facilitate flip-chip bonding. The material used for the fourth metal bump 201 is gold, copper, tin, gold alloy, copper alloy, tin alloy, etc., preferably Au, and the thickness is preferably 5 μm to 10 μm.
S7, as shown in fig. 8, fabricating a microlens 210 corresponding to the active region of the diode chip 200 on the substrate on the back side of the diode chip 200; the diode chip 200 is a vertical incidence type high-speed photodiode chip 200, and the structure thereof is the prior art and is not described herein. This step may include the following substeps:
s71, taking a wafer with the diode chip 200; and thinning and polishing the wafer to 100-200 μm by adopting a chemical mechanical polishing mode.
S72, defining the position of the microlens 210 on the back of the diode chip 200 by double-sided lithography, so that the position of the microlens 210 and the position of the active region of the diode chip 200 need to be aligned strictly, and the error is less than 1 μm.
And S73, defining the appearance of the micro lens 210 by using a photoetching process, wherein the types of the micro lens 210 comprise a diffraction type micro lens 210 and a refraction type micro lens 210, and transferring the appearance of the micro lens 210 to the substrate on the back side of the diode chip 200 by using dry etching. In the present embodiment, it is preferable to use the refractive microlens 210, and the microlens 210 has a diameter of 50 μm to 80 μm and a height of 3 μm to 10 μm.
S74, depositing SiNx, SiO2 or SiNxOy as an anti-reflection antireflection film on the diode chip 200 by adopting plasma enhanced chemical vapor deposition PECVD. In this embodiment, it is preferable to use plasma enhanced chemical vapor deposition PECVD to deposit SiNx as the anti-reflection antireflection film.
And S75, scribing the wafer through the scribing lines to form the single diode chip 200.
S8, as shown in fig. 9 and 10, the diode chip 200 is flip-chip bonded to the carrier 100, the first metal bump 161 is connected to the P-electrode of the diode chip 200 by soldering, and the second metal bump 162 is connected to the N-electrode of the diode chip 200 by soldering. When the third metal bump 163 is disposed on the carrier 100 and the fourth metal bump 201 is disposed on the diode chip 200, the third metal bump 163 and the fourth metal bump 201 at corresponding positions are also connected by soldering.
In this embodiment, the control of parasitic parameters is realized and the detector bandwidth is increased (the bandwidth of the photodetector chip in this embodiment can reach 70GHz) by the monolithic integration of the bias network and the impedance matching network; coupling redundancy and responsivity are improved by integrating the micro-lenses 210 on the back side, and the influence of polarization loss is avoided; the heat dissipation of the chip is enhanced by the flip chip bonding mode, the large saturation optical power is realized, and all indexes can reach or exceed the performance index level of the current mainstream waveguide type detector. The embodiment adopts a simple vertical incidence structure to manufacture the high-performance photoelectric detector, develops a new design idea of the high-speed photoelectric detector, and has positive significance for the design and manufacture of the ultra-wideband photoelectric detector; the method can be widely applied to structural designs of a back-illuminated Positive-Intrinsic-Negative (PIN) structure and an Avalanche Photodiode (APD).
As shown in fig. 9 and 10, a preferred embodiment of the ultra-wideband integrated photodetector chip of the present invention comprises a carrier 100 and a diode chip 200 connected by flip-chip bonding; as shown in fig. 6 and 7, the material of the carrier 100 is preferably silicon carbide, aluminum nitride, diamond or graphene. The carrier 100 is provided with a dielectric film layer 110, and the dielectric film layer 110 is preferably thick
The SiNx dielectric film of (1); two capacitor lower electrodes 120 are symmetrically arranged on the dielectric film layer 110, one end of each capacitor lower electrode 120 is respectively provided with a first bias network transmission line 121 protruding inwards, the other end of each capacitor lower electrode 120 is respectively provided with a second bias network transmission line 122 protruding outwards, the capacitor lower electrodes 120, the first bias network transmission lines 121 and the second bias network transmission lines 122 are preferably made of titanium/platinum/gold, and the thicknesses of the capacitor lower electrodes 120, the first bias network transmission lines 121 and the second bias network transmission lines 122 are preferably titanium/platinum/gold
The capacitive bottom electrode 120, the first bias network transmission line 121 and the second bias network transmission line 122 are covered with a capacitive dielectric layer 130, and the capacitive dielectric layer 130 is preferably thick
And a silicon nitride SiNx dielectric film. The capacitance dielectric layer 130 is provided with first contact holes 131 at positions corresponding to the first bias network transmission lines 121, and is provided with second contact holes 132 at positions corresponding to the second bias network transmission lines 122, each first contact hole 131 is provided with a second metal bump 162, the second metal bump 162 is preferably made of Au, and the thickness of the second metal bump 162 is preferably 5 μm to 10 μm. A position on the capacitor dielectric layer 130 corresponding to the upper part of each capacitor lower electrode 120A capacitor upper electrode 150 is respectively arranged, one side of the capacitor upper electrode 150 is provided with a matching resistor 140, the matching resistor 140 is preferably made of CrSi, and the thickness is preferably selected
A first impedance matching network transmission line 151 is connected to the middle of the matching resistor 140, the first impedance matching network transmission line 151 is provided with a first metal bump 161, two ends of the matching resistor 140 are respectively connected with a second impedance matching network transmission line 152, and the two second impedance matching network transmission lines 152 are also respectively connected with a capacitor upper electrode 150; the first impedance matching network transmission line 151 and the two second impedance matching network transmission lines 152 are used for connecting radio frequency output ends; the material used by the impedance matching network transmission line and the two capacitor upper electrodes 150 is preferably Au, and the thickness is preferably 1-2.5 μm.
The diode chip 200 is a vertical incidence type high-speed photodiode chip 200, the P pole of the diode chip 200 is connected with the first metal bump 161 in a welding manner, and the N pole of the diode chip 200 is connected with the second metal bump 162 in a welding manner. A fourth metal bump 201 is respectively arranged at a position on the diode chip 200 corresponding to each third metal bump 163; the third metal bump 163 and the fourth metal bump 201 at the corresponding positions are connected by soldering. As shown in fig. 8, a microlens 210 corresponding to an active region of the diode chip 200 is fabricated on the substrate on the rear surface of the diode chip 200. In the present embodiment, it is preferable to use the refractive microlens 210, and the microlens 210 has a diameter of 50 μm to 80 μm and a height of 3 μm to 10 μm. SiNx is deposited on the diode chip 200 as an anti-reflection film.
In the embodiment, the carrier 100 of the monolithic integrated impedance matching network and the bias network and the vertical incidence type high-speed photodiode chip 200 of the monolithic integrated microlens 210 are mixed and integrated together by flip chip bonding. Parasitic parameters can be reduced and controlled, the bandwidth of the detector is improved, the high-performance photoelectric detector is manufactured by adopting a simple vertical incidence structure, and all indexes can reach or exceed the performance index level of the current mainstream waveguide type detector.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (10)
1. A method for manufacturing a vertical incidence ultra-wideband integrated photoelectric detector chip is characterized by comprising the following steps:
s1, manufacturing two capacitor lower electrodes on a carrier, and respectively forming a first bias network transmission line and a second bias network transmission line at two ends of each capacitor lower electrode;
s2, manufacturing a capacitance dielectric layer on the carrier;
s3, defining first contact holes on the capacitance dielectric layer at positions corresponding to the first bias network transmission lines respectively through a photoetching process, and defining second contact holes at positions corresponding to the second bias network transmission lines respectively through a photoetching process;
s4, forming a matching resistor, an impedance matching network transmission line and two capacitor upper electrodes on the capacitor dielectric layer; the matching resistor is respectively connected with the upper electrodes of the two capacitors through an impedance matching network transmission line;
s5, thinning and polishing the carrier to 100-150 mu m;
s6, forming a first metal bump connected with the matching resistor and a second metal bump connected with the first bias network transmission line through the first contact hole;
s7, manufacturing a micro lens corresponding to the active area of the diode chip on the substrate on the back of the diode chip;
and S8, welding the diode chip on the carrier in a flip-chip welding mode, so that the first metal bump is connected with the P pole of the diode chip in a welding mode, and the second metal bump is connected with the N pole of the diode chip in a welding mode.
2. The method for manufacturing the chip of the vertical incidence ultra-wideband integrated photodetector as claimed in claim 1, wherein the carrier material is silicon carbide, aluminum nitride, diamond or graphene.
3. The method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip according to claim 1, wherein the step of S1 includes:
s101, taking a carrier, and depositing the carrier with the thickness of
The SiNx dielectric film is used as a dielectric film layer;
and S102, evaporating or sputtering by adopting a stripping process to form two capacitor lower electrodes on the dielectric film layer, respectively forming a first bias network transmission line protruding inwards at one end of each capacitor lower electrode, and respectively forming a second bias network transmission line protruding outwards at the other end of each capacitor lower electrode.
4. The method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip as claimed in claim 1, wherein in the step S2, the carrier is deposited by plasma enhanced chemical vapor deposition PECVD to a thickness of
The silicon nitride SiNx dielectric film is used as a capacitor dielectric layer, and the capacitor dielectric layer covers the capacitor lower electrode, the first bias network transmission line and the second bias network transmission line.
5. The method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip according to claim 1, wherein the step of S4 includes:
s401, forming a matching resistor on the capacitor dielectric layer by evaporation or sputtering through a stripping process;
s402, forming an impedance matching network transmission line and two capacitor upper electrodes by adopting an electroplating process, wherein the two capacitor upper electrodes are respectively positioned above the two capacitor lower electrodes; the impedance matching network transmission line comprises a first impedance matching network transmission line and two second impedance matching network transmission lines symmetrically arranged on two sides of the first impedance matching network transmission line, one end of the first impedance matching network transmission line is connected with the middle part of the matching resistor and then extends into a position between the two first contact holes, the two second impedance matching network transmission lines are respectively connected with one end of the matching resistor, and the two second impedance matching network transmission lines are also respectively connected with an electrode on a capacitor.
6. The method for manufacturing a vertical incidence ultra-wideband integrated photodetector chip according to claim 1, wherein the step of S7 includes:
s71, taking a wafer with a diode chip; thinning and polishing the wafer to 100-200 μm by adopting a chemical mechanical polishing mode;
s72, defining a micro-lens position on the back of the diode chip by adopting a double-sided photoetching mode, and aligning the micro-lens position with the active area position of the diode chip;
s73, defining the shape of the micro lens by a photoetching process, and transferring the shape of the micro lens to the substrate on the back of the diode chip by adopting dry etching;
s74, depositing SiNx, SiO2 or SiNxOy as an anti-reflection antireflection film on the diode chip by adopting plasma enhanced chemical vapor deposition PECVD;
and S75, scribing the wafer to form a single diode chip.
7. The method for manufacturing the chip of the vertical incidence ultra-wideband integrated photodetector as claimed in claim 6, wherein the micro-lens is a diffractive micro-lens or a refractive micro-lens.
8. A vertical incidence ultra-wideband integrated photoelectric detector chip is characterized by comprising a carrier and a diode chip which are connected in a flip-chip welding mode, wherein a dielectric film layer is arranged on the carrier, two capacitor lower electrodes are symmetrically arranged on the dielectric film layer, a first bias network transmission line protruding inwards is formed at one end of each capacitor lower electrode, a second bias network transmission line protruding outwards is formed at the other end of each capacitor lower electrode, and capacitor dielectric layers are covered on the capacitor lower electrodes, the first bias network transmission lines and the second bias network transmission lines; the capacitor comprises a capacitor dielectric layer, a capacitor upper electrode, a capacitor lower electrode, a first impedance matching network transmission line, a second impedance matching network transmission line, a first metal bump, a second metal bump, a third metal bump, a fourth metal bump, a fifth metal bump, a sixth metal bump, a seventh metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth metal bump, a sixth metal bump, a fifth bump, a sixth metal, a fifth metal, a sixth metal; and a micro lens corresponding to the active area of the diode chip is manufactured on the substrate on the back of the diode chip, the P pole of the diode chip is in welding connection with the first metal bump, and the N pole of the diode chip is in welding connection with the second metal bump.
9. The vertically incident ultra-wideband integrated photodetector chip of claim 8, wherein the carrier material is silicon carbide, aluminum nitride, diamond or graphene.
10. The normal-incidence ultra-wideband integrated photodetector chip of claim 8, wherein the dielectric film layer is thick
The SiNx dielectric film, the capacitor dielectric layer is thick
And a silicon nitride SiNx dielectric film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111586437.4A CN114284390B (en) | 2021-12-23 | 2021-12-23 | Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111586437.4A CN114284390B (en) | 2021-12-23 | 2021-12-23 | Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114284390A true CN114284390A (en) | 2022-04-05 |
| CN114284390B CN114284390B (en) | 2024-04-16 |
Family
ID=80874210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111586437.4A Active CN114284390B (en) | 2021-12-23 | 2021-12-23 | Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114284390B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115285930A (en) * | 2022-07-25 | 2022-11-04 | 武汉衷华脑机融合科技发展有限公司 | Micro-needle and flat cable inverse welding connecting structure and preparation process thereof |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10256467A (en) * | 1997-03-10 | 1998-09-25 | Japan Radio Co Ltd | Silicon high frequency integrated circuit |
| CN1244031A (en) * | 1998-07-31 | 2000-02-09 | 佳能株式会社 | Method and apparatus for manufacturing semiconductor layers, and manufacture of photovoltaic solar cell |
| JP2001053297A (en) * | 1999-08-05 | 2001-02-23 | Kanegafuchi Chem Ind Co Ltd | Solar cell short circuit part removing device and method |
| AU2002224563B2 (en) * | 2000-07-25 | 2005-03-03 | Kevin Liddiard | Active or self-biasing micro-bolometer infrared detector |
| US7718965B1 (en) * | 2006-08-03 | 2010-05-18 | L-3 Communications Corporation | Microbolometer infrared detector elements and methods for forming same |
| CN102280439A (en) * | 2011-05-13 | 2011-12-14 | 中国电子科技集团公司第十三研究所 | Internally matching network for microwave power transistor and manufacturing method of internally matching network |
| CN104538480A (en) * | 2015-01-04 | 2015-04-22 | 中国电子科技集团公司第四十四研究所 | Integrated structure for inversely installing high-speed InGaAs photoelectric detector chip and manufacturing method |
| CN106784118A (en) * | 2017-01-13 | 2017-05-31 | 深圳市芯思杰联邦国际科技发展有限公司 | Back-illuminated type high-speed photodiode receives chip and preparation method thereof |
| CN107800376A (en) * | 2016-04-05 | 2018-03-13 | 太阳能安吉科技有限公司 | Safety switch for photovoltaic system |
| CN108318907A (en) * | 2018-02-01 | 2018-07-24 | 北京京东方光电科技有限公司 | X-ray detection panel and its manufacturing method and X-ray detection device |
| CN108710056A (en) * | 2018-07-19 | 2018-10-26 | 中国科学院高能物理研究所 | A kind of Flip Chip Bond Technique yield and parasitic parameter qualitative assessment device and method |
| CN109659707A (en) * | 2018-12-24 | 2019-04-19 | 广东工业大学 | Terahertz detector and method based on N × M dielectric resonator antenna array |
| CN110854210A (en) * | 2019-11-18 | 2020-02-28 | 中航光电科技股份有限公司 | Ultrahigh frequency radio frequency photoelectric detector based on BOX encapsulation |
| CN110865434A (en) * | 2019-11-21 | 2020-03-06 | 中国科学院半导体研究所 | Integrated microwave circuit |
| CN111509372A (en) * | 2020-05-09 | 2020-08-07 | 成都理工大学 | Automobile anti-collision radar array antenna |
| CN112768550A (en) * | 2020-12-18 | 2021-05-07 | 中国电子科技集团公司第四十四研究所 | Structure for improving responsivity of back-illuminated photodiode and manufacturing method |
-
2021
- 2021-12-23 CN CN202111586437.4A patent/CN114284390B/en active Active
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10256467A (en) * | 1997-03-10 | 1998-09-25 | Japan Radio Co Ltd | Silicon high frequency integrated circuit |
| CN1244031A (en) * | 1998-07-31 | 2000-02-09 | 佳能株式会社 | Method and apparatus for manufacturing semiconductor layers, and manufacture of photovoltaic solar cell |
| JP2001053297A (en) * | 1999-08-05 | 2001-02-23 | Kanegafuchi Chem Ind Co Ltd | Solar cell short circuit part removing device and method |
| AU2002224563B2 (en) * | 2000-07-25 | 2005-03-03 | Kevin Liddiard | Active or self-biasing micro-bolometer infrared detector |
| US7718965B1 (en) * | 2006-08-03 | 2010-05-18 | L-3 Communications Corporation | Microbolometer infrared detector elements and methods for forming same |
| CN102280439A (en) * | 2011-05-13 | 2011-12-14 | 中国电子科技集团公司第十三研究所 | Internally matching network for microwave power transistor and manufacturing method of internally matching network |
| CN104538480A (en) * | 2015-01-04 | 2015-04-22 | 中国电子科技集团公司第四十四研究所 | Integrated structure for inversely installing high-speed InGaAs photoelectric detector chip and manufacturing method |
| CN107800376A (en) * | 2016-04-05 | 2018-03-13 | 太阳能安吉科技有限公司 | Safety switch for photovoltaic system |
| CN106784118A (en) * | 2017-01-13 | 2017-05-31 | 深圳市芯思杰联邦国际科技发展有限公司 | Back-illuminated type high-speed photodiode receives chip and preparation method thereof |
| CN108318907A (en) * | 2018-02-01 | 2018-07-24 | 北京京东方光电科技有限公司 | X-ray detection panel and its manufacturing method and X-ray detection device |
| CN108710056A (en) * | 2018-07-19 | 2018-10-26 | 中国科学院高能物理研究所 | A kind of Flip Chip Bond Technique yield and parasitic parameter qualitative assessment device and method |
| CN109659707A (en) * | 2018-12-24 | 2019-04-19 | 广东工业大学 | Terahertz detector and method based on N × M dielectric resonator antenna array |
| US20200203833A1 (en) * | 2018-12-24 | 2020-06-25 | Guangdong University Of Technology | TERAHERTZ DETECTOR AND METHOD BASED ON NxM DIELECTRIC RESONANT ANTENNA ARRAY |
| CN110854210A (en) * | 2019-11-18 | 2020-02-28 | 中航光电科技股份有限公司 | Ultrahigh frequency radio frequency photoelectric detector based on BOX encapsulation |
| CN110865434A (en) * | 2019-11-21 | 2020-03-06 | 中国科学院半导体研究所 | Integrated microwave circuit |
| CN111509372A (en) * | 2020-05-09 | 2020-08-07 | 成都理工大学 | Automobile anti-collision radar array antenna |
| CN112768550A (en) * | 2020-12-18 | 2021-05-07 | 中国电子科技集团公司第四十四研究所 | Structure for improving responsivity of back-illuminated photodiode and manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115285930A (en) * | 2022-07-25 | 2022-11-04 | 武汉衷华脑机融合科技发展有限公司 | Micro-needle and flat cable inverse welding connecting structure and preparation process thereof |
| US12434315B2 (en) | 2022-07-25 | 2025-10-07 | Wuhan Neuracom Technology Development Co., Ltd. | Reverse soldering connection structure of microneedle and wiring and preparation process therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114284390B (en) | 2024-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1965414B (en) | Photodiode and method for manufacturing the same | |
| CN104538480B (en) | High Speed I nGaAs photoelectric detector chip upside-down mounting integrated morphology and manufacture method | |
| CN112234118B (en) | Micro array light transceiving integrated chip for visible light communication and manufacturing method | |
| CN111418074B (en) | Optical semiconductor device | |
| WO2005093857A1 (en) | Semiconductor light detecting element and manufacturing method thereof | |
| CN114284390A (en) | Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof | |
| US20080265357A1 (en) | Semiconductor optical receiver device, optical receiver module, and method for manufacturing semiconductor optical receiver device | |
| CN108847416B (en) | Absorption-enhanced grating-coupled silicon-based photodetector and preparation method thereof | |
| JP2004200202A (en) | Semiconductor light receiving element | |
| JPH04246868A (en) | P-i-n photodiode and method of improving efficiency thereof | |
| JPH05129638A (en) | Optical semiconductor device | |
| CN104576808A (en) | High-speed avalanche photodetector chip with carrier and manufacturing method for high-speed avalanche photodetector chip | |
| CN112768550A (en) | Structure for improving responsivity of back-illuminated photodiode and manufacturing method | |
| JP2005129689A (en) | Semiconductor light receiving element and light receiving module | |
| JP4279650B2 (en) | Semiconductor photo detector | |
| JP3008571B2 (en) | Light receiving device | |
| CN114420714A (en) | On-chip integrated spectrometer and its fabrication method and electronic device | |
| JP6660282B2 (en) | Light receiving element | |
| CN118198080B (en) | Avalanche diode array device integrated with planar lens and preparation method thereof | |
| US20120176680A1 (en) | Patterned backside optical coating on transparent substrate | |
| CN114400235B (en) | A back-illuminated light detection array structure and preparation method thereof | |
| CN118519231B (en) | A heterogeneous integrated optoelectronic chip based on optically penetrating substrate channels | |
| US20140319677A1 (en) | Submount for electronic, optoelectronic, optical, or photonic components | |
| Makiuchi et al. | Flip-chip planar GaInAs/InP pin photodiodes-fabrication and characteristics | |
| JP2005129776A (en) | Semiconductor light receiving element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |