CN114284405B - Light emitting diode and preparation method thereof - Google Patents
Light emitting diode and preparation method thereof Download PDFInfo
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Abstract
The application relates to a light-emitting diode and a preparation method thereof. The preparation method of the light-emitting diode comprises the following steps: providing a substrate; forming an epitaxial structure on the upper surface of the substrate, wherein the epitaxial structure comprises a first limiting material layer and a light-emitting layer, and the light-emitting layer is positioned on the upper surface of the first limiting material layer; in is contained In the first limiting material layer, and the In composition gradually changes along the thickness direction of the first limiting material layer; processing the first limiting material layer, and consuming part of the first limiting material layer to form a first limiting region and a first limiting layer, wherein the first limiting region is positioned on the periphery of the first limiting layer; the surface size of the first limiting layer close to the light-emitting layer is smaller than that of the light-emitting layer and smaller than that of the first limiting layer away from the light-emitting layer. The preparation method of the light-emitting diode can improve the injection efficiency of the current carrier and enhance the expansion effect of the current carrier in other functional layers.
Description
Technical Field
The application relates to the field of semiconductor devices, in particular to a light-emitting diode and a preparation method thereof.
Background
The novel GaN-based Micro-LED display based on the third-generation semiconductor material has the excellent characteristics of high luminous efficiency, high brightness, short response time and good reliability, and is known as a next-generation display technology for displaying the LCD and the OLED.
In recent years, micro-LEDs are shown to be a hot research direction, and are highly valued in domestic and foreign industries and academia, and in addition, the photoelectric modulation bandwidth of the Micro-LEDs reaches GHz, which is far higher than that of illumination LEDs, so that the Micro-LEDs have the advantage of high-speed parallel visible light communication.
However, some problems still remain to be solved when Micro-LEDs are currently applied to display technology. As the device size decreases, the external quantum efficiency of the Micro-LED decreases sharply, the surface area to volume ratio increases, and the surface damage of the side wall of the device is serious due to cutting, resulting in current leakage and attenuation of the external quantum efficiency, and affecting the photoelectric characteristics of the device.
Disclosure of Invention
Based on this, it is necessary to provide a light emitting diode and a method for manufacturing the same in order to solve the above-mentioned problems.
The application discloses a preparation method of a light-emitting diode, which comprises the following steps: providing a substrate; forming an epitaxial structure on the upper surface of the substrate, wherein the epitaxial structure comprises a first limiting material layer and a light-emitting layer, and the light-emitting layer is positioned on the upper surface of the first limiting material layer; in is contained In the first limiting material layer, and the In component gradually changes along the thickness direction of the first limiting material layer; processing the first limiting material layer, and consuming part of the first limiting material layer to form a first limiting area and a first limiting layer, wherein the first limiting area is positioned on the periphery of the first limiting layer; the surface size of the first limiting layer close to the light-emitting layer is smaller than the size of the light-emitting layer and smaller than the surface size of the first limiting layer away from the light-emitting layer.
According to the preparation method of the light-emitting diode, the first limiting material layer with the gradually changed In component is formed, the corrosion resistance or oxidation resistance of the first limiting material layer is influenced by the In component, the etching speed or oxidation speed of different positions In the first limiting material layer is changed, the first limiting layer with the inclined side face can be formed after the first limiting material layer is etched, the contact area between the first limiting layer and the light-emitting layer is reduced, meanwhile, the contact area between the first limiting layer and the first doped nitride layer (such as an n-type nitride layer) is kept to be larger, carriers can be effectively limited In the middle area of the light-emitting layer during carrier injection, the capture of side wall defects on the carriers is reduced, the carrier injection efficiency is improved, and the expansion effect of the carriers In other functional layers can be improved.
In one embodiment, the In composition In the first confinement material layer gradually increases from a surface facing away from the light-emitting layer to a surface near the light-emitting layer.
In one embodiment, processing the first confinement material layer to consume a portion of the first confinement material layer to form the first confinement region and the first confinement layer includes: etching the first limiting material layer, and consuming part of the first limiting material layer to form a first limiting region and a first limiting layer; or oxidizing the first limiting material layer to consume part of the first limiting material layer to form a first limiting region and a first limiting layer.
In one embodiment, the epitaxial structure further includes a nitride buffer layer, an undoped nitride layer, a nitride layer of a first doping type, and a nitride layer of a second doping type, and the epitaxial structure is formed on the upper surface of the substrate, including: forming a nitride buffer layer on the upper surface of the substrate; forming an undoped nitride layer on the upper surface of the nitride buffer layer; forming a nitride layer of a first doping type on the upper surface of the undoped nitride layer; forming a first limiting material layer on the upper surface of the nitride layer with the first doping type; forming a light-emitting layer on the upper surface of the first limiting material layer; a nitride layer of a second doping type is formed over the light emitting layer.
In one embodiment, after forming the light emitting layer on the upper surface of the first confinement layer, before forming the nitride layer of the second doping type over the light emitting layer, the method further includes: and forming a second limiting material layer on the upper surface of the light-emitting layer, wherein In is contained In the second limiting material layer, and the composition of In gradually increases from the surface away from the light-emitting layer to the surface close to the light-emitting layer.
In one embodiment, the first confinement material layer further comprises, prior to processing: the epitaxial structure is etched to form a mesa structure.
In one embodiment, processing the first confinement material layer while processing the second confinement material layer includes: and consuming part of the second limiting material layer to form a second limiting region and a second limiting layer, wherein the second limiting region is positioned at the periphery of the second limiting layer, and the surface size of the second limiting layer close to the light emitting layer is smaller than that of the light emitting layer and smaller than that of the second limiting layer away from the light emitting layer.
By forming the second limiting layer and the second limiting region on the upper surface of the light-emitting layer, the first limiting layer can limit carriers in the middle region of the light-emitting layer together, so that the injection efficiency of the carriers is further improved, and current leakage and external quantum efficiency attenuation caused by damage to the side wall of the device are improved.
The application also discloses a light emitting diode, which comprises: a substrate; the epitaxial structure is positioned on the upper surface of the substrate and comprises a first limiting layer and a light-emitting layer, and the light-emitting layer is positioned on the upper surface of the first limiting layer; the surface size of the first limiting layer close to the light-emitting layer is smaller than that of the light-emitting layer and smaller than that of the first limiting layer away from the light-emitting layer.
According to the light-emitting diode, the first limiting layer is arranged on the lower surface of the light-emitting layer, the surface size of the first limiting layer, which is close to the light-emitting layer, is smaller than that of the light-emitting layer, and is smaller than that of the first limiting layer, which is away from the light-emitting layer, so that carrier injection is effectively limited in the middle area of the light-emitting layer, capture of side wall defects to carriers is greatly reduced, carrier injection efficiency and quantum efficiency are improved, and current leakage and external quantum efficiency attenuation caused by damage to the side wall surface of a device due to cutting are improved. And, because the surface size of the first limiting layer, which faces away from the light-emitting layer, is larger, the expansion effect of carriers in other functional layers can be enhanced.
In one embodiment, the epitaxial structure further comprises: a nitride buffer layer on the upper surface of the substrate; the undoped nitride layer is positioned on the upper surface of the nitride buffer layer; a first doped nitride layer located on the upper surface of the undoped nitride layer and contacting the lower surface of the first limiting layer; and a nitride layer of a second doping type over the light emitting layer.
In one embodiment, the epitaxial structure further comprises a second confinement layer between the light emitting layer and the nitride layer of the second doping type; the surface dimension of the second limiting layer close to the light emitting layer is smaller than the dimension of the light emitting layer and smaller than the surface dimension of the second limiting layer away from the light emitting layer.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a light emitting diode according to an embodiment of the application.
FIG. 2 is a schematic cross-sectional view of a semiconductor structure after forming a nitride buffer layer on an upper surface of a substrate according to an embodiment of the present application.
FIG. 3 is a schematic cross-sectional view of a semiconductor structure after forming an undoped nitride layer on an upper surface of a nitride buffer layer according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure after forming a nitride layer of a first doping type on an upper surface of an undoped nitride layer according to an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a semiconductor structure after forming a first limiting material layer on an upper surface of a nitride layer of a first doping type according to an embodiment of the present application.
Fig. 6a is a schematic cross-sectional view of a semiconductor structure after forming a light emitting layer on an upper surface of a first confinement material layer according to an embodiment of the application.
Fig. 6b is a schematic cross-sectional view of a semiconductor structure after forming a light emitting layer on an upper surface of a first confinement material layer according to another embodiment of the application.
Fig. 7 is a schematic cross-sectional view of a semiconductor structure after forming a second limiting material layer on an upper surface of a light emitting layer according to an embodiment of the application.
Fig. 8 is a schematic cross-sectional view of a semiconductor structure after forming a nitride quantum barrier layer on an upper surface of a second confinement material layer according to an embodiment of the application.
Fig. 9 is a schematic cross-sectional view of a semiconductor structure after forming a low temperature p-type layer and an electron blocking layer in accordance with an embodiment of the present application.
Fig. 10 is a schematic cross-sectional view of a semiconductor structure after forming a nitride layer of a second doping type according to an embodiment of the present application.
Fig. 11 is a schematic cross-sectional view of a semiconductor structure after forming a mesa structure in accordance with an embodiment of the present application.
Fig. 12a and 12b are schematic cross-sectional views of a semiconductor structure after forming a first confinement layer and a second confinement layer in accordance with an embodiment of the application.
Fig. 13a and 13b are schematic cross-sectional views of a semiconductor structure after forming a first confinement layer and a second confinement layer in accordance with another embodiment of the application.
Fig. 14 and 15 are schematic cross-sectional views of a light emitting diode with a confinement layer prepared by a conventional method.
Fig. 16 is a schematic cross-sectional view of a conventionally prepared light emitting diode with an unlimited layer.
Reference numerals illustrate:
10. a substrate; 21. a first layer of confinement material; 211. a first confinement layer; 212. a first confinement region; 22. a light emitting layer; 221. a nitride quantum barrier layer; 222. a nitride quantum well layer; 23. a nitride buffer layer; 24. an undoped nitride layer; 25. a nitride layer of a first doping type; 26. a second layer of confinement material; 261. a second confinement layer; 262. a second confinement region; 27. a low temperature p-type layer; 28. an electron blocking layer; 29. a nitride layer of a second doping type.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, when an element such as a layer, film or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or intervening film layers may also be present, unless otherwise indicated. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Where the terms "comprising," "having," and "including" are used herein, another component may also be added unless explicitly defined as such, e.g., "consisting of … …," etc. Unless mentioned to the contrary, singular terms may include plural and are not to be construed as being one in number.
As shown in fig. 1, an embodiment of the present application provides a method for manufacturing a light emitting diode, including:
s10: a substrate is provided.
S20: forming an epitaxial structure on the upper surface of the substrate, wherein the epitaxial structure comprises a first limiting material layer and a light-emitting layer, and the light-emitting layer is positioned on the upper surface of the first limiting material layer; in is contained In the first limiting material layer, and the composition of In is gradually changed along the thickness direction of the first limiting material layer.
S30: processing the first limiting material layer, and consuming part of the first limiting material layer to form a first limiting area and a first limiting layer, wherein the first limiting area is positioned on the periphery of the first limiting layer; the surface size of the first limiting layer close to the light-emitting layer is smaller than the size of the light-emitting layer and smaller than the surface size of the first limiting layer away from the light-emitting layer.
In step S10, the substrate may be a sapphire, silicon carbide, gallium nitride, gallium oxide, zinc oxide, or aluminum nitride substrate. For example, the substrate may be subjected to a temperature of 1200 ℃ H prior to forming the epitaxial structure 2 The surface cleaning treatment is performed in an atmosphere, and the treatment time is, for example, 5 minutes.
In step S20, the first confinement material layer may be an In-containing nitride confinement layer, such as an AlInN layer. Illustratively, the first limiting material layer is a compositionally graded AlInN layer, and the composition of In is graded along the thickness direction of the first limiting material layer. Illustratively, the In composition varies from 0 to 0.5.
In some embodiments, the In composition In the first confinement material layer increases gradually from a surface facing away from the light-emitting layer to a surface near the light-emitting layer. The surface of the first limiting material layer close to the light-emitting layer is taken as a first surface, and the surface of the first limiting material layer away from the light-emitting layer is taken as a second surface. As an example, the In composition at the first surface is 0.34, and the In composition at the second surface is 0. The In composition decreases linearly from the first surface to the second surface. Alternatively, the In composition at the first surface and the second surface may also be other values. Alternatively, the In composition variation between the first surface and the second surface may also be nonlinear. As an example, the average value of the In composition In the first limiting material layer is 0.17.
By way of example, the light emitting layer may be a nitride quantum well layer, such as an InGaN quantum well layer. Alternatively, the light emitting layer may be a nitride quantum barrier layer and a nitride quantum well layer sequentially stacked from bottom to top, for example, a GaN quantum barrier layer and an InGaN quantum well layer sequentially stacked from bottom to top. In some embodiments, the light emitting layer may also be a nitride quantum barrier layer and a nitride quantum well layer that are periodically stacked alternately. For example, a plurality of periodic structures may be cyclically prepared as the light emitting layer, wherein a single periodic structure includes a GaN quantum barrier layer and an InGaN quantum well layer stacked in order from bottom to top. For example, the light emitting layer may include 1 to 30 periodic structures composed of a GaN quantum barrier layer and an InGaN quantum well layer.
In some embodiments, the epitaxial structure includes, in addition to the first confinement material layer and the light emitting layer, a nitride buffer layer, an undoped nitride layer, a nitride layer of a first doping type, and a nitride layer of a second doping type. The step of forming an epitaxial structure on the upper surface of the substrate may include:
s21: a nitride buffer layer 23 is formed on the upper surface of the substrate 10 as shown in fig. 2.
Illustratively, the substrate 10 is placed in an H2 atmosphere, and the growth temperature is set to 600℃, the growth pressure is set to 650mbar, a 25nm undoped GaN layer is grown on the surface of the substrate 10 as a nitride buffer layer 23, with TMG source as the Ga source.
S22: an undoped nitride layer 24 is formed on the upper surface of the nitride buffer layer 23 as shown in fig. 3.
Illustratively, a 2.5 μm undoped nitride layer 24, such as an undoped GaN layer, is grown on the surface of the nitride buffer layer 23. Specifically, the Ga source required for growth is a TMG source, the growth atmosphere is an H2 atmosphere, the growth temperature is 1215 ℃, and the growth pressure is 300mbar.
S23: a nitride layer 25 of the first doping type is formed on the upper surface of the undoped nitride layer 24 as shown in fig. 4.
By way of example, the nitride layer 25 of the first doping type may be an n-type nitride layer, such as an n-type GaN layer. As an example, an n-type GaN layer of 2.5 μm can be grown on the surface of the undoped GaN layer, specifically, the Ga source required for growth is TMG source, the growth atmosphere is H2 atmosphere, the growth temperature is 1210 ℃, the growth pressure is 150mbar, and the doping concentration of Si is 5×10 18 cm -3 。
S24: a first limiting material layer 21 is formed on the upper surface of the first doping type nitride layer 25 as shown in fig. 5.
For example, the growth atmosphere may be switched to an N2 atmosphere, and an AlInN layer of 5nm may be grown on the upper surface of the N-type nitride layer as the first limiting material layer 21 under the condition of a temperature of 750 ℃. In the growth of the first limiting material layer 21, the supply amount of In at the initial stage is 0 or less, and then the supply amount of In is gradually increased, and an AlInN layer In which the In composition gradually changes can be formed. Illustratively, the surface of the first confinement material layer 21 adjacent to the nitride layer 25 of the first doping type has a smaller In composition and the surface of the first confinement material layer 21 facing away from the nitride layer 25 of the first doping type has a larger In composition.
S25: a light emitting layer 22 is formed on the upper surface of the first confinement material layer 21 as shown in fig. 6 a.
For example, the growth temperature may be raised to 950 ℃ after the AlInN layer is produced, and the growth atmosphere is maintained at N 2 Providing TEGa as Ga source in the atmosphere, and growing a GaN quantum barrier layer of 8nm on the upper surface of the AlInN layer; and then reducing the growth temperature to 850 ℃, providing TMIn as an In source, and growing a 3nm InGaN quantum well layer on the surface of the GaN quantum barrier layer. The GaN quantum barrier layer and the InGaN quantum well layer stacked in this order from bottom to top together constitute the light emitting layer 22.
Alternatively, in some embodiments, the above steps may be repeated to periodically alternately generate GaN quantum barrier layers and InGaN quantum well layers, as shown in fig. 6 b. Illustratively, one periodic structure includes a single-layer GaN quantum barrier layer and a single-layer InGaN quantum well layer, and the light-emitting layer 22 may include 1-30 periodic structures.
S26: a nitride layer of the second doping type is formed over the light emitting layer 22.
The nitride layer of the second doping type may be a p-type nitride layer, for example a p-type GaN layer. In some embodiments, before forming the nitride layer of the second doping type over the light emitting layer 22, further comprising:
s261: a second confinement material layer 26 is formed on the upper surface of the light-emitting layer 22, as shown in fig. 7.
Illustratively, at N 2 In the atmosphere at 750 ℃, an AlInN layer of 5nm was formed on the upper surface of the light-emitting layer 22 as the second limiting material layer 26. In the growth process of the second limiting material layer 26, the supply amount of In is large In the initial stage, and then the supply amount of In is gradually reduced, thereby forming an AlInN layer In which the In composition is graded. Illustratively, the surface of the second confinement material layer 26 adjacent to the light-emitting layer 22 has a larger In composition and the surface of the second confinement material layer 26 facing away from the light-emitting layer 22 has a smaller In composition.
Optionally, in some embodiments, before forming the second limiting material layer 26, the growth temperature is raised to 950 ℃, the growth pressure is adjusted to 400mbar, and a nitride quantum barrier layer 221 is formed on the upper surface of the light emitting layer 22 by using TEGa as a Ga source, as shown in fig. 8. The newly formed nitride quantum barrier layer 221 also belongs to the light emitting layer 22.
Optionally, in some embodiments, as shown in fig. 9, after forming the second limiting material layer 26, before forming the second doping type nitride layer, further includes:
s262: a low temperature p-type layer 27 is formed on the upper surface of the second confinement material layer 26.
S263: an electron blocking layer 28 is formed on the upper surface of the low temperature p-type layer 27.
Illustratively, in step S262, a p-type layer may be formed on the upper surface of the second confinement material layer 26 using a TMG source as the Ga source in a growth atmosphere of H2 at a growth temperature of 920 ℃The GaN layer serves as a p-type layer 27 in which the doping concentration of Mg is 2×10 19 cm -3 。
In step S263, an electron blocking layer 28 having a thickness of 25nm is grown on the upper surface of the low temperature p-type layer 27, and the electron blocking layer 28 may be a 25nm p-type doped AlGaN layer, for example. Specifically, the Ga source is a TMG source, the Al source is TMAL, and the growth atmosphere is N 2 The atmosphere, the growth temperature, and the growth pressure were 1000℃and 150mbar.
As shown in fig. 10, a nitride layer 29 of a second doping type is formed on the upper surface of the electron blocking layer 28. Illustratively, a 45nm p-type GaN layer is formed on the upper surface of the electron blocking layer 28. Specifically, the Ga source required for growth is a TMG source, and the growth atmosphere is switched to H 2 Atmosphere, growth temperature of 1100 ℃, growth pressure of 500mbar and Mg doping concentration of 5×10 19 cm -3 。
In step S30, the first confinement material layer 21 is processed to consume a portion of the first confinement material layer 21 to form a first confinement region and a first confinement layer.
Optionally, in some embodiments, before the first limiting material layer 21 is processed, further comprising:
s31: the epitaxial structure is etched to form a mesa structure, as shown in fig. 11.
For example, an n-type nitride mesa structure may be formed by mesa etching the epitaxial structure using an inductively coupled plasma process (Inductive Coupled Plasma, ICP). The depth of etching is from the upper surface of the nitride layer 29 of the second doping type to the upper surface of the nitride layer 25 of the first doping type.
After forming the mesa structure, the step of processing the first limiting material layer 21 includes:
s32: the first confinement material layer 21 is etched, and a portion of the first confinement material layer 21 is consumed to form a first confinement region 212 and a first confinement layer 211, as shown in fig. 12 a.
For example, the first limiting material layer 21 may be etched using a wet etching process. For example, the first limiting material layer 21 is etched using a DEA (diethanolamine) solution having a characteristic of selectively laterally etching an AlInN material, a peripheral portion of the first limiting material layer 21 may be removed to form a first limiting region 212, and the remaining AlInN layer serves as the first limiting layer 211. Wherein the In composition In the first limiting material layer 21 gradually increases from a surface facing away from the light emitting layer 22 to a surface near the light emitting layer 22. The higher the In composition, the weaker the corrosion resistance of the AlInN layer, and the lower the In composition, the stronger the corrosion resistance of the AlInN layer. Therefore, when the first limiting material layer 21 is wet etched using the DEA solution, the portion near the light emitting layer 22 is etched at a faster rate, and the portion away from the light emitting layer 22 is etched at a slower rate, thereby forming the first limiting layer 211 as shown in fig. 12 a. Wherein, the surface size of the first confinement layer 211 near the light emitting layer 22 is smaller than the surface size of the first confinement layer 211 away from the light emitting layer 22.
In some other embodiments, the step of processing the first layer of confinement material 21 includes:
s32': the first confinement material layer 21 is subjected to an oxidation treatment, and a part of the first confinement material layer 21 is consumed to form a first confinement region 212 and a first confinement layer 211, as shown in fig. 12 b.
For example, the mesa structure may be subjected to oxidation treatment with an acidic solution or an alkaline solution, and the peripheral region of the first confinement material layer 21 is oxidized to form a first confinement region 212, and the non-oxidized portion serves as the first confinement layer 211. Wherein the In composition In the first limiting material layer 21 gradually increases from a surface facing away from the light emitting layer 22 to a surface near the light emitting layer 22. The higher the In component, the weaker the oxidation resistance of the AlInN layer, and the lower the In component, the stronger the oxidation resistance of the AlInN layer. Therefore, when the mesa structure is subjected to oxidation treatment using an acidic solution or an alkaline solution, the portion close to the light emitting layer 22 is etched at a faster rate, and the portion away from the light emitting layer 22 is etched at a slower rate, thereby forming the first confinement layer 211 as shown in fig. 12 b. Wherein, the surface size of the first confinement layer 211 near the light emitting layer 22 is smaller than the surface size of the first confinement layer 211 away from the light emitting layer 22.
According to the preparation method of the light-emitting diode, by forming the first limiting material layer 21 with the gradual change of the In component and changing the etching speed or the oxidation speed of different positions In the first limiting material layer 21 by utilizing the influence of the In component on the corrosion resistance or the oxidation resistance of the first limiting material layer 21, the first limiting layer 211 with an inclined side surface can be formed after the first limiting material layer 21 is etched, the contact area between the first limiting layer 211 and the light-emitting layer 22 is reduced, and meanwhile, the first limiting layer 211 and the first doping type nitride layer 25 (such as an n-type nitride layer) have a larger contact area, so that the carrier injection can be effectively limited In the middle area of the light-emitting layer 22, the capture of the carrier caused by side wall defects is greatly reduced, the carrier injection efficiency is improved, and the expansion effect of the carrier In other functional layers is improved.
In some embodiments, please continue with fig. 12a and 12b, processing the first confinement material layer 21 while processing the second confinement material layer 26 includes: a portion of the second confinement material layer 26 is consumed to form a second confinement region 262 and a second confinement layer 261, the second confinement region 262 is located at the periphery of the second confinement layer 261, and the size of the second confinement layer 261 is smaller than the size of the light emitting layer 22.
When the etching process in step 32 or the oxidation process in step 32' is performed on the mesa structure as a whole, the peripheral portion of the second confinement material layer 26 is also removed or oxidized, forming the second confinement region 262 and the second confinement layer 261. Similarly, since the composition of In the second confinement material layer 26 gradually increases from the surface facing away from the light-emitting layer 22 to the surface near the light-emitting layer 22, the second confinement layer 261 shown In fig. 12a or 12b may be formed after the etching treatment In step 32 or the oxidation treatment In step 32'.
Similar to the effect of the first confinement layer 211, the second confinement layer 261 may confine carriers to the middle region of the light emitting layer 22, further improve the injection efficiency of carriers, improve current leakage and external quantum efficiency attenuation caused by damage to the device sidewall, and simultaneously maintain a larger contact area between the second confinement layer 261 and the low-temperature p-type layer 27, so that the expansion effect of carriers is better.
In some other embodiments, the first confinement material layer 21 may include a first sub-material layer having a higher In composition near the light-emitting layer 22 and a second sub-material layer having a lower In composition away from the light-emitting layer 22. After the first confinement material layer 21 is subjected to the etching treatment in step 32 or the oxidation treatment in step 32', a first confinement layer 211 as shown in fig. 13a or 13b can be obtained.
In some other embodiments, the second confinement material layer 26 may include a third sub-material layer having a higher In composition near the light-emitting layer 22 and a fourth sub-material layer having a lower In composition away from the light-emitting layer 22. After the second confinement material layer 26 has been subjected to the etching treatment in step 32 or the oxidation treatment in step 32', a second confinement layer 261 as shown in fig. 13a or 13b can be obtained.
According to the preparation method of the light-emitting diode, the first limiting layer 211 and the second limiting layer 261 with the trapezoid side surface structures are formed, so that carriers can be limited in the middle area of the light-emitting layer 22, the injection efficiency of the carriers is further improved, current leakage and external quantum efficiency attenuation caused by damage to the side wall of the device are improved, and meanwhile, the larger contact area between the limiting layer and the p-type nitride layer and the n-type nitride layer is kept, so that the expansion effect of the carriers is better.
Alternatively, in some embodiments, the first and second confinement material layers 21 and 26 may include N sub-material layers, N being 3 or more. Wherein the sub-material layer closest to the light emitting layer 22 has the largest In composition, and the sub-material layer farthest from the light emitting layer 22 has the smallest In composition, and the In composition of the sub-material layer therebetween varies linearly. After the first and second confining material layers 21 and 26 are subjected to etching and oxidation treatment, a first confining layer 211 and a second confining layer 261 having stepped sides are formed.
Preferably, the method for manufacturing the light emitting diode can be applied to a chip manufacturing process with a size of less than or equal to 100 μm by 100 μm, and particularly when the chip size is less than or equal to 60 μm by 60 μm, the method can play a great advantage in terms of quantum efficiency and brightness.
An embodiment of the present application also discloses a light emitting diode, as shown in fig. 12a or 12b, comprising: a substrate 10; an epitaxial structure on the upper surface of the substrate 10, the epitaxial structure including a first confinement layer 211 and a light emitting layer 22, the light emitting layer 22 being on the upper surface of the first confinement layer 211; wherein, the surface dimension of the first confinement layer 211 near the light emitting layer 22 is smaller than the dimension of the light emitting layer 22, and smaller than the surface dimension of the first confinement layer 211 away from the light emitting layer 22.
The substrate 10 may be, for example, a sapphire substrate 10 or other substrate 10. The first confinement layer 211 may be an AlInN layer. As shown in fig. 12a and 12b, the first confinement layer 211 has inclined sides, and the area of the first confinement layer 211 in contact with the light emitting layer 22 is smaller than the area of the first confinement layer 211 in contact with the nitride layer 25 of the first doping type. The light emitting layer 22 may be a nitride quantum barrier layer 221 and a nitride quantum well layer 222, which are sequentially stacked from bottom to top, such as a GaN quantum barrier layer and an InGaN quantum well layer, which are sequentially stacked from bottom to top.
Alternatively, the light emitting layer 22 may also be a nitride quantum barrier layer 221 and a nitride quantum well layer 222 which are periodically stacked alternately. For example, if a single periodic structure is a GaN quantum barrier layer and an InGaN quantum well layer stacked from bottom to top, the light emitting layer 22 may include 1 to 30 periodic structures composed of a GaN quantum barrier layer and an InGaN quantum well layer.
In the light emitting diode, the first confinement layer 211 is disposed on the lower surface of the light emitting layer 22, and the surface dimension of the first confinement layer 211, which is close to the light emitting layer 22, is smaller than the dimension of the light emitting layer 22, so that carrier injection is effectively confined in the middle region of the light emitting layer 22, capturing of carrier by side wall defects is greatly reduced, carrier injection efficiency and quantum efficiency are improved, and current leakage and external quantum efficiency attenuation caused by damage to the side wall surface of the device due to cutting are improved. Meanwhile, a larger contact area is maintained between the first confinement layer 211 and the nitride layer 25 of the first doping type, and an extension effect of carriers can be enhanced.
In one embodiment, referring to fig. 12a or 12b, the epitaxial structure further comprises: a nitride buffer layer 23 on the upper surface of the substrate 10; an undoped nitride layer 24 on an upper surface of the nitride buffer layer 23; a first doping type nitride layer 25 on the upper surface of the undoped nitride layer 24 and in contact with the lower surface of the first confinement layer 211; and a nitride layer 29 of a second doping type over the light emitting layer 22.
Illustratively, the nitride buffer layer 23 and the undoped nitride layer 24 are undoped GaN layers, and the formation conditions and thickness of the two layers are different. As an example, the thickness of the nitride buffer layer may be 25nm and the thickness of the undoped nitride layer 24 is 2.5 μm. The nitride layer 25 of the first doping type may be an n-type nitride layer, such as an n-type GaN layer. As an example, the thickness of the nitride layer 25 of the first doping type may be 2.5 μm, the doping concentration of Si 5×10 18 cm -3 . The nitride layer 29 of the second doping type may be a p-type nitride layer, such as a p-type GaN layer. As an example, the thickness of the nitride layer 29 of the second doping type may be 45nm, with a mg doping concentration of 5×10 19 cm -3 。
In one embodiment, with continued reference to fig. 12a or 12b, the epitaxial structure further includes a second confinement layer 261 between the light emitting layer 22 and the nitride layer 29 of the second doping type; the surface dimension of the second confinement layer 261 near the light-emitting layer 22 is smaller than the dimension of the light-emitting layer 22, and smaller than the surface dimension of the second confinement layer 261 facing away from the light-emitting layer 22.
The second confinement layer 261 and the first confinement layer 211 together may confine carriers to the middle region of the light emitting layer 22, further improve the injection efficiency of carriers, and improve current leakage and external quantum efficiency attenuation caused by device sidewall damage. And, the second confinement layer 261 and the low-temperature p-type layer 27 maintain a larger contact area therebetween, so that the carrier expansion effect can be better.
Alternatively, in some embodiments, the first confinement layer 211 and the second confinement layer 261 have stepped sides, as shown in fig. 13a and 13 b. The contact area between the first confinement layer 211 and the second confinement layer 261 and the light-emitting layer is smaller, so that carriers can be better confined in the middle area of the light-emitting layer 22, and the carrier injection efficiency is improved; the larger contact area between the first confinement layer 211 and the first doping type nitride layer 25 and the larger contact area between the second confinement layer 261 and the low temperature p-type layer 27 can enhance the carrier expansion effect.
Fig. 14, 15 and 16 are comparative examples of the embodiments of the present application, and fig. 14 and 15 are light emitting diodes having a confinement layer prepared using a conventional preparation method, and fig. 16 is a light emitting diode having an unlimited layer. The dimensions of the first confinement layer and the second confinement layer in fig. 14 and 15 are the same as the dimensions of the upper surface of the first confinement layer 211 in fig. 12a and 12b, and the dimensions of the lower surface of the second confinement layer 261 in fig. 12a and 12 b.
The light emitting diodes shown in fig. 12a, 12b, 14, 15 and 16 of the examples of the present application were manufactured to have two dimensions of 100 μm by 100 μm and 60 μm by 60 μm, and the light intensities were tested under test conditions of 1mA and 2mA of current, respectively, and the results are shown in table 1.
TABLE 1
As can be seen from table 1, the light emitting diode in the embodiment of the present application has a larger light intensity and a better light emitting effect than the light emitting diode in fig. 14, 15 and 16 under the same current driving. Specifically, the surface dimensions of the first confinement layer 211 and the second confinement layer 261 in fig. 12a and fig. 12b, which are close to the light-emitting layer 22, are smaller than the dimensions of the light-emitting layer 22, so that the contact area between the confinement layer and the light-emitting layer can be reduced, the carrier injection is effectively confined in the middle area of the light-emitting layer, the capture of the carrier by the side wall defect is reduced, and the carrier injection efficiency is improved; and the surface of the first confinement layer 211 and the second confinement layer 261 facing away from the light emitting layer 22 has a larger contact area with other functional layers, so that the spreading effect of carriers in the other functional layers can be improved.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (9)
1. A method of manufacturing a light emitting diode, comprising:
providing a substrate;
forming an epitaxial structure on the upper surface of the substrate, wherein the epitaxial structure comprises a first limiting material layer and a light-emitting layer, and the light-emitting layer is positioned on the upper surface of the first limiting material layer; wherein In is contained In the first limiting material layer;
processing the first limiting material layer, and consuming part of the first limiting material layer to form a first limiting area and a first limiting material layer, wherein the first limiting area is positioned on the periphery of the first limiting material layer; wherein the surface dimension of the first confinement material layer near the light-emitting layer is smaller than the dimension of the light-emitting layer and smaller than the surface dimension of the first confinement material layer away from the light-emitting layer;
wherein an In composition In the first limiting material layer gradually increases from a surface facing away from the light emitting layer to a surface near the light emitting layer.
2. The method of claim 1, wherein the processing the first confinement material layer to consume a portion of the first confinement material layer to form a first confinement region and a first confinement material layer comprises:
etching the first limiting material layer, consuming a portion of the first limiting material layer to form the first limiting region and the first limiting material layer; or (b)
And oxidizing the first limiting material layer to consume part of the first limiting material layer to form the first limiting region and the first limiting material layer.
3. The method of claim 2, wherein the epitaxial structure further comprises a nitride buffer layer, an undoped nitride layer, a nitride layer of a first doping type, and a nitride layer of a second doping type, and wherein the forming the epitaxial structure on the upper surface of the substrate comprises:
forming the nitride buffer layer on the upper surface of the substrate;
forming the undoped nitride layer on the upper surface of the nitride buffer layer;
forming a nitride layer of the first doping type on the upper surface of the undoped nitride layer;
forming the first limiting material layer on the upper surface of the first doping type nitride layer;
forming the light emitting layer on the upper surface of the first limiting material layer;
and forming a nitride layer of the second doping type above the light-emitting layer.
4. The method of claim 3, further comprising, after forming the light emitting layer on the upper surface of the first limiting material layer, before forming a nitride layer of a second doping type over the light emitting layer:
and forming a second limiting material layer on the upper surface of the light-emitting layer, wherein In is contained In the second limiting material layer, and the composition of In gradually increases from the surface away from the light-emitting layer to the surface close to the light-emitting layer.
5. The method of claim 4, further comprising, prior to the processing the first confinement material layer:
the epitaxial structure is etched to form a mesa structure.
6. The method of claim 5, wherein processing the first confinement material layer and simultaneously processing the second confinement material layer comprises:
and consuming part of the second limiting material layer to form a second limiting region and a second limiting material layer, wherein the second limiting region is positioned at the periphery of the second limiting material layer, and the surface size of the second limiting material layer close to the light-emitting layer is smaller than the size of the light-emitting layer and smaller than the surface size of the second limiting material layer away from the light-emitting layer.
7. A light emitting diode, comprising:
a substrate;
the epitaxial structure is positioned on the upper surface of the substrate and comprises a first limiting material layer and a light-emitting layer, and the light-emitting layer is positioned on the upper surface of the first limiting material layer;
wherein the surface dimension of the first confinement material layer near the light-emitting layer is smaller than the dimension of the light-emitting layer and smaller than the surface dimension of the first confinement material layer away from the light-emitting layer; in is contained In the first limiting material layer, and the In component In the first limiting material layer gradually increases from the surface away from the light-emitting layer to the surface close to the light-emitting layer.
8. The light emitting diode of claim 7, wherein the epitaxial structure further comprises:
a nitride buffer layer on the upper surface of the substrate;
an undoped nitride layer located on an upper surface of the nitride buffer layer;
a nitride layer of a first doping type on an upper surface of the undoped nitride layer and in contact with a lower surface of the first limiting material layer; and
a nitride layer of a second doping type is located over the light emitting layer.
9. The light emitting diode of claim 8, wherein the epitaxial structure further comprises a second layer of confinement material between the light emitting layer and the nitride layer of the second doping type;
the surface dimension of the second limiting material layer close to the light-emitting layer is smaller than the dimension of the light-emitting layer and smaller than the surface dimension of the second limiting material layer away from the light-emitting layer.
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