CN114296896A - Method, device, computer storage medium and terminal for realizing command scheduling - Google Patents

Abstract

Disclosed herein are a method, an apparatus, a computer storage medium and a terminal for implementing command scheduling, including: determining whether a first position for inserting a first command exists in a command queue when a Dynamic Random Access Memory (DRAM) receives the first command; when a first location exists, determining whether the first location passes a consistency conflict check; inserting a first command into a first location that passes a consistency conflict check; wherein the first command comprises: a read command or a write command. The embodiment of the invention carries out insertion processing after the consistency conflict check on the newly received first command under the condition of not carrying out read-write grouping on the command queue, thereby improving the read-write performance of a System On Chip (SOC).

Description

A method, device, computer storage medium and terminal for realizing command scheduling

technical field

This article relates to, but is not limited to, SoC technology, especially a method, device, computer storage medium, and terminal for implementing command scheduling.

Background technique

With the increasing scale of the system on chip (SOC), more and more modules such as central processing unit (CPU) and data processing unit (DPU) are integrated in the SOC; the efficiency of the system to execute the DRAM cache of each module, It will directly affect the overall performance of the SOC.

The dynamic random access memory (DRAM) controller is the basic component for parsing and processing SOC bus commands. It mainly schedules read and write commands according to the read and write classification or queue rearrangement technology; among them, the read and write classification in the related art, fixed rules And the queue scheduling strategy of strongly coupled logic; the complexity of the current scheduling strategy is getting higher and higher, and there are problems such as low flexibility, tight logic coupling and poor compatibility; it has become a major problem in the design of current DRAM controllers.

SUMMARY OF THE INVENTION

The following is an overview of the topics detailed in this article. This summary is not intended to limit the scope of protection of the claims.

Embodiments of the present invention provide a method, a device, a computer storage medium and a terminal for implementing command scheduling, which can improve the data read and write performance of the system on chip.

An embodiment of the present invention provides a method for implementing command scheduling, including:

When the dynamic random access memory DRAM receives a new first command, determine whether the dynamic random access memory DRAM receives the first command in the command queue, and determine whether there is a first position in the command queue for inserting the first command;

When the first position exists, determine whether the first position passes the consistency conflict check;

inserting the first command into the first position that passes the consistency conflict check;

Wherein, the first command includes: a read command or a write command.

On the other hand, an embodiment of the present invention further provides a computer storage medium, where a computer program is stored in the computer storage medium, and when the computer program is executed by a processor, the above method for implementing command scheduling is implemented.

In another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor, where a computer program is stored in the memory; wherein,

the processor is configured to execute the computer program in the memory;

The computer program, when executed by the processor, implements the method for implementing command scheduling as described above.

In another aspect, an embodiment of the present invention further provides an apparatus for implementing command scheduling, including: a location determination unit, a conflict checking unit, and an insertion processing unit; wherein,

The determining position unit is set to: when the first command is received, determine whether there is a first position for inserting the first command in the command queue;

The conflict checking unit is set to: when the first position exists, determine whether the first position passes the consistency conflict check;

The insertion processing unit is set to: insert the first command into the first position that has passed the consistency conflict check;

Wherein, the first command includes: a read command or a write command.

The technical solution of the present application includes: when the dynamic random access memory (DRAM) receives the first command, determining whether there is a first position for inserting the first command in the command queue; when the first position exists, determining whether the first position passes the Consistency conflict check; insert the first command into the first position that passes the consistency conflict check; wherein the first command includes: a read command or a write command. When the embodiment of the present invention does not perform read and write grouping on the command queue, the newly received first command is checked for consistency conflict and then inserted, thereby improving the read and write performance of the system on chip (SOC).

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. They are used to explain the technical solutions of the present invention together with the embodiments of the present application, and do not limit the technical solutions of the present invention.

1 is a flowchart of a method for implementing command scheduling according to an embodiment of the present invention;

2 is a schematic diagram of a first position according to an embodiment of the present invention;

3 is a schematic diagram of a first position according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of a first position according to yet another embodiment of the present invention;

5 is a schematic diagram of inserting a fourth command according to an embodiment of the present invention;

6 is a schematic diagram of inserting a fourth command according to another embodiment of the present invention;

7 is a schematic diagram of a data cache according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of alarm processing according to an embodiment of the present invention;

FIG. 9 is a structural block diagram of an apparatus for implementing command scheduling according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

FIG. 1 is a flowchart of a method for implementing command scheduling according to an embodiment of the present invention, as shown in FIG. 1 , including:

Step 101, when the dynamic random access memory (DRAM) receives the first command, determine whether there is a first position for inserting the first command in the command queue;

In an exemplary example, the first command in the embodiment of the present invention includes a newly received command.

In an exemplary example, the embodiment of the present invention determines whether there is a first position in the command queue for inserting the first command, including:

In order from the tail of the command queue to the head, it is determined whether there is a first position in the command queue for inserting the first command.

Step 102, when the first position exists, determine whether the first position passes the consistency conflict check;

Step 103, inserting the first command into the first position that has passed the consistency conflict check;

Wherein, the first command includes: a read command or a write command.

It should be noted that, in the embodiment of the present invention, the read command and the write command in the command queue are processed serially, so only one first command is processed in one command scheduling.

When the embodiment of the present invention does not perform read and write grouping on the command queue, the newly received first command is checked for consistency conflict and then inserted, thereby improving the read and write performance of the system on chip (SOC).

In an exemplary example, the embodiment of the present invention determines whether there is a first position in the command queue for inserting the first command, including:

When there is a command conforming to a page hit (Page Hit, accessing the same bank (Bank) or row (Row)) in the command queue, the position after the command conforming to the page hit is determined as the first position;

When there are two commands with bank conflict (Bank Conflict) in the command queue, the middle position of the two commands with bank conflict is determined as the first position;

It should be noted that the two fourth commands with a group conflict should be adjacent commands, and only the adjacent commands may have a group conflict.

When there are two adjacent commands with the same operation type in the command queue, the middle position of the two adjacent commands with the same operation type is determined as the first position;

Among them, the operation type includes: read operation and write operation.

For the difference in determining the first position, a brief description is given below through an example; FIG. 2 is a schematic diagram of the first position according to an embodiment of the present invention, as shown in FIG. 2 , WR in WR_Bx_Rx_Cx in the figure represents a write operation, Bx represents xBank, Rx Represents the xth row, Cx represents the xth column, the above command means to write the x row and x column of the xbank; RD in RD_Bx_Rx_Cx means read, and the above command means to read the x row and x column of the xbank; Indicates that there are three determined first positions of commands that conform to the Page Hit; wherein, the first position of the identifier 1 is close to the head of the command queue, and when the first command insertion processing is performed, the priority of the first position of the identifier 1 is greater than The priority of the first position of the identification 2; the priority of the first position of the identification 2 is greater than the priority of the first position of the identification 3; when the consistency conflict check is performed, the embodiments of the present invention follow the above priorities from high to high The lower order is judged one by one.

FIG. 3 is a schematic diagram of the first position of another embodiment of the present invention. As shown in FIG. 3 , the marks 1, 2 and 3 in the figure respectively represent the first position when there are three two commands with group conflicts; mark 1 is close to In the head of the command queue, when the first command insertion processing is performed, the priority of the first position of ID 1 is greater than the priority of the first position of ID 2; the priority of the first position of ID 2 is greater than the priority of the first position of ID 3 The priority of a position; when performing the consistency conflict check, the embodiment of the present invention performs judgment processing one by one according to the above-mentioned priority from high to low.

FIG. 4 is a schematic diagram of the first position of still another embodiment of the present invention, as shown in FIG. 4 , the marks 1, 2 and 3 in the figure respectively represent the first position when there are two commands with the same operation type and adjacent to each other; ID 1 is close to the head of the command queue, and when the first command is inserted, the priority of the first position of ID 1 is greater than the priority of the first position of ID 2; the priority of the first position of ID 2 is greater than that of ID 2 The priority of the first position of 3; when performing the consistency conflict check, the embodiment of the present invention performs judgment processing one by one according to the above-mentioned priority from high to low.

In an exemplary example, the embodiment of the present invention may determine the first position only based on the judgment of whether there is a command that matches the page hit; in an exemplary example, the embodiment of the present invention may only determine the first position based on whether there is a group conflict The first position is determined by judging the two commands; in an exemplary example, the embodiment of the present invention can determine the first position according to the judgment of whether there are two adjacent commands of the same operation type and the order of the adjacent commands. In an exemplary example, the embodiment of the present invention may be selected from the judgments of whether there is a command that matches a page hit, whether there are two commands that have a group conflict, and whether there are two adjacent commands that have the same operation type and are adjacent to each other. Two, according to the order of whether there is a command that matches the page hit, whether there are two commands with a group conflict, and whether there are two adjacent commands with the same operation type, the judgment processing of the first position is executed sequentially. In an exemplary example, the embodiment of the present invention can judge whether there is a command that matches a page hit, whether there are two commands with group conflicts, and whether there are two adjacent commands with the same operation type, according to : Whether there is a command that matches the page hit, whether there are two commands with a group conflict, and whether there is an order of two adjacent commands with the same operation type, execute the judgment processing of the first position one by one.

In an exemplary example, the embodiment of the present invention determines whether the first location passes the consistency conflict check, including:

According to the sequence from the head to the tail of the command queue, the first position is checked for the consistency conflict between the first command and the second command;

When the first command and the second command pass the consistency conflict check, determine that the first position passes the consistency conflict check;

Wherein, the second command includes: a read command and/or a write command adjacent to the first position.

It should be noted that the consistency conflict check in the embodiment of the present invention is based on the address of the module and the attribute definition of read and write, and may include: module address conflict and/or read and write conflict; for example, according to the data processing process of the module, preset Therefore, once the read and write sequence does not conform to the preset, it is considered that there is a conflict. In an exemplary example, the rules for consistency conflicts in the embodiments of the present invention may be set by those skilled in the art according to implementation scenarios. In an exemplary example, the modules in this embodiment of the present invention include modules such as a central processing unit (CPU), a data processing unit (DPU), and a display module integrated in the SOC, which need to read and write data through DRAM; In this exemplary example, the embodiment of the present invention can distinguish each module in the SOC by a preset number, distinguish the command and address of each module based on the number, and then perform a consistency conflict check. When the consistency conflict detection in the embodiment of the present invention determines that there is a consistency conflict, the first position is deleted from the position where the first instruction can be inserted.

In an exemplary example, the embodiment of the present invention inserts the first command into the first position that passes the consistency conflict check, including:

Insert the first command in the first position closest to the head of the command queue that passes the consistency conflict check.

In an exemplary example, the embodiment of the present invention may also insert the first command into another first position that passes the consistency conflict check. Inserting the first command into the first position that is closest to the head of the command queue and passes the consistency conflict check improves the processing efficiency of the first command, and also avoids any problems caused by the position where the first command is inserted when inserting subsequent commands. Timing (later received commands inserted before the first) issue.

In an exemplary embodiment, the method according to the embodiment of the present invention further includes:

When it is determined that the first position for inserting the first command does not exist in the command queue, the first command is written to the tail of the command queue.

In this embodiment of the present invention, when the first position does not exist, the order of the command queue is kept unchanged, and the newly added first command is written to the tail of the command queue.

In an exemplary embodiment, the method according to the embodiment of the present invention further includes:

set a timeout threshold for more than one third command in the command queue;

When the third command is not executed within the timeout threshold, the third command is inserted into the head of the command queue.

In an exemplary example, in this embodiment of the present invention, a technician may set a timeout threshold according to a system application; for example, the access unique identifier (ID) of the sixth command is a read operation of the display module (Display), which can be set according to the Display The resolution dynamically configures the timeout threshold. The setting of the timeout threshold in the embodiment of the present invention can be understood as a timeout mechanism or an aging mechanism, and by setting the timeout threshold, the blocking of commands with time limit requirements is avoided.

In an exemplary embodiment, the method according to the embodiment of the present invention further includes:

determining a fourth command in the command queue that can be operated in parallel;

Insert more than one fourth command that can be operated in parallel within the first delay interval of the bank conflict (Bank Conflict) of the first fourth command;

Wherein, the fourth command includes: a multi-group (Muti-Bank) command and/or a group (BankGroup) command; the first fourth command includes: a fourth command close to the head of the command queue; more than one inserted can operate in parallel The fourth command includes: other parallel operable fourth commands except the first fourth command; the cumulative sum of the second delay intervals of the group conflicts of the inserted more than one parallel operable fourth commands is less than the first a delay interval.

In an exemplary example, the embodiment of the present invention may use the DRAM usage scenario of the embodiment of the present invention to set a fixed number of fourth commands that can be operated in parallel within the first delay interval; for example, insert two parallel-operable fourth commands; The fourth command of the operation. Directly setting a fixed number can reduce the calculation steps of the accumulated sum of the second delay interval and improve the processing speed. In an exemplary example, the embodiment of the present invention may search for the fourth command that can be operated in parallel in order from the head to the tail. The fourth commands that can be operated in parallel may include multiple groups, and the embodiment of the present invention performs the foregoing processing for each group of fourth commands respectively. In an exemplary example, the inserted one or more fourth commands that can be operated in parallel are fourth commands determined according to the order of the command queue, that is, the order of the inserted fourth commands in the command queue is consistent with that before the uninserted commands.

FIG. 5 is a schematic diagram of inserting a fourth command according to an embodiment of the present invention. As shown in FIG. 5 , the timing parameter in FIG. 5 is a parameter defined by the JEDEC standard. The embodiment of the present invention hides the write operation of B4-R3 in B0 within the first delay interval (group conflict period) of the group conflict; the embodiment of the present invention reads or writes subsequent groups that can operate in parallel according to the isolation operation attribute between group conflicts (the feature that requires long delay and waiting). The command is executed in advance to the first delay interval of the group conflict; the delay of the group conflict is hidden in parallel.

The processing of inserting the fourth command in the embodiment of the present invention can avoid designing a complex logic mechanism of queue insertion sorting, and reduce the logic coupling degree of the DRAM. In an exemplary example, when the operation performed by the fourth command in the embodiment of the present invention is a write operation, the first delay interval of the group conflict of the write operation is TCFH=tWR+tRP+tRCD; wherein, tWR represents the write recovery time , tRP represents the precharge time, and tRCD represents the activation time. The above-mentioned time information can be obtained from the JEDEC handbook of the Joint Electronic Device Engineering Committee. Correspondingly, the number of multiple groups of write commands inserted theoretically = the first delay interval/(data bus (DQ) conflict length (Burst Length)/2), here, it should be noted that, but the command queue contains many When the number of group write commands is less than the calculated number of commands that can be inserted, only multiple groups of write commands included in the command queue are inserted; FIG. 6 is a schematic diagram of inserting a fourth command according to another embodiment of the present invention, as shown in FIG. 6 As shown, the timing parameters in FIG. 6 are parameters defined by the JEDEC standard. Compared with FIG. 5, the embodiment of the present invention inserts three more sets of commands in the first delay interval. Embodiments improve the bandwidth utilization of the data bus.

In an exemplary example, after inserting more than one fourth command that can be operated in parallel, the method according to the embodiment of the present invention further includes:

Performing a consistency conflict check with the fifth command for each of the more than one fourth commands that can be operated in parallel;

When the fourth command and the fifth command pass the consistency conflict check, the data operation is performed according to the fourth command when the fourth command is read;

When the fourth command and the fifth command fail the consistency conflict check, the activation operation is performed on the fourth command when the fourth command is read;

Wherein, the fifth command includes: the first command in the command queue after the fourth command that can be operated in parallel.

In an exemplary embodiment, the method according to the embodiment of the present invention further includes:

When it is determined that the addresses of N commands in the command queue are continuous according to the address information of the command, the data of the N+1th address is read, and the read data and address information are cached in the preset cache area;

When an instruction containing the N+1th address is received, the cached data is read from the cache area according to the address information.

In the embodiment of the present invention, by judging the continuity of the addresses of the commands, when the addresses of the N commands are continuous, the data of the N+1th address is read to realize the pre-reading of the data; FIG. 7 is an embodiment of the present invention. The schematic diagram of the data cache, as shown in Figure 7, the pre-read address is Bank2-Row1-Col4; the data in the pre-read corresponding DRAM address is stored in the buffer (Buffer) and the address information of the data is recorded; if the subsequent If there is no write operation to this address, the Buffer has always been the latest data. If the write operation reaches this address, the write data in the Buffer will be updated. If the new read command hits the Buffer, the data will be read directly from the Buffer, and there is no need to read data from the DRAM particles.

It should be noted that the address continuity in the embodiment of the present invention includes: the group and row addresses are the same, and the column addresses are continuous; for example, bank1-row1-c1->bank1-row1-c2->bank1-row1-c3->bank1-row1-c4 ; The value of N is set by the user according to the application scenario of DRAM. The cache depth D can be set by the user according to system performance and application requirements; in an exemplary embodiment, the embodiment of the present invention can perform simulation through batch performance tests to determine reasonable values of D and N, so that the system can achieve performance optimal.

In an exemplary embodiment, the method according to the embodiment of the present invention further includes:

When the data cached in the cache area has not been read or updated within a preset period of time, delete the data;

When the data cached in the cache area has not been read within a preset period of time but is updated, after the data is output to the DRAM, the data output to the DRAM in the cache area is deleted.

In an exemplary example, the preset duration in this embodiment of the present invention may be set by those skilled in the art based on empirical values.

In an exemplary embodiment, the method according to the embodiment of the present invention further includes:

determining whether the first command is inserted at the first position;

When the first command is not inserted into the first position, alarm processing is performed.

By setting a self-check function in the embodiment of the present invention, when a problem including a logical operation error occurs, causing the first command to not be inserted into the first position, alarm processing is performed; FIG. 8 is a schematic diagram of the alarm processing according to the embodiment of the present invention, as shown in FIG. 8 . As shown in the figure, when no other group command is inserted between the two group conflicts, alarm processing is performed; in an exemplary example, performing the alarm processing in this embodiment of the present invention includes: generating an error report according to the fact that the first command is not inserted into the first position , the generated error report is fed back to the user through system messages, emails or other means, or the module that automatically handles the alarm is set in the system; the user or the module that automatically handles the alarm executes according to the received error report, including: closing: Insert functions, etc.

The embodiment of the present invention determines the first position where the first command can be inserted, realizes the rearrangement of the command queue, and avoids read and write conflicts through consistency conflict checking; and through the setting of the timeout threshold, it avoids the occurrence of excessively long waiting times for commands. question. By inserting the fourth command that can be operated in parallel into the interval time between group conflicts, the complexity and coupling degree of command scheduling are simplified, and the execution efficiency of the DRAM is improved. By judging the continuity of the address, data pre-reading is performed, so that less queue resources are used, and better read efficiency can be achieved in the case of continuous reading; the embodiment of the present invention realizes real-time queue scheduling problems through alarm processing. Discovery provides a basis for timely adjustment of command scheduling.

An embodiment of the present invention further provides a computer storage medium, where a computer program is stored in the computer storage medium, and the above method for implementing command scheduling is implemented when the computer program is executed by a processor.

An embodiment of the present invention further provides a terminal, including: a memory and a processor, and a computer program is stored in the memory; wherein,

the processor is configured to execute the computer program in the memory;

When the computer program is executed by the processor, the method for implementing command scheduling as described above is implemented.

FIG. 9 is a structural block diagram of an apparatus for implementing command scheduling according to an embodiment of the present invention. As shown in FIG. 9 , it includes: a location determination unit, a conflict checking unit, and an insertion processing unit; wherein,

The determining position unit is set to: when the first command is received, determine whether there is a first position for inserting the first command in the command queue;

The conflict checking unit is set to: when the first position exists, determine whether the first position passes the consistency conflict check;

The insertion processing unit is set to: insert the first command into the first position that has passed the consistency conflict check;

Wherein, the first command includes: a read command or a write command.

When the embodiment of the present invention does not perform read and write grouping on the command queue, the newly received first command is checked for consistency conflict and then inserted, thereby improving the read and write performance of the system on chip (SOC).

In an exemplary example, the embodiment of the present invention determines that the location unit is set to:

When there is a command matching the page hit in the command queue, the position after the command matching the page hit is determined as the first position;

When there are two commands with group conflict in the command queue, the middle position of the two commands with group conflict is determined as the first position;

When there are two adjacent commands with the same operation type in the command queue, the middle position of the two adjacent commands with the same operation type is determined as the first position; wherein the operation types include: read operation and write operation.

In an exemplary embodiment, the conflict checking unit in the embodiment of the present invention is set to:

According to the sequence from the head to the tail of the command queue, the first position is checked for the consistency conflict between the first command and the second command;

When the first command and the second command pass the consistency conflict check, determine that the first position passes the consistency conflict check;

Wherein, the second command includes: a read command and/or a write command adjacent to the first position.

In an exemplary embodiment, the insertion processing unit according to the embodiment of the present invention is configured as:

Insert the first command in the first position closest to the head of the command queue that passes the consistency conflict check.

In an exemplary embodiment, the insertion processing unit according to the embodiment of the present invention is further configured to:

When the position determining unit determines that the first position for inserting the first command does not exist in the command queue, the first command is written to the tail of the command queue.

In an exemplary embodiment, the apparatus according to the embodiment of the present invention further includes a timeout processing unit, which is set to:

A timeout threshold is set for more than one third command in the command queue; when the third command is not executed within the timeout threshold, the third command is inserted into the head of the command queue.

In an exemplary embodiment, the apparatus according to the embodiment of the present invention further includes a parallel processing unit, configured as:

determining a fourth command that can be operated in parallel in the command queue; inserting more than one fourth command that can be operated in parallel within the first delay interval of the group conflict of the first fourth command;

Wherein, the fourth command includes: multiple groups of commands and/or group commands; the first fourth command includes: a fourth command close to the head of the command queue; the inserted more than one fourth command that can be operated in parallel includes: A fourth command other than the fourth command that can be operated in parallel; the cumulative sum of the second delay interval of the group conflict of the inserted one or more fourth commands that can be operated in parallel is smaller than the first delay interval.

In an exemplary example, the parallel processing unit in the embodiment of the present invention is further configured as:

Performing a consistency conflict check with the fifth command for each of the more than one fourth commands that can be operated in parallel;

When the fourth command and the fifth command pass the consistency conflict check, the data operation is performed according to the fourth command when the fourth command is read;

When the fourth command and the fifth command fail the consistency conflict check, the activation operation is performed on the fourth command when the fourth command is read;

Wherein, the fifth command includes: the first command in the command queue after the fourth command that can be operated in parallel.

In an exemplary embodiment, the device according to the embodiment of the present invention further includes a pre-reading unit, configured as:

When it is determined that the addresses of N commands in the command queue are continuous according to the address information of the command, the data of the N+1th address is read, and the read data and address information are cached in the preset cache area;

When an instruction containing the N+1th address is received, the cached data is read from the cache area according to the address information.

In an exemplary embodiment, the pre-reading unit in the embodiment of the present invention is further set to:

When the data cached in the cache area has not been read or updated within a preset period of time, delete the data;

When the data cached in the cache area has not been read within a preset period of time but is updated, after the data is output to the DRAM, the data output to the DRAM in the cache area is deleted.

In an exemplary example, the apparatus according to the embodiment of the present invention further includes an alarm unit, which is set to:

It is determined whether the first command is inserted into the first position; when the first command is not inserted into the first position, alarm processing is performed.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, functional modules/units in the systems, and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

Claims (14)

1. A method for implementing command scheduling, comprising: When the dynamic random access memory DRAM receives the first command, determine whether there is a first position for inserting the first command in the command queue; When the first position exists, determine whether the first position passes the consistency conflict check; inserting the first command into the first position that passes the consistency conflict check; Wherein, the first command includes: a read command or a write command. 2. The method according to claim 1, wherein the determining whether there is a first position for inserting the first command in the command queue comprises: When there is a command conforming to the page hit in the command queue, the position after the command conforming to the page hit is determined as the first position; When there are two commands with group conflict in the command queue, the middle position of the two commands with group conflict is determined as the first position; When there are two adjacent commands with the same operation type in the command queue, the middle position of the two adjacent commands with the same operation type is determined as the first position; Wherein, the operation types include: read operation and write operation. 3. The method according to claim 1, wherein the determining whether the first position passes the consistency conflict check comprises: According to the sequence from the head to the tail of the command queue, the first position is checked for consistency conflict between the first command and the second command; When the first command and the second command pass the consistency conflict check, determine that the first position passes the consistency conflict check; Wherein, the second command includes: a read command and/or a write command adjacent to the first position. 4. The method according to claim 1, wherein the inserting the first command into the first position that passes the consistency conflict check comprises: Inserting the first command into the first position closest to the head of the command queue that passes the consistency conflict check. 5. The method according to any one of claims 1 to 4, wherein the method further comprises: When it is determined that the first position for inserting the first command does not exist in the command queue, the first command is written to the tail of the command queue. 6. The method according to any one of claims 1 to 4, wherein the method further comprises: setting a timeout threshold for more than one third command in the command queue; When the third command is not executed within the timeout threshold, the third command is inserted into the head of the command queue. 7. The method according to any one of claims 1 to 4, wherein the method further comprises: determining a fourth command in the command queue that can operate in parallel; Inserting more than one fourth command that can be operated in parallel within the first delay interval of the group conflict of the first fourth command; Wherein, the fourth command includes: multiple groups of commands and/or group commands; the first fourth command includes: a fourth command close to the head of the command queue; The four commands include: other fourth commands that can be operated in parallel except the first fourth command; the accumulated sum of the second delay intervals of the group conflicts of the inserted one or more fourth commands that can be operated in parallel, less than the first delay interval. 8. The method according to claim 7, wherein after inserting more than one fourth command that can be operated in parallel, the method further comprises: Performing a consistency conflict check with the fifth command for each of the more than one fourth commands that can be operated in parallel; When the fourth command and the fifth command pass the consistency conflict check, the data operation is performed according to the fourth command when the fourth command is read; When the fourth command and the fifth command fail the consistency conflict check, perform an activation operation on the fourth command when reading the fourth command; Wherein, the fifth command includes: a first command in the command queue after the one or more parallel operable fourth commands. 9. The method according to any one of claims 1 to 4, wherein the method further comprises: According to the address information of the command, when it is determined that the addresses of N commands in the command queue are continuous, the data of the N+1th address is read, and the read data and address information are cached in a preset cache area; When an instruction including the N+1 th address is received, the cached data is read from the cache area according to the address information. 10. The method according to claim 9, wherein the method further comprises: When the data cached in the cache area has not been read or updated within a preset period of time, delete the data; When the data cached in the cache area has not been read within a preset period of time but is updated, after the data is output to the DRAM, the data output to the DRAM in the cache area is deleted. 11. The method according to any one of claims 1 to 4, wherein the method further comprises: determining whether the first command is inserted into the first location; When the first command is not inserted into the first position, alarm processing is performed. 12 . A computer storage medium, wherein a computer program is stored in the computer storage medium, and when the computer program is executed by a processor, the method for implementing command scheduling according to any one of claims 1 to 11 is implemented. 13. A terminal, comprising: a memory and a processor, wherein a computer program is stored in the memory; wherein, the processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, the method for implementing command scheduling according to any one of claims 1 to 11 is implemented. 14. An apparatus for implementing command scheduling, comprising: a location determination unit, a conflict checking unit, and an insertion processing unit; wherein, The determining position unit is set to: when the first command is received, determine whether there is a first position for inserting the first command in the command queue; The conflict checking unit is set to: when the first position exists, determine whether the first position passes the consistency conflict check; The insertion processing unit is set to: insert the first command into the first position that has passed the consistency conflict check; Wherein, the first command includes: a read command or a write command.

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