CN114301428B - Latch Circuit - Google Patents
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- CN114301428B CN114301428B CN202111675445.6A CN202111675445A CN114301428B CN 114301428 B CN114301428 B CN 114301428B CN 202111675445 A CN202111675445 A CN 202111675445A CN 114301428 B CN114301428 B CN 114301428B
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Abstract
本发明涉及一种锁存电路。包括：传输模块，包括第一输出端和第二输出端，所述第一输出端用于根据输入信号输出第一电平状态的第一信号，所述第二输出端用于根据所述输入信号输出第二电平状态的第二信号，所述第一电平状态和第二电平状态不同；输出模块，分别与所述第一输出端、所述第二输出端连接，用于根据所述第一信号和所述第二信号生成输出信号；反馈控制模块，分别与所述输出模块的输出端、所述第一输出端、所述第二输出端连接，用于根据所述输出信号、所述第一信号及所述第二信号控制所述第一输出端的电平状态为所述第一电平状态，及控制所述第二输出端的电平状态为所述第二电平状态。
The present invention relates to a latch circuit, comprising: a transmission module, comprising a first output terminal and a second output terminal, wherein the first output terminal is used to output a first signal of a first level state according to an input signal, and the second output terminal is used to output a second signal of a second level state according to the input signal, wherein the first level state and the second level state are different; an output module, connected to the first output terminal and the second output terminal respectively, and used to generate an output signal according to the first signal and the second signal; and a feedback control module, connected to the output terminal of the output module, the first output terminal, and the second output terminal respectively, and used to control the level state of the first output terminal to be the first level state, and control the level state of the second output terminal to be the second level state according to the output signal, the first signal, and the second signal.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a latch circuit.
Background
As the feature size of integrated circuits continues to decrease, the supply voltage and logic gate node capacitance also continue to decrease, and the circuits become more and more sensitive to radiation. The reduction in supply voltage and node capacitance results in a reduction in the amount of charge stored on the node, making the circuit susceptible to radiation-induced soft errors. When a high energy particle, such as alpha or neutron, hits an off-state transistor in the timing circuit, it will disturb the logic value stored by the node to its complement. This phenomenon occurring in sequential logic circuits is known as Single Event Upset (SEU).
The intermediate and output nodes of conventional CMOS latch circuits are very sensitive to radiation effects. When a high energy particle strikes any of the sensitive nodes described above, the logical value of the striking node may change to its complement. Due to the circuit structure of the latch, the logic level change of any sensitive node will be transferred to the other node through the feedback path between the two inverters, thereby causing the wrong logic to pass and ultimately affecting the output logic value of the latch.
The amount of charge that a high energy particle deposits in a sensitive node and causes a single event upset is referred to as critical charge. The critical charge depends on the capacitance of the node and the supply voltage of the circuit. These two parameters decrease as the scale of integrated circuit technology increases, and thus the critical charge of the sensitive node also gradually decreases. Thus, a lower energy particle striking the sensitive node may result in a single particle flip. A typical technique for SEU reinforcement of latches is triple modular redundant latches (TMR), in which three parallel latches and a voter circuit are used to eliminate the problem of single event upset. However, while TMR may completely prevent the occurrence of single event upset events, this technique may result in higher power consumption, larger area overhead, and higher latency. And, the triple modular redundant latch has only three nodes inside the latch fully immune to SEU, and single event upset may still occur when the energetic particles bombard the voter circuit. Therefore, how to reduce power consumption, delay and area overhead as much as possible on the basis of maintaining SEU immunity is a problem to be solved.
Disclosure of Invention
Accordingly, it is necessary to provide a latch circuit capable of reducing power consumption of the latch circuit while eliminating single event upset of each node in the latch circuit.
The present application provides a latch circuit including:
The transmission module comprises a first output end and a second output end, wherein the first output end is used for outputting a first signal in a first level state according to an input signal, and the second output end is used for outputting a second signal in a second level state according to the input signal, and the first level state and the second level state are different;
the output module is respectively connected with the first output end and the second output end and is used for generating output signals according to the first signals and the second signals;
and the feedback control module is respectively connected with the output end, the first output end and the second output end of the output module and is used for controlling the level state of the first output end to be the first level state and controlling the level state of the second output end to be the second level state according to the output signals, the first signals and the second signals.
In one embodiment, the transmission module includes:
The input end of the first transmission circuit is used for receiving the input signal, the output end of the first transmission circuit is the first output end and is used for outputting a first signal in a first level state according to the input signal under the control of a control signal;
The input end of the second transmission circuit is used for receiving the input signal, the output end of the second transmission circuit is the second output end, and the second transmission circuit is used for outputting a second signal in a second level state according to the input signal under the control of the control signal.
In one embodiment, the first transmission circuit includes:
The input end of the first transmission gate is used for receiving the input signal, the controlled end of the first transmission gate is used for receiving the control signal, and the output end of the first transmission gate is the first output end.
In one embodiment, the second transmission circuit includes:
the input end of the second transmission gate is used for receiving the input signal, and the controlled end of the second transmission gate is used for receiving the control signal;
and the input end of the inverter is connected with the output end of the second transmission gate, and the output end of the inverter is the second output end.
In one embodiment, the output module includes:
The first end of the first pull-up circuit is connected with the first output end, and the second end of the first pull-up circuit is connected with the second output end;
the first end of the first pull-down circuit is connected with the first output end, the second end of the first pull-down circuit is connected with the second output end, and the third end of the first pull-down circuit is connected with the third end of the first pull-up circuit so as to jointly output the output signal.
In one embodiment, the first pull-up circuit includes:
A first transistor, a first end of which is connected with a power supply voltage, and a control end of which is connected with the second output end;
and the first end of the second transistor is connected with the second end of the first transistor, the control end of the second transistor is connected with the first output end, and the second end of the second transistor is the third end of the first pull-up circuit.
In one embodiment, the first pull-down circuit includes:
A third transistor, a first end of which is a third end of the first pull-down circuit, and a control end of which is connected with the first output end;
And the first end of the fourth transistor is connected with the second end of the third transistor, the control end of the fourth transistor is connected with the second output end, and the second end of the fourth transistor is grounded.
In one embodiment, the feedback control module includes:
the first feedback circuit is respectively connected with the output end, the second output end and the first output end of the output module and is used for controlling the level state of the first output end to be the first level state according to the output signals and the second signals;
and the second feedback circuit is respectively connected with the output end, the first output end and the second output end of the output module and is used for controlling the level state of the second output end to be the second level state according to the output signals and the first signals.
In one embodiment, the first feedback circuit comprises:
The first end of the second pull-up circuit is connected with the second output end, the second end of the second pull-up circuit is connected with the output end of the output module, and the third end of the second pull-up circuit is connected with the first output end;
the first end of the second pull-down circuit is connected with the second output end, the second end of the second pull-down circuit is connected with the output end of the output module, and the third end of the second pull-down circuit is connected with the first output end.
In one embodiment, the second feedback circuit comprises:
The first end of the third pull-up circuit is connected with the first output end, the second end of the third pull-up circuit is connected with the output end of the output module, and the third end of the third pull-up circuit is connected with the second output end;
the first end of the third pull-down circuit is connected with the first output end, the second end of the third pull-down circuit is connected with the output end of the output module, and the third end of the third pull-down circuit is connected with the second output end.
In the latch circuit, the first output end of the transmission module outputs a first signal in a first level state according to the input signal, the second output end outputs a second signal in a second level state according to the input signal, the output module generates an output signal according to the first signal and the second signal, the feedback control module controls the level state of the first output end to be in the first level state and controls the level state of the second output end to be in the second level state according to the output signal, the first signal and the second signal, the influence of single event upset on the first output end, the second output end and the output end of the output module is eliminated, the function of resisting single event upset of an internal node of the latch circuit is realized, and the latch circuit is simple in structure and low in power consumption.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a block diagram schematically showing a latch circuit in embodiment 1;
FIG. 2 is a block diagram schematically showing a latch circuit according to embodiment 2;
FIG. 3 is a schematic diagram of a latch circuit according to embodiment 1;
FIG. 4 is a schematic diagram of a latch circuit in embodiment 2;
FIG. 5 is a schematic diagram of a latch circuit in embodiment 3;
FIG. 6 is a schematic diagram of a latch circuit according to embodiment 4;
FIG. 7 is a schematic diagram of a latch circuit according to embodiment 5;
Fig. 8 is a schematic diagram of a latch circuit in embodiment 6.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first output may be referred to as a second output, and similarly, a second output may be referred to as a first output, without departing from the scope of the application. Both the first output and the second output are outputs of the transmission module, but they are not the same output.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
Fig. 1 is a block diagram schematically illustrating a latch circuit in embodiment 1, and as shown in fig. 1, in this embodiment, a latch circuit is provided, which includes a transmission module 102, an output module 104, and a feedback control module 106.
The transmission module 102 comprises a first output end 1 and a second output end 2, wherein the first output end 1 is used for outputting a first signal in a first level state according to an input signal D, the second output end 2 is used for outputting a second signal in a second level state according to the input signal D, the first level state and the second level state are different, the level states are divided into a high level state and a low level state, the first level state and the second level state are different, the second level state is a low level state when the first level state is a high level state, and the second level state is a high level state when the first level state is a low level state.
The output module 104 is connected to the first output terminal 1 and the second output terminal 2, respectively, and is configured to generate an output signal Q according to the first signal and the second signal.
The feedback control module 106 is respectively connected to the output end 3, the first output end 1, and the second output end 2 of the output module 104, and is configured to control the level state of the first output end 1 to be the first level state and control the level state of the second output end 2 to be the second level state according to the output signal Q, the first signal, and the second signal.
In the latch circuit, the first output end of the transmission module outputs a first signal in a first level state according to the input signal, the second output end outputs a second signal in a second level state according to the input signal, the output module generates an output signal according to the first signal and the second signal, the feedback control module controls the level state of the first output end to be in the first level state and controls the level state of the second output end to be in the second level state according to the output signal, the first signal and the second signal, the influence of single event upset on the first output end, the second output end and the output end of the output module is eliminated, the function of resisting single event upset of an internal node of the latch circuit is realized, and the latch circuit is simple in structure and low in power consumption.
Fig. 2 is a schematic block diagram of a latch circuit in embodiment 2, as shown in fig. 2, in one embodiment, a transmission module 102 includes a first transmission circuit 202 and a second transmission circuit 204, an input end of the first transmission circuit 202 is configured to receive the input signal D, an output end of the first transmission circuit 202 is the first output end 1, the first transmission circuit 202 is configured to output a first signal in a first level state according to the input signal D under control of a control signal, an input end of the second transmission circuit 204 is configured to receive the input signal D, an output end of the second transmission circuit 204 is the second output end 2, and the second transmission circuit 204 is configured to output a second signal in a second level state according to the input signal D under control of the control signal.
Fig. 3 is a schematic diagram of the latch circuit in embodiment 1, as shown in fig. 3, in one embodiment, the first transmission circuit 202 includes a first transmission gate, an input terminal of the first transmission gate is used for receiving the input signal D, controlled terminals CLKB and CLK of the first transmission gate are used for receiving the control signal, and an output terminal of the first transmission gate is the first output terminal 1. When the controlled terminal CLKB receives a control signal "1" and the controlled terminal CLK receives a control signal "0", the first transmission gate is turned on, and outputs a first signal in a first level state according to the input signal D, and when the controlled terminal CLKB receives a control signal "0" and the controlled terminal CLK receives a control signal "1", the first transmission gate is turned off.
In one embodiment, as shown in fig. 3, the second transmission circuit 204 includes a second transmission gate 302 and an inverter 304, where an input end of the second transmission gate 302 is configured to receive the input signal D, a controlled end of the second transmission gate 302 is configured to receive the control signal, an input end of the inverter 304 is connected to an output end of the second transmission gate 302, and an output end of the inverter 304 is the second output end 2. The controlled terminals CLKB and CLK of the second transmission gate 302 are configured to receive the control signal, when the controlled terminal CLKB receives the control signal "1" and the controlled terminal CLK receives the control signal "0", the second transmission gate 302 is turned on, a signal in a first level state is output to the inverter 304 according to the input signal D, the inverter 304 outputs a second signal in a second level state according to the received signal in the first level state, and when the controlled terminal CLKB receives the control signal "0" and the controlled terminal CLK receives the control signal "1", the second transmission gate 302 is turned off, where the first transmission gate and the second transmission gate receive the same control signal at the same time, i.e., the first transmission gate and the second transmission gate are turned on and off at the same time.
Fig. 4 is a schematic diagram of a latch circuit in embodiment 2, as shown in fig. 4, in one embodiment, the output module 104 includes a first pull-up circuit 206 and a first pull-down circuit 208, a first end of the first pull-up circuit 206 is connected to the first output terminal 1, a second end of the first pull-up circuit 206 is connected to the second output terminal 2, a first end of the first pull-down circuit 208 is connected to the first output terminal 1, a second end of the first pull-down circuit 208 is connected to the second output terminal 2, and a third end of the first pull-down circuit 208 is connected to a third end of the first pull-up circuit 206 to jointly output the output signal Q.
Fig. 5 is a schematic diagram of a latch circuit in embodiment 3, as shown in fig. 5, in one embodiment, the first pull-up circuit 206 includes a first transistor 306 and a second transistor 308, and a first end of the first transistor 206 is connected to a power voltage V1, where the power voltage V1 satisfies that the output Q is high when the first transistor 306 and the second transistor 308 are both turned on, and the output Q is low when the first transistor 306 and the second transistor 308 are turned off. The control terminal of the first transistor 306 is connected to the second output terminal 2, the first terminal of the second transistor 308 is connected to the second terminal of the first transistor 306, the control terminal of the second transistor 308 is connected to the first output terminal 1, and the second terminal of the second transistor 308 is the third terminal of the first pull-up circuit 206.
In one embodiment, the first transistor 306 is a first PMOS transistor, the second transistor 308 is a first NMOS transistor, and at this time, the source of the first PMOS transistor is a first end of the first transistor 306, the gate of the first PMOS transistor is a control end of the first transistor 306, the drain of the first PMOS transistor is a second end of the first transistor 306, the drain of the first NMOS transistor is a first end of the second transistor 308, the gate of the first NMOS transistor is a control end of the second transistor 308, and the source of the first NMOS transistor is a second end of the second transistor 308.
In one embodiment, as shown in fig. 5, the first pull-down circuit 208 includes a third transistor 310 and a fourth transistor 312, wherein a first end of the third transistor 310 is a third end of the first pull-down circuit 208, a control end of the third transistor 310 is connected to the first output terminal 1, a first end of the fourth transistor 312 is connected to a second end of the third transistor 310, a control end of the fourth transistor 312 is connected to the second output terminal 2, and a second end of the fourth transistor 312 is grounded.
In one embodiment, the third transistor 310 is a second PMOS transistor, the fourth transistor 312 is a second NMOS transistor, and at this time, the source of the second PMOS transistor is the first end of the third transistor 310, the gate of the second PMOS transistor is the control end of the third transistor 310, the drain of the second PMOS transistor is the second end of the third transistor 310, the drain of the second NMOS transistor is the first end of the fourth transistor 312, the gate of the second NMOS transistor is the control end of the fourth transistor 312, and the source of the second NMOS transistor is the second end of the fourth transistor 312.
Fig. 6 is a schematic diagram of a latch circuit in embodiment 4, as shown in fig. 6, in one embodiment, the feedback control module 106 includes a first feedback circuit 210 and a second feedback circuit 212, where the first feedback circuit 210 is respectively connected to the output terminal 3, the second output terminal 2 and the first output terminal 1 of the output module 104, and is used for controlling the level state of the first output terminal 1 to be the first level state according to the output signal Q and the second signal, and the second feedback circuit 212 is respectively connected to the output terminal 3, the first output terminal 1 and the second output terminal 2 of the output module 104, and is used for controlling the level state of the second output terminal 2 to be the second level state according to the output signal Q and the first signal. That is, the first feedback circuit 210 locks the level state of the first output terminal 1 to the first level state according to the output signal Q and the second signal, and the second feedback circuit 212 locks the level state of the second output terminal 2 to the second level state according to the output signal Q and the second signal, so as to achieve the purpose of single event upset resistance.
Fig. 7 is a schematic diagram of a latch circuit in embodiment 5, as shown in fig. 7, in one embodiment, the first feedback circuit 210 includes a second pull-up circuit 314 and a second pull-down circuit 316, a first end of the second pull-up circuit 314 is connected to the second output terminal 2, a second end of the second pull-up circuit 314 is connected to the output terminal 3 of the output module 104, a third end of the second pull-up circuit 314 is connected to the first output terminal 1, a first end of the second pull-down circuit 316 is connected to the second output terminal 2, a second end of the second pull-down circuit 316 is connected to the output terminal 3 of the output module 104, and a third end of the second pull-down circuit 316 is connected to the first output terminal 1.
In one embodiment, as shown in fig. 7, the second feedback circuit 212 includes a third pull-up circuit 318 and a third pull-down circuit 320, wherein a first end of the third pull-up circuit 318 is connected to the first output terminal 1, a second end of the third pull-up circuit 318 is connected to the output terminal 3 of the output module 104, a third end of the third pull-up circuit 318 is connected to the second output terminal 2, a first end of the third pull-down circuit 320 is connected to the first output terminal 1, a second end of the third pull-down circuit 320 is connected to the output terminal 3 of the output module 104, and a third end of the third pull-down circuit 320 is connected to the second output terminal 2.
Fig. 8 is a schematic diagram of a latch circuit in embodiment 6, as shown in fig. 8, in one embodiment, the second pull-up circuit 314 includes a fifth transistor 402 and a sixth transistor 404, wherein a first terminal of the fifth transistor 402 is connected to a power voltage V2, and the power voltage V2 is such that the first output terminal 1 is locked in a high-level state when the fifth transistor 402 and the sixth transistor 404 are both turned on, and the first output terminal 1 is locked in a low-level state when the fifth transistor 402 and the sixth transistor 404 are turned off. The control terminal of the fifth transistor 402 is connected to the second output terminal 2, the first terminal of the sixth transistor 404 is connected to the second terminal of the fifth transistor 402, the control terminal of the sixth transistor 404 is connected to the output terminal 3 of the output module 104, and the second terminal of the sixth transistor 404 is connected to the first output terminal 1.
In one embodiment, the fifth transistor 402 is a third PMOS transistor, the sixth transistor 404 is a third NMOS transistor, and at this time, the source of the third PMOS transistor is the first end of the fifth transistor 402, the gate of the third PMOS transistor is the control end of the fifth transistor 402, the drain of the third PMOS transistor is the second end of the fifth transistor 402, the drain of the third NMOS transistor is the first end of the sixth transistor 404, the gate of the third NMOS transistor is the control end of the sixth transistor 404, and the source of the third NMOS transistor is the second end of the sixth transistor 404.
In one embodiment, as shown in fig. 8, the second pull-down circuit 316 includes a seventh transistor 406 and an eighth transistor 408, wherein a first end of the seventh transistor 406 is connected to the first output terminal 1, a control end of the seventh transistor 406 is connected to the output terminal 3 of the output module 104, a first end of the eighth transistor 408 is connected to a second end of the seventh transistor 406, a control end of the eighth transistor 408 is connected to the second output terminal 2, and a second end of the eighth transistor 408 is grounded.
In one embodiment, the seventh transistor 406 is a fourth PMOS transistor, the eighth transistor 408 is a fourth NMOS transistor, and at this time, the source of the fourth PMOS transistor is the first end of the seventh transistor 406, the gate of the fourth PMOS transistor is the control end of the seventh transistor 406, the drain of the fourth PMOS transistor is the second end of the seventh transistor 406, the drain of the fourth NMOS transistor is the first end of the eighth transistor 408, the gate of the fourth NMOS transistor is the control end of the eighth transistor 408, and the source of the fourth NMOS transistor is the second end of the eighth transistor 408.
As shown in fig. 8, in one embodiment, the third pull-up circuit 318 includes a ninth transistor 410 and a tenth transistor 412, wherein a first terminal of the ninth transistor 410 is connected to a power supply voltage V3, wherein the power supply voltage V3 satisfies that the second output terminal 2 is locked in a high-level state when both the ninth transistor 410 and the tenth transistor 412 are turned on, and the second output terminal 2 is locked in a low-level state when both the ninth transistor 410 and the tenth transistor 412 are turned off. The control terminal of the ninth transistor 410 is connected to the output terminal 3 of the output module 104, the first terminal of the tenth transistor 412 is connected to the second terminal of the ninth transistor 410, the control terminal of the tenth transistor 412 is connected to the first output terminal 1, and the second terminal of the tenth transistor 412 is connected to the second output terminal 2.
In one embodiment, the ninth transistor 410 is a fourth PMOS transistor, the ninth transistor 410 is a fifth PMOS transistor, at this time, the source of the fourth PMOS transistor is the first end of the ninth transistor 410, the gate of the fourth PMOS transistor is the control end of the ninth transistor 410, the drain of the fourth PMOS transistor is the second end of the ninth transistor 410, the source of the fifth PMOS transistor is the first end of the tenth transistor 412, the gate of the fifth PMOS transistor is the control end of the tenth transistor 412, and the drain of the fifth PMOS transistor is the second end of the tenth transistor 412.
In one embodiment, as shown in fig. 8, the third pull-down circuit 320 includes an eleventh transistor 414 and a twelfth transistor 416, wherein a first end of the eleventh transistor 414 is connected to the second output terminal 2, a control end of the eleventh transistor 414 is connected to the first output terminal 1, a first end of the twelfth transistor 416 is connected to the second end of the eleventh transistor 414, a control end of the twelfth transistor 416 is connected to the output terminal 3 of the output module 104, and a second end of the twelfth transistor 416 is grounded.
In one embodiment, the eleventh transistor 414 is a fifth NMOS transistor, the twelfth transistor 416 is a sixth NMOS transistor, and at this time, the drain of the fifth NMOS transistor is the first end of the eleventh transistor 414, the gate of the fifth NMOS transistor is the control end of the eleventh transistor 414, the source of the fifth NMOS transistor is the second end of the eleventh transistor 414, the drain of the sixth NMOS transistor is the first end of the twelfth transistor 416, the gate of the sixth NMOS transistor is the control end of the twelfth transistor 416, and the source of the sixth NMOS transistor is the second end of the twelfth transistor 416.
In the following, the operation of the latch circuit will be illustrated by taking fig. 8 as an example, when clk= "1" and clkb= "0", the latch circuit of the present invention is in a transparent state, the first transmission gate and the second transmission gate 302 are in a conducting state, the logic values (level states) of the first signal of the first output terminal 1 and the second signal of the second output terminal 2 are a set of complementary signals (respectively, a high level state and a low level state), and the first signal and the second signal directly act on the output module 104, and the input signal D terminal is transmitted to the output terminal 3 of the output module 104, so as to obtain the output signal Q. At this time, only the pull-up circuit or the pull-down circuit in the first feedback circuit 210 and the second feedback circuit 212 is turned on, that is, one of the first feedback circuit 210 and the second feedback circuit 212 is turned on for the pull-up circuit, and the other is turned on for the pull-down circuit, so that in order to prevent the influence of the outside on the first output terminal 1 and the second output terminal 2, no path from the power source (V2, V3) directly to the ground is provided, and the purpose of reducing the overall power consumption of the latch circuit can be achieved. When clk= "0" and clkb= "1", the latch circuit of the present invention is in the latch state, the first transmission gate and the second transmission gate 302 are turned off, the first output terminal 1 and the second output terminal 2 are disconnected from the input signal D, and since a cross feedback loop is formed between the output terminal 3 of the output module 104 and the first output terminal 1 and the second output terminal 2 through the first feedback circuit 210 and the second feedback circuit 212, the first output terminal 1 and the second output terminal 2 keep maintaining the previous level state, and the output signal Q of the output terminal 3 of the output module 104 is determined by the output module 104. The principle of the latch circuit of the invention for resisting single event upset is as follows:
When the logic value latched by the latch circuit is "1" (the input signal D is at a high level), that is, the logic value of the first output terminal 1 is "1" (the level state of the first output terminal 1 is at a high level state), and the logic value of the second output terminal 2 is "0" (the level state of the second output terminal 2 is at a low level state), the logic value of the output terminal 3 of the output module 104 is "1", if the first output terminal 1 is turned over by a single event, that is, the logic state of the first output terminal 1 is changed from "1" to "0", the change of the logic state of the first output terminal 1 does not affect the logic state of the output terminal 3 due to the time delay of the logic state, the fifth transistor 402 and the sixth transistor 404 are turned on, and the connection point of the first feedback circuit 210 and the first output terminal 1 is pulled up to the logic value "1", so that the logic state of the first output terminal 1 is also restored to "1", and the influence of the single event of the first output terminal 1 is eliminated.
Similarly, when the logic value latched by the latch circuit is "1", that is, the logic value of the first output terminal 1 is "1", and the logic value of the second output terminal 2 is "0", the logic value of the output terminal 3 of the output module 104 is "1", and if the second output terminal 2 is turned over by a single event, that is, the logic state of the second output terminal 2 is changed from "0" to "1", at this time, the logic value of the output terminal 3 is "1", the eleventh transistor 414 and the twelfth transistor 416 are turned on, and the connection point between the second feedback circuit 212 and the second output terminal 2 is pulled down to the logic value "0", so that the logic state of the second output terminal 2 is also restored to "0", and the influence of the single event of the second output terminal 2 is eliminated.
When the logic value latched by the latch circuit is "0", that is, the logic value of the first output terminal 1 is "0", and the logic value of the second output terminal 2 is "1", the logic value of the output terminal 3 of the output module 104 is "0", and if the first output terminal 1 is turned over by a single event, that is, the logic state of the first output terminal 1 is changed from "0" to "1", at this time, the logic value of the output terminal 3 of the output module 104 is "0", the seventh transistor 406 and the eighth transistor 408 are turned on, the connection point of the first feedback circuit 210 and the first output terminal 1 is pulled down to the logic value "0", and therefore, the logic state of the first output terminal 1 is also restored to "0".
When the logic value latched by the latch circuit is "0", that is, the logic value of the first output terminal 1 is "0", and the logic value of the second output terminal 2 is "1", the logic value of the output terminal 3 of the output module 104 is "0", and if the second output terminal 2 is turned over by a single event, that is, the logic state of the second output terminal 2 is changed from "1" to "0", at this time, the logic value of the output terminal 3 of the output module 104 is "0", the ninth transistor 410 and the tenth transistor 412 are turned on, and the connection point of the second feedback circuit 212 and the second output terminal 2 is pulled up to the logic value "1", so that the logic state of the second output terminal 2 is also restored to "1".
When the output 3 of the output module 104 is turned over by a single event, the logic values of the output 3 are always kept in the correct state by the output module 104 because the logic states of the first output 1 and the second output 2 are determined. The single event upset resistance function of each node in the latch circuit can be completely realized, the circuit structure is simple, and the power consumption, the time delay and the area cost can be effectively reduced.
The application also provides electronic equipment comprising the latch circuit.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A latch circuit, comprising:
The transmission module comprises a first output end and a second output end, wherein the first output end is used for outputting a first signal in a first level state according to an input signal, and the second output end is used for outputting a second signal in a second level state according to the input signal, and the first level state and the second level state are different;
the output module is respectively connected with the first output end and the second output end and is used for generating output signals according to the first signals and the second signals;
The feedback control module is respectively connected with the output end, the first output end and the second output end of the output module and is used for controlling the level state of the first output end to be the first level state and controlling the level state of the second output end to be the second level state according to the output signals, the first signals and the second signals;
The feedback control module includes:
the first feedback circuit is respectively connected with the output end, the second output end and the first output end of the output module and is used for controlling the level state of the first output end to be the first level state according to the output signals and the second signals;
and the second feedback circuit is respectively connected with the output end, the first output end and the second output end of the output module and is used for controlling the level state of the second output end to be the second level state according to the output signals and the first signals.
2. The latch circuit of claim 1 wherein said transmission module comprises:
The input end of the first transmission circuit is used for receiving the input signal, the output end of the first transmission circuit is the first output end and is used for outputting a first signal in a first level state according to the input signal under the control of a control signal;
The input end of the second transmission circuit is used for receiving the input signal, the output end of the second transmission circuit is the second output end, and the second transmission circuit is used for outputting a second signal in a second level state according to the input signal under the control of the control signal.
3. The latch circuit of claim 2 wherein said first transmission circuit comprises:
The input end of the first transmission gate is used for receiving the input signal, the controlled end of the first transmission gate is used for receiving the control signal, and the output end of the first transmission gate is the first output end.
4. The latch circuit of claim 2 wherein said second transmission circuit comprises:
the input end of the second transmission gate is used for receiving the input signal, and the controlled end of the second transmission gate is used for receiving the control signal;
and the input end of the inverter is connected with the output end of the second transmission gate, and the output end of the inverter is the second output end.
5. The latch circuit of claim 1 wherein said output module comprises:
The first end of the first pull-up circuit is connected with the first output end, and the second end of the first pull-up circuit is connected with the second output end;
the first end of the first pull-down circuit is connected with the first output end, the second end of the first pull-down circuit is connected with the second output end, and the third end of the first pull-down circuit is connected with the third end of the first pull-up circuit so as to jointly output the output signal.
6. The latch circuit of claim 5 wherein said first pull-up circuit comprises:
A first transistor, a first end of which is connected with a power supply voltage, and a control end of which is connected with the second output end;
and the first end of the second transistor is connected with the second end of the first transistor, the control end of the second transistor is connected with the first output end, and the second end of the second transistor is the third end of the first pull-up circuit.
7. The latch circuit of claim 5 wherein the first pull-down circuit comprises:
A third transistor, a first end of which is a third end of the first pull-down circuit, and a control end of which is connected with the first output end;
And the first end of the fourth transistor is connected with the second end of the third transistor, the control end of the fourth transistor is connected with the second output end, and the second end of the fourth transistor is grounded.
8. The latch circuit of claim 1 wherein the first feedback circuit comprises:
The first end of the second pull-up circuit is connected with the second output end, the second end of the second pull-up circuit is connected with the output end of the output module, and the third end of the second pull-up circuit is connected with the first output end;
the first end of the second pull-down circuit is connected with the second output end, the second end of the second pull-down circuit is connected with the output end of the output module, and the third end of the second pull-down circuit is connected with the first output end.
9. The latch circuit of claim 1 wherein said second feedback circuit comprises:
The first end of the third pull-up circuit is connected with the first output end, the second end of the third pull-up circuit is connected with the output end of the output module, and the third end of the third pull-up circuit is connected with the second output end;
the first end of the third pull-down circuit is connected with the first output end, the second end of the third pull-down circuit is connected with the output end of the output module, and the third end of the third pull-down circuit is connected with the second output end.
10. The latch circuit of claim 8 wherein the second pull-up circuit comprises:
a fifth transistor, a first end of which is connected with the power supply voltage, and a control end of which is connected with the second output end;
And the first end of the sixth transistor is connected with the second end of the fifth transistor, the control end of the sixth transistor is connected with the output end of the output module, and the second end of the sixth transistor is connected with the first output end.
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| JP4551731B2 (en) * | 2004-10-15 | 2010-09-29 | 株式会社東芝 | Semiconductor integrated circuit |
| CN103475359B (en) * | 2013-09-24 | 2016-03-02 | 中国科学院微电子研究所 | Single-event transient pulse resistant CMOS circuit |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN210958333U (en) * | 2019-11-18 | 2020-07-07 | 南京航空航天大学 | Pulse latch unit structure |
| CN111211769B (en) * | 2020-01-08 | 2023-04-25 | 中国人民武装警察部队海警学院 | Latch capable of resisting single event upset and data trigger |
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