CN114334664A - Display panel and preparation method thereof - Google Patents

Abstract

The present application provides a display panel and a manufacturing method thereof, and the manufacturing method of the display panel includes the following steps: providing a base substrate, and forming an active layer on the base substrate; forming a first insulating layer and a first metal in sequence patterning the first metal layer to form a gate; using the gate as a mask, patterning the first insulating layer to form an intermediate insulating layer and two layers located in the intermediate insulating layer The side insulating layer on the side, the middle insulating layer is correspondingly arranged on the active layer; wherein, the ratio of the thickness of the side insulating layer to the thickness of the middle insulating layer is 1/2 to 1 . The above-mentioned manufacturing method of the display panel is used to solve the technical problem that cracks may easily occur in the interlayer dielectric layer when the first insulating layer is etched by using the gate electrode as a mask.

Description

Display panel and preparation method thereof

technical field

The present application relates to the field of display technology, and in particular, to a display panel and a preparation method thereof.

Background technique

The self-luminous properties of organic light-emitting diodes (OLEDs) are receiving increasing attention in active-matrix (AMOLED) flat-panel displays. Thin-film transistors (TFTs) provide driving current for OLED light-emitting devices, and this feature makes AMOLEDs put forward higher requirements for the output current and mobility of thin-film transistors.

At present, the mainstream technologies of thin film transistors that are widely studied are low temperature polysilicon (LTPS) technology and metal oxide thin film transistor technology represented by indium gallium zinc oxide (IGZO). In the low-temperature polysilicon technology, due to the characteristics of polysilicon materials, the uniformity of large-area display screens is poor, so the main application field of low-temperature polysilicon technology is small and medium-sized display screens. The metal oxide thin film transistor technology represented by indium gallium zinc oxide has many advantages, such as the characteristics of wide bandgap semiconductor materials, which make it suitable for the requirements of fully transparent display, and the lower process temperature can meet the requirements of using glass substrate or plastic flexible The substrate, large-area uniformity meets the requirements of large-screen displays, and high carrier mobility can meet the high-definition image quality requirements of next-generation flat-panel displays.

Most of the research on indium gallium zinc oxide thin film transistors in the prior art adopts the bottom gate layer device structure, which has the following disadvantages: the over-etching introduced by the back-channel etching process will affect the device characteristics, and the gate The existence of the source-drain overlapping region and the overlapping parasitic capacitance limit the application of the bottom gate structure in short-channel high-resolution and high-speed circuits. The top gate self-aligned device (TGSA) structure can effectively solve the problems brought by the bottom gate device structure. In addition, the gate dielectric layer and the gate electrode above the channel effectively cover the channel and can function as a protective layer for the channel.

Although the top-gate self-aligned structure has lower parasitic capacitance, when the gate is used as a mask to etch the gate insulating layer, when the angle of the gate or gate insulating layer is too large, it is easy to cause interlayer dielectrics. Cracks appear when the electrical layer climbs the slope.

SUMMARY OF THE INVENTION

The present application provides a display panel and a manufacturing method to solve the technical problem that cracks may easily occur in the interlayer dielectric layer when the gate insulating layer is etched by using the gate electrode as a mask.

The present application provides a preparation method of a display panel, comprising the following steps:

providing a base substrate, and forming an active layer on the base substrate;

forming a first insulating layer and a first metal layer in sequence;

patterning the first metal layer to form a gate;

Using the gate as a mask, patterning the first insulating layer to form an intermediate insulating layer and side insulating layers on both sides of the intermediate insulating layer, and the intermediate insulating layers are correspondingly arranged on the active layer;

Wherein, the ratio of the thickness of the side insulating layer to the thickness of the middle insulating layer is 1/2 to 1.

Optionally, after the patterning processing step is performed on the first insulating layer, the following steps are further included:

forming an interlayer dielectric layer on the first insulating layer;

etching the interlayer dielectric layer to form a through hole, and the through hole penetrates to the active layer;

forming a second metal layer;

patterning the second metal layer to form a source-drain layer; the source-drain layer extends from a part of the surface of the interlayer dielectric layer to the surface of the active layer to form a source-drain contact Area.

Optionally, after the step of forming the active layer on the base substrate, the following steps are included:

The first insulating layer is formed on the active layer.

Optionally, after the step of forming the active layer on the base substrate, the following steps are included:

semiconductorizing the active layer with plasma gas;

After the step of patterning the interlayer dielectric layer to form a through hole, the following steps are further included:

Conducting conductive treatment on the active layer exposed in the through hole.

Optionally, the plasma gas is one or more mixed gases of helium, argon, hydrogen and oxygen.

Optionally, before the step of forming the active layer on the base substrate, the following steps are further included:

forming a light-shielding layer on the base substrate, and patterning the light-shielding layer;

A buffer layer is formed on the base substrate, and the buffer layer covers the light shielding layer.

Correspondingly, the present application also provides a display panel, which is applicable to the preparation method of the display panel, including a base substrate, an active layer, a first insulating layer and a gate electrode, and the active layer is prepared on the base substrate , the active layer includes a channel region and source-drain contact regions located on both sides of the channel region; the first insulating layer is located on the active layer, and includes an intermediate insulating layer and is located in the intermediate portion side insulating layers on both sides of the insulating layer, the middle insulating layer is correspondingly disposed on the active layer; the gate corresponds to the channel region and is located on the first insulating layer; the side insulating layer The ratio of the thickness of the layer to the thickness of the intermediate insulating layer is 1/2 to 1.

Optionally, the display panel further includes an interlayer dielectric layer and a source and drain electrodes, the interlayer dielectric layer is prepared on the gate, and includes a through hole, the through hole penetrates to the active layer; and a source The drain electrode is prepared on the interlayer dielectric layer and is electrically connected to the source-drain contact region through the through hole.

Optionally, the upper surface of the side insulating layer and the side surface of the middle insulating layer form an angle, the supplementary angle of the angle is a first slope angle, and the degree of the first slope angle is less than 40°.

Optionally, the gate includes a gate bottom surface and a gate side surface, the gate bottom surface and the gate side surface form a second slope angle, and the degree of the second slope angle is less than 50°.

The present application provides a display panel and a manufacturing method thereof. A gate is used as a mask to pattern a first insulating layer to form a middle insulating layer and side insulating layers on both sides thereof, and the side insulating layers are formed. The thickness of the layer is smaller than that of the middle insulating layer; since the side insulating layer corresponds to the source and drain contact regions, when the interlayer dielectric layer is prepared on the side insulating layer with a slightly smaller thickness, the first insulating layer and the gate can be reduced. The inclination angle of the poles makes the gradient of the interlayer dielectric layer relatively gentle, thereby reducing the cracks when the interlayer dielectric layer climbs the slope.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a flowchart of a display panel method in Embodiment 1 provided by the present application;

FIG. 2 is a flowchart of a display panel method in Embodiment 2 provided by the present application;

3-10 are schematic diagrams of the manufacturing process of the display panel provided by the present application.

Description of reference numbers:

100, base substrate; 200, light shielding layer; 300, buffer layer; 400, active layer; 410, source and drain contact region; 420, channel region; 500, first insulating layer; 510, side insulating layer; 520, intermediate insulating layer; 600, gate electrode; 700, interlayer dielectric layer; 800, through hole; 910, source electrode; 920, drain electrode.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of this application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, but not to limit the present application. In this application, unless otherwise stated, the directional words used such as "up", "down", "left" and "right" usually refer to the upper, lower and left of the device in actual use or working state. and right, specifically the direction of the drawing in the drawings.

The present application provides a display panel and a manufacturing method, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application. In addition, in the following embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

Referring to FIG. 1, the present application provides a method for manufacturing a display panel, which includes the following steps:

S100, providing a base substrate 100, forming a light shielding layer 200 on the base substrate 100, and performing a patterning process on the light shielding layer 200;

As shown in FIG. 3 , the light-shielding layer 200 is deposited on the base substrate 100 by physical vapor deposition, and the above-mentioned light-shielding layer 200 is patterned through a photolithography process; in the present application, the light-shielding layer 200 is a metal layer, and its material can be molybdenum .

S200, forming a buffer layer 300 on the base substrate 100, and the buffer layer 300 covers the light shielding layer 200;

Referring to FIG. 4 , the buffer layer 300 is deposited on the base substrate 100 by chemical vapor deposition, so as to cover the light shielding layer 200 . In the present application, the material of the buffer layer 300 is silicon dioxide or silicon nitride.

S300 , forming the active layer 400 on the base substrate 100 , specifically, forming the active layer 400 on the buffer layer 300 ;

As shown in FIG. 5 , the material of the active layer 400 includes but is not limited to indium gallium zinc oxide (IGZO), and can also be other oxide semiconductor materials such as indium gallium zinc oxide (IGZTO).

S400 , forming a first insulating layer 500 and a first metal layer on the base substrate 100 in sequence, specifically, forming a first insulating layer 500 and a first metal layer directly on the active layer 400 in sequence; patterning the first insulating layer 500 a metal layer to form the gate 600; in this application, the first insulating layer 500 is the gate insulating layer, and the first metal layer is the gate layer;

As shown in FIG. 6 , after the preparation of the active layer 400 is completed and before the first insulating layer 500 process, the active layer 400 is not subjected to plasma treatment with nitrous oxide (N2O), at this time the active layer 400 It exhibits conductor characteristics (smaller impedance). Then, the first insulating layer 500 and the first metal layer are directly prepared on the above-mentioned active layer 400. In the subsequent process of forming the through hole 800, the active layer 400 exposed in the through hole 800 will be further etched during dry etching. Conductive.

In the present application, the first insulating layer 500 may be formed by continuous deposition, wherein the material of the first insulating layer 500 is usually silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide, or the like. Meanwhile, the first metal layer is patterned through a dry etching process to form the gate 600. The material of the first metal layer generally includes molybdenum, aluminum-neodymium alloy, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium or copper.

S500 , using the gate 600 as a mask, patterning the first insulating layer 500 to form a middle insulating layer 520 and side insulating layers 510 on both sides of the middle insulating layer 520 , The middle insulating layer 520 is correspondingly disposed on the active layer 400; wherein, the ratio of the thickness of the side insulating layer 510 to the thickness of the middle insulating layer 520 is 1/2 to 1;

Referring to FIG. 7 , using the gate 600 as a mask, the first insulating layer 500 is processed by a dry etching process, and the first insulating layer 500 is located on both sides of the gate 600 to form side insulating layers 510 , and The thickness of the side insulating layer 510 is at least half of the thickness of the first insulating layer 500 .

S600 , forming an interlayer dielectric layer 700 on the first insulating layer 500 , and the interlayer dielectric layer 700 covers the gate electrode 600 ;

Referring to FIG. 8 , the material of the interlayer dielectric layer 700 in the present application includes, but is not limited to, inorganic materials such as silicon oxide.

S700, patterning the interlayer dielectric layer 700 to form a through hole 800, the through hole 800 penetrating to the active layer 400;

Referring to FIG. 9 , an interlayer dielectric layer 700 is prepared on the first insulating layer 500 , and the interlayer dielectric layer 700 is patterned, so that the two sides of the gate electrode 600 correspond to the source-drain contact regions 410 . A through hole 800 is formed at the position, and the through hole 800 extends from the upper surface of the interlayer dielectric layer 700 and penetrates to the active layer 400 .

S800 , forming a second metal layer, and patterning the second metal layer to form a source and drain layer;

Referring to FIG. 10 , the source and drain layers include a source electrode 910 and a drain electrode 920, and the source and drain layers extend from a part of the surface of the interlayer dielectric layer 700 to the surface of the active layer 400 to form a source Drain contact region 410 . In addition, a passivation layer is formed on the interlayer dielectric layer 700, and the passivation layer can cover the interlayer dielectric layer 700, the source electrode 910 and the drain electrode 920; at the same time, a via hole is provided on the drain electrode 920, and the above-mentioned via hole Used to connect the pixel electrode layer above.

In this application, the gate 600 is used as a mask to etch the first insulating layer 500 to form a side insulating layer 510 , and the thickness of the side insulating layer 510 is smaller than that of the middle insulating layer 520 . In the present application, the side insulating layer 510 corresponds to the source-drain contact region 410. When the interlayer dielectric layer 700 is formed on the side insulating layer 510 with a slightly smaller thickness, the inclination of the first insulating layer 500 and the gate electrode 600 can be reduced The angle of the interlayer dielectric layer 700 makes the slope of the interlayer dielectric layer 700 relatively gentle, thereby reducing cracks when the interlayer dielectric layer 700 climbs the slope.

A display panel is manufactured by the manufacturing method of the display panel described in the above embodiments. The above-mentioned display panel includes a base substrate 100 , an active layer 400 , a first insulating layer 500 and a gate electrode 600 . The active layer 400 is prepared on the base substrate 100 , and the active layer 400 includes a channel region 420 and source-drain contact regions 410 located on both sides of the channel region 420 . The first insulating layer 500 is located on the active layer 400 , and includes a middle insulating layer 520 and side insulating layers 510 on both sides of the middle insulating layer 520 , and the middle insulating layer 520 is correspondingly disposed on the middle insulating layer 520 . Above the active layer 400 , the side insulating layer 510 corresponds to the source-drain contact region 410 . The gate 600 corresponds to the channel region 420 and is located on the intermediate insulating layer 520 . The ratio of the thickness of the side insulating layer 510 to the thickness of the middle insulating layer 520 is 1/2 to 1.

In the above display panel, since the ratio of the thickness of the side insulating layer 510 to the thickness of the middle insulating layer 520 is 1/2 to 1, the side insulating layer 510 corresponds to the source-drain contact region 410, so that the first insulating layer 500 and the gate The slope angle of the electrode 600 is reduced, and the slope of the interlayer dielectric layer 700 located above the first insulating layer 500 along the gate 600 is reduced, thereby reducing cracks generated when the interlayer dielectric layer 700 climbs the slope.

In the present application, the upper surface of the middle insulating layer 520 is consistent with the upper surface of the first insulating layer 500 , the upper surface of the side insulating layer 510 is recessed from the upper surface of the first insulating layer 500 , and the two side insulating layers 510 They are located on both sides of the middle insulating layer 520 respectively, so that the middle insulating layer 520 corresponds to the channel region 420 of the active layer 400 , and the side insulating layer 510 corresponds to the source and drain contact regions 410 of the active layer 400 .

Further, the display panel further includes an interlayer dielectric layer 700 and a source and drain electrodes. The interlayer dielectric layer 700 is prepared on the gate electrode 600 and includes a through hole 800 which penetrates to the active Layer 400. The source and drain electrodes are prepared on the interlayer dielectric layer 700 and are electrically connected to the source and drain contact regions 410 through the through holes 800 .

Further, the upper surface of the side insulating layer 510 and the side surface of the middle insulating layer 520 form an angle, the supplementary angle of this angle is a first slope angle, and the degree of the first slope angle α1 is less than 40° .

By limiting the degree of the first slope to be less than 40°, the angle at which the side insulating layer 510 and the middle insulating layer 520 are connected can be limited, thereby reducing cracks generated when the interlayer dielectric layer 700 climbs along the gate 600 .

Further, the gate 600 includes a bottom surface of the gate 600 and a side surface of the gate 600 , the bottom surface of the gate 600 and the side surface of the gate 600 form a second slope angle, and the second slope angle α2 is less than 50 degrees. °.

By defining the angle of the second slope angle formed by the bottom surface of the gate 600 and the side surface of the gate 600 to be less than 50°, the gate 600 formed by patterning forms a tail, thereby reducing the slope of the interlayer dielectric layer 700 along the gate 600 cracks produced.

Embodiment 2

The present application provides a method for preparing a display panel, as shown in FIG. 2 , which includes the following steps:

S100, providing a base substrate 100, forming a light shielding layer 200 on the base substrate 100, and performing a patterning process on the light shielding layer 200;

As shown in FIG. 3 , the light-shielding layer 200 is deposited on the base substrate 100 by physical vapor deposition, and the above-mentioned light-shielding layer 200 is patterned through a photolithography process; in the present application, the light-shielding layer 200 is a metal layer, and its material can be molybdenum .

S200, forming a buffer layer 300 on the base substrate 100, and the buffer layer 300 covers the light shielding layer 200;

Referring to FIG. 4 , the buffer layer 300 is deposited on the base substrate 100 by chemical vapor deposition, so as to cover the light shielding layer 200 . In the present application, the material of the buffer layer 300 is silicon dioxide or silicon nitride.

S300 , forming the active layer 400 on the base substrate 100 , specifically, forming the active layer 400 on the buffer layer 300 ;

As shown in FIG. 5 , the material of the active layer 400 includes but is not limited to indium gallium zinc oxide (IGZO), and can also be other oxide semiconductor materials such as indium gallium zinc oxide (IGZTO).

S400, using plasma gas to perform semiconductorization processing on the active layer 400;

The above-mentioned plasma gas is one or more mixed gases of helium, argon, hydrogen and oxygen.

S500 , forming a first insulating layer 500 and a first metal layer on the base substrate 100 in sequence, specifically, forming a first insulating layer 500 and a first metal layer directly on the active layer 400 in sequence; patterning the first insulating layer 500 a metal layer to form the gate 600;

As shown in FIG. 6 , after the preparation of the active layer 400 is completed and before the first insulating layer 500 process, the active layer 400 is not subjected to plasma treatment with nitrous oxide (N2O), at this time the active layer 400 It exhibits conductor characteristics (smaller impedance). Then, the first insulating layer 500 and the first metal layer are directly prepared on the above-mentioned active layer 400. In the subsequent process of forming the through hole 800, the active layer 400 exposed in the through hole 800 will be further etched during dry etching. Conductive.

In the present application, the first insulating layer 500 may be formed by continuous deposition, wherein the material of the first insulating layer 500 is usually silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide, or the like. At the same time, the first metal layer is patterned through a dry etching process to form the gate 600. The material of the first metal layer generally includes metals such as molybdenum, aluminum-neodymium alloy, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium or copper.

S600, using the gate 600 as a mask, patterning the first insulating layer 500 to form a middle insulating layer 520 and side insulating layers 510 on both sides of the middle insulating layer 520, The middle insulating layer 520 is correspondingly disposed on the active layer 400; wherein, the ratio of the thickness of the side insulating layer to the thickness of the middle insulating layer 520 is 1/2 to 1;

Referring to FIG. 7 , using the gate 600 as a mask, the first insulating layer 500 is processed by a dry etching process, and the first insulating layer 500 is located on both sides of the gate 600 to form side insulating layers 510 , and The thickness of the side insulating layer 510 is at least half of the thickness of the first insulating layer 500 .

S700 , forming an interlayer dielectric layer 700 on the first insulating layer 500 , and the interlayer dielectric layer 700 covers the gate 600 ; patterning the interlayer dielectric layer 700 to form a pass through a hole 800, the through hole 800 penetrates to the active layer 400;

As shown in FIG. 8 and FIG. 9 , the material of the interlayer dielectric layer 700 in the present application includes, but is not limited to, inorganic materials such as silicon oxide. An interlayer dielectric layer 700 is prepared on the first insulating layer 500, and the interlayer dielectric layer 700 is patterned, so that through holes 800 are formed on both sides of the gate electrode 600 at positions corresponding to the source and drain contact regions 410, The above-mentioned through hole 800 extends from the upper surface of the interlayer dielectric layer 700 and penetrates to the active layer 400 .

S800 , conducting conductive treatment on the active layer 400 exposed in the through hole 800 ;

The active layer 400 exposed in the through hole 800 is subjected to conducting treatment by using He gas, so that the source and the drain form an ohmic contact with the conductive active layer 400 .

S900 , forming a second metal layer, and patterning the second metal layer to form a source and drain layer;

10 , the source and drain layers include a source electrode 910 and a drain electrode 920, and the source and drain layers extend from a part of the surface of the interlayer dielectric layer 700 to the surface of the active layer 400 to form a source Drain contact region 410 . In addition, a passivation layer is formed on the interlayer dielectric layer 700, and the passivation layer can cover the interlayer dielectric layer 700, the source electrode 910 and the drain electrode 920; at the same time, a via hole is provided on the drain electrode 920, and the above-mentioned via hole Used to connect the pixel electrode layer above.

In this application, the gate 600 is used as a mask to etch the first insulating layer 500 to form a side insulating layer 510 , and the thickness of the side insulating layer 510 is smaller than that of the middle insulating layer 520 . In the present application, the side insulating layer 510 corresponds to the source-drain contact region 410. When the interlayer dielectric layer 700 is formed on the side insulating layer 510 with a slightly smaller thickness, the inclination of the first insulating layer 500 and the gate electrode 600 can be reduced The angle of the interlayer dielectric layer 700 makes the slope of the interlayer dielectric layer 700 relatively gentle, thereby reducing cracks when the interlayer dielectric layer 700 climbs the slope.

A display panel is prepared by the preparation method of the display panel disclosed in the second embodiment. The structure of the above-mentioned display panel is the same as that of the display panel in the first embodiment, so the specific structure can refer to the display panel in the first embodiment. The structure of the panel is not repeated here.

The above provides a detailed introduction to a display panel and a manufacturing method provided by the present application. The principles and implementations of the present application are described with specific examples in this paper. At the same time, for those skilled in the art, according to the idea of the application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as a limitation to the application. .

Claims (10)

1. A preparation method of a display panel, characterized in that, comprising the following steps: providing a base substrate, and forming an active layer on the base substrate; forming a first insulating layer and a first metal layer in sequence; patterning the first metal layer to form a gate; Using the gate as a mask, patterning the first insulating layer to form an intermediate insulating layer and side insulating layers on both sides of the intermediate insulating layer, and the intermediate insulating layers are correspondingly arranged on the active layer; Wherein, the ratio of the thickness of the side insulating layer to the thickness of the middle insulating layer is 1/2 to 1. 2. The manufacturing method of the display panel according to claim 1, wherein, After the patterning processing step is performed on the first insulating layer, the following steps are further included: forming an interlayer dielectric layer on the first insulating layer; patterning the interlayer dielectric layer to form a through hole, and the through hole penetrates to the active layer; forming a second metal layer; patterning the second metal layer to form a source-drain layer; the source-drain layer extends from a part of the surface of the interlayer dielectric layer to the surface of the active layer to form a source-drain contact Area. 3. The method for manufacturing a display panel according to claim 1, wherein after the step of forming an active layer on the base substrate, the method comprises the following steps: The first insulating layer is formed on the active layer. 4. The manufacturing method of the display panel according to claim 2, wherein, After the step of forming the active layer on the base substrate, the following steps are included: semiconductorizing the active layer with plasma gas; After the step of patterning the interlayer dielectric layer to form a through hole, the following steps are further included: Conducting conductive treatment on the active layer exposed in the through hole. 5 . The manufacturing method of the display panel according to claim 4 , wherein the plasma gas is one or more mixed gases of helium, argon, hydrogen and oxygen. 6 . 6. The method for manufacturing a display panel according to claim 2, wherein before the step of forming an active layer on the base substrate, the method further comprises the following steps: forming a light-shielding layer on the base substrate, and patterning the light-shielding layer; A buffer layer is formed on the base substrate, and the buffer layer covers the light shielding layer. 7. A display panel, applicable to the preparation method of the display panel according to any one of claims 1-6, characterized in that, comprising: substrate substrate; an active layer, which is prepared on the base substrate, the active layer includes a channel region and source-drain contact regions located on both sides of the channel region; a first insulating layer, which is located on the active layer and includes a middle insulating layer and side insulating layers on both sides of the middle insulating layer, the middle insulating layer is correspondingly arranged on the active layer above; and a gate, which corresponds to the channel region and is located on the first insulating layer; Wherein, the ratio of the thickness of the side insulating layer to the thickness of the middle insulating layer is 1/2 to 1. 8. The display panel according to claim 7, further comprising: an interlayer dielectric layer, which is prepared on the gate electrode and includes a through hole that penetrates to the active layer; and A source-drain electrode is prepared on the interlayer dielectric layer and is electrically connected to the source-drain contact region through the through hole. 9 . The display panel according to claim 7 , wherein the upper surface of the side insulating layer forms an angle with the side surface of the middle insulating layer, and the supplementary angle of the angle is the first slope angle, so the The degree of the first slope angle is less than 40°. 10 . The display panel of claim 7 , wherein the gate comprises a gate bottom surface and a gate side surface, the gate bottom surface and the gate side surface form a second slope angle, and the first The degree of the second slope angle is less than 50°.

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