CN114333677A

CN114333677A - Display panel, driving method and display device

Info

Publication number: CN114333677A
Application number: CN202111678651.2A
Authority: CN
Inventors: 孙光远
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-12

Abstract

The embodiment of the application provides a display panel, a driving method and a display device, wherein a first display area is provided with a pixel row p, and a second display area is provided with a pixel row p + 1; the ith stage first shift register and the jth stage second shift register are connected with the pixel row p; the i +1 th stage first shift register and the j +1 th stage second shift register are connected to the pixel row p + 1; the first switching element K1 is provided between adjacent first shift registers; the second switching element K2 is provided between the first trigger signal line and the i +1 th stage first shift register; the third switching element K3 is provided between adjacent second shift registers; the fourth switching element K4 is disposed between the off-level line and the j +1 th stage or the 1 st stage second shift register; when K1, K3 are closed and K2, K4 are opened, the first display area or the second display area stops working. The embodiment of the application can solve the problem of poor display effect caused by insufficient data writing time.

Description

Display panel, driving method and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a display panel, a driving method and a display device.

Background

With the development of display technology, display panels can support a variety of refresh rates. However, the inventors of the present application have found that, at a high refresh rate, the data writing time of each row of sub-pixels of the display panel is short, which results in insufficient data writing time and thus poor display effect of the display panel.

Disclosure of Invention

The embodiment of the application provides a display panel, a driving method and a display device, which can solve the problem of poor display effect of the display panel caused by insufficient data writing time.

In a first aspect, an embodiment of the present application provides a display panel, which includes a first scan driving circuit, a second scan driving circuit, and a plurality of rows of sub-pixels, where the first scan driving circuit includes a first trigger signal line and a cascade of multiple stages of first shift registers, the second scan driving circuit includes a second trigger signal line and a cascade of multiple stages of second shift registers, each stage of first shift registers is electrically connected to at least one row of sub-pixels, and each stage of second shift registers is electrically connected to at least one row of sub-pixels; the display panel comprises a first display area and a second display area, wherein the first display area is provided with a first critical pixel row p, and the second display area is provided with a second critical pixel row p + 1; the ith stage first shift register and the jth stage second shift register are connected to the first critical pixel row p; the (i + 1) th stage first shift register and the (j + 1) th stage second shift register are connected to the second critical pixel row p + 1; the first switching elements are arranged between adjacent first shift registers; the second switching element is arranged between the first trigger signal line and the (i + 1) th stage first shift register; the third switching element is arranged between the adjacent second shift registers; the fourth switching element is provided between the off-level power supply signal line and the j +1 th stage second shift register or between the off-level power supply signal line and the 1 st stage second shift register; when the first switching element and the third switching element are turned on and the second switching element and the fourth switching element are turned off, the first display area and the second display area are displayed together; when the first switching element and the third switching element are turned off and the second switching element and the fourth switching element are turned on, the first display area or the second display area stops operating.

In a second aspect, an embodiment of the present application provides a driving method applied to the display panel provided in the first aspect, the method includes: when the display panel displays the picture at a first refresh rate higher than a preset refresh rate threshold, the first switch element and the third switch element are controlled to be closed, and the second switch element and the fourth switch element are controlled to be opened, so that any one of the first display area and the second display area stops working.

In a third aspect, an embodiment of the present application provides a display device, which includes the display panel provided in the first aspect.

According to the display panel, the driving method and the display device, when the refresh rate is high, the first switch element is closed, and the third switch element is closed, so that the cascade relation among the first multi-stage shift registers is broken, and the cascade relation among the second multi-stage shift registers is broken, so that the display panel is divided into a plurality of independent display areas, such as the first display area and the second display area; the second switch element is turned on, a first trigger signal of the first trigger signal line is transmitted to the input end of the (i + 1) th-stage first shift register, and the data writing of the sub-pixels in the (p + 1) th row and the sub-pixels in the 1 st row is guaranteed to be carried out simultaneously, so that the data writing time of each row of sub-pixels in the first display area and the second display area is prolonged; the fourth switch element is turned on, the cut-off level of the cut-off level power supply signal line is transmitted to the 1 st-stage second shift register or the j +1 th-stage second shift register, and meanwhile, the second trigger signal line provides a trigger signal for the j +1 th-stage second shift register or the 1 st-stage second shift register, so that one of the first display area and the second display area can be ensured to display a picture, and the other one of the first display area and the second display area is kept in a black state. Therefore, the embodiment of the application can increase the data writing time of each row of sub-pixels by reducing the resolution under the condition of not reducing the refresh rate, and solves the problem of poor display effect caused by insufficient data writing time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1a and fig. 1b are schematic structural diagrams of a display panel according to an embodiment of the present application;

FIG. 2 is a diagram illustrating the display effect of the display panel shown in FIG. 1a and FIG. 1 b;

fig. 3a and fig. 3b are schematic structural diagrams of another display panel provided in an embodiment of the present application;

FIG. 4 is a diagram illustrating the display effect of the display panel shown in FIG. 3a and FIG. 3 b;

fig. 5a and fig. 5b are schematic structural diagrams of a display panel according to an embodiment of the present disclosure;

FIG. 6 is a diagram illustrating the display effect of the display panel shown in FIG. 5a and FIG. 5 b;

fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 9a and 9b are schematic structural diagrams of a display panel according to an embodiment of the present disclosure;

fig. 10a and fig. 10b are schematic structural diagrams of a display panel according to an embodiment of the present application;

fig. 11a and 11b are schematic structural diagrams of a display panel according to an embodiment of the present disclosure;

fig. 12a and 12b are schematic circuit diagrams of a display panel according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

Note that the transistors in the embodiments of the present application are described using P-type transistors as examples, but the transistors are not limited to P-type transistors, and may be replaced with N-type transistors. For a P-type transistor, the on level is low and the off level is high. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. For an N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole of the N-type transistor are turned on, and when the gate of the N-type transistor is at a low level, the first pole and the second pole of the N-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source and the second electrode as its drain, or the first electrode of each transistor can be used as its drain and the second electrode as its source, which are not distinguished herein.

In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the prior art:

the inventor of the present application has found that, at a high refresh rate (e.g., 144Hz), the data writing time of each row of sub-pixels of the display panel is short, which results in insufficient data writing time and thus poor display effect of the display panel.

Specifically, the inventors of the present application found that the relationship between the refresh rate of the display panel and the row period of each row of sub-pixels is:

where t denotes a row period of the sub-pixels per row, f denotes a refresh rate of the display panel, and y denotes the number of sub-pixels in the vertical direction in resolution, that is, the number of rows of sub-pixels.

As can be seen from the above expression (1), the refresh rate f of the display panel is inversely proportional to the row period t of each row of sub-pixels. That is, as the refresh rate f of the display panel is higher, the row period t of each row of sub-pixels is smaller, so that the data writing time of each row of sub-pixels is smaller. Under a high refresh rate, the data writing time of each row of sub-pixels of the display panel is short, so that the sub-pixels cannot be charged to an expected voltage value in a short time, and the display panel has a poor display effect, such as uneven display or smear.

In order to solve the above technical problem, the inventors of the present application considered or could improve the row period t of the sub-pixels per row at a high refresh rate by reducing the number of sub-pixels in the vertical direction in the resolution (i.e., the parameter y in the above expression (1)), thereby solving the problem of poor display effect caused by insufficient data write time.

Based on the above-mentioned findings and preliminary ideas of the inventors, embodiments of the present application provide a display panel, a driving method, and a display device.

The specific technical idea of the embodiment of the application is as follows: adding a first switching element, a second switching element, a third switching element and a fourth switching element in the display panel, wherein at the time of high refresh rate, the first switching element is turned off in response to the cut-off level output by the first control signal line, and the third switching element is turned off in response to the cut-off level output by the third control signal line, thereby disconnecting the cascade relation between the first shift registers of the plurality of stages and disconnecting the cascade relation between the second shift registers of the plurality of stages, so that the display panel is divided into a plurality of independent display regions, such as a first display region and a second display region; the second switch element is turned on in response to the on level output by the second control signal line, and transmits a first trigger signal of the first trigger signal line to the input end of the (i + 1) th-stage first shift register, so that the (p + 1) th row of sub-pixels and the (1) th row of sub-pixels are ensured to carry out data writing simultaneously, and the data writing time of each row of sub-pixels in the first display area and the second display area is prolonged; the fourth switching element is turned on in response to the on level output by the fourth control signal line, transmits the off level of the off level power signal line to the 1 st-stage second shift register or the j +1 th-stage second shift register, and simultaneously the second trigger signal line provides a trigger signal for the j +1 th-stage second shift register or the 1 st-stage second shift register, thereby ensuring that one of the first display area and the second display area can display a picture and the other one remains in a black state. Therefore, under the condition of not reducing the refresh rate, the data writing time of each row of sub-pixels is increased by reducing the actual resolution of the display panel, and the problem of poor display effect caused by insufficient data writing time is solved.

The following first describes a display panel provided in an embodiment of the present application.

Fig. 1a and fig. 1b are schematic structural diagrams of a display panel according to an embodiment of the present application. As shown in fig. 1a and 1b, the display panel 10 according to the embodiment of the present application includes a first scan driving circuit S1 ', a second scan driving circuit S2', and a plurality of rows of sub-pixels PX. The first scan driving circuit S1' includes a first trigger signal line SIN and a cascade of multiple first shift registers 101, that is, an output terminal Gout of the mth first shift register 101 is connected to an input terminal IN of the (m + 1) th first shift register 101, where m is a positive integer. The second scan driving circuit S2' includes a second trigger signal line EIN and a plurality of cascaded second shift registers 102, that is, an output terminal Gout of the mth second shift register 102 is connected to an input terminal IN of the (m + 1) th second shift register 102, where m is a positive integer. Each stage of the first shift register 101 is electrically connected to at least one row of the sub-pixels PX, and is configured to provide a scan signal to the sub-pixels to control writing of data signals of the sub-pixels. Accordingly, each stage of the second shift register 102 may also be electrically connected to at least one row of the sub-pixels PX for providing the sub-pixels with light-emitting control signals to control the sub-pixels to emit light.

The display panel 10 includes a first display area AA1 and a second display area AA2, and the first display area AA1 has a first critical pixel row p, i.e., a p-th row of sub-pixels PX. The second display area AA2 has a second critical pixel row p +1, i.e., a p +1 th row of sub-pixels PX. The ith stage first shift register 101 and the jth stage second shift register 102 are connected to the first critical pixel row p. The i +1 th stage first shift register 101 and the j +1 th stage second shift register 102 are connected to the second critical pixel row p + 1.

With continued reference to fig. 1a and 1b, in order to improve the problem of poor display effect of the display panel due to insufficient data writing time, the display panel 10 includes a first switching element K1, a second switching element K2, a third switching element K3 and a fourth switching element K4.

The first switching element K1 is provided between adjacent first shift registers 101, specifically, between any adjacent first shift register 101 among the 1 st-stage first shift register 101 to the i +1 th-stage first shift register 101. For example, the first switching element K1 may be disposed between the i-th stage first shift register 101 and the i + 1-th stage first shift register 101. The second switching element K2 is provided between the first trigger signal line SIN and the i +1 th stage first shift register 101. The third switching element K3 is provided between adjacent second shift registers 102, specifically, between any adjacent second shift registers 102 among the 1 st stage second shift register 102 to the j +1 th stage second shift register 102. For example, the third switching element K3 may be disposed between the j-th stage second shift register 102 and the j + 1-th stage second shift register 102. The fourth switching element K4 is disposed between the off-level power supply signal line VGH and the j +1 th stage second shift register 102 or between the off-level power supply signal line VGH and the 1 st stage second shift register 102. Illustratively, the second trigger signal line EIN is electrically connected to the 1 st stage second shift register 102 or the j +1 th stage second shift register 102.

When the first and third switching elements K1 and K3 are turned on and the second and fourth switching elements K2 and K4 are turned off, the first display area AA1 is displayed in common with the second display area AA 2. When the first and third switching elements K1 and K3 are turned off and the second and fourth switching elements K2 and K4 are turned on, the first display area AA1 or the second display area AA2 stops operating. Therefore, under the condition of not reducing the refresh rate, the data writing time of each row of sub-pixels is increased by reducing the actual resolution of the display panel, and the problem of poor display effect caused by insufficient data writing time is solved.

For ease of understanding, the circuit structure shown in fig. 1a and 1b will be described in detail below.

Taking an example IN which the first switching element K1 is disposed between the i-th stage first shift register 101 and the i + 1-th stage first shift register 101, a control terminal of the first switching element K1 is electrically connected to the first control signal line S1, a first terminal of the first switching element K1 is electrically connected to the output terminal Gout of the i-th stage first shift register 101, a second terminal of the first switching element K1 is electrically connected to the input terminal IN of the i + 1-th stage first shift register 101, the i-th stage first shift register 101 is configured to control writing of the data signal of the p-th row of sub-pixels PX, and i and p are positive integers. In the case where the first scan driver circuit S1' includes the cascade N stages of the first shift register 101, i may be any value from 1 to N-1, and the embodiment of the present application is not limited to specific values of i. For example, when N is 100, i is any of 1 to 99, e.g., i may be equal to 1, 10, 20, 70, or 99, etc. It should be noted that the first switching element K1 is not limited to be disposed between the i-th stage first shift register 101 and the i + 1-th stage first shift register 101, and may be disposed between any adjacent first shift register 101 in the 1-th to i + 1-th stage first shift registers 101, for example, the first switching element K1 is disposed between the 1-th stage first shift register 101 and the 2-th stage first shift register 101.

A control terminal of the second switching element K2 is electrically connected to the second control signal line S2, a first terminal of the second switching element K2 is electrically connected to the first trigger signal line SIN, and a second terminal of the second switching element K2 is electrically connected to the input terminal IN of the i +1 th stage first shift register 101.

Taking the example that the third switching element K3 is disposed between the j-th stage of the second shift register 102 and the j + 1-th stage of the second shift register 102, the control terminal of the third switching element K3 is electrically connected to the third control signal line S3, the first terminal of the third switching element K3 is electrically connected to the output terminal Gout of the j-th stage of the second shift register 101, the second terminal of the third switching element K3 is electrically connected to the input terminal IN of the j + 1-th stage of the second shift register 101, the j-th stage of the second shift register 101 is configured to provide the light emitting control signal to the p-th row of sub-pixels PX, and j is a positive integer. Similarly to the parameter i, in the case that the second scan driving circuit S2' includes the cascaded M stages of second shift registers 102, j may be any value from 1 to M, and the specific value of j is not limited in the embodiment of the present application. For example, when M is 100, j is any number from 1 to 100, e.g., j may be equal to 1, 10, 20, 70, or 99, etc. Alternatively, j may be equal to i. It should be noted that the third switching element K3 is not limited to be disposed between the j-th stage second shift register 102 and the j + 1-th stage second shift register 102, and may be disposed between any adjacent second shift register 102 in the 1-th stage second shift register 102 to the j + 1-th stage second shift register 102.

A control terminal of the fourth switching element K4 is electrically connected to the fourth control signal line S4, a first terminal of the fourth switching element K4 is electrically connected to the off-level power supply signal line VGH, and a second terminal of the fourth switching element K4 is electrically connected to the input terminal IN of the 1 st stage second shift register 101; the second trigger signal line EIN is used to provide a trigger signal to the j +1 th stage second shift register 102. Note that the off level output from the off level power supply signal line VGH is a positive voltage, that is, a voltage for turning off the P-type transistor, for example, + 7V.

For ease of understanding, the operation states of the respective switching elements when the display panel 10 displays a picture at a high refresh rate will be described below.

When the display panel 10 displays a screen at the first refresh rate, the first control signal line S1 and the third control signal line S3 output an off level, and the second control signal line S2 and the fourth control signal line S4 output an on level. In the embodiment of the present application, the first refresh rate is higher than a preset refresh rate threshold, such as the first refresh rate includes but is not limited to 144 Hz. The preset refresh rate threshold value can be flexibly set according to actual conditions, and the embodiment of the application does not limit the preset refresh rate threshold value.

When the display panel 10 displays a picture at the first refresh rate, the first switching element K1 is turned off in response to the off level output from the first control signal line S1, thereby breaking the cascade relationship between the plurality of stages of the first shift registers 101 in the first scan driving circuit S1'. Likewise, the third switching element K3 is turned off in response to the off level of the third control signal line S3, thereby breaking the cascade relationship between the plurality of stages of the second shift register 102 in the second scan driving circuit S2'. Thus, the display panel 10 is divided into two display regions that can be independently displayed, such as a first display region AA1 and a second display region AA 2.

Meanwhile, the second switching element K2 is turned on IN response to the on level of the second control signal line S2, and transmits the first trigger signal of the first trigger signal line SIN to the input terminal IN of the i +1 th stage first shift register 101. In this way, the i +1 th stage first shift register 101 and the 1 st stage first shift register 101 may receive the first trigger signal at the same time, and it is ensured that the p +1 th row of sub-pixels and the 1 st row of sub-pixels perform data writing at the same time, for example, it may be implemented that the second display area AA2 is scanned by using the original one-frame time for scanning the entire display area (the sum of the first display area AA1 and the second display area AA 2), so as to increase the data writing time of each row of sub-pixels in the second display area AA 2.

Meanwhile, the fourth switching element K4 is turned on IN response to the on level of the fourth control signal line S4, transmitting the off level of the off-level power supply signal line VGH to the input terminal IN of the 1 st stage second shift register 102. Since the second shift register 102 controls the sub-pixels PX to emit light, by transmitting the off-level to the input terminal IN of the 1 st stage second shift register 102, the respective rows of sub-pixels PX (i.e., the 1 st row to the p th row of sub-pixels) IN the first display area AA1 may be maintained IN the black state, and no picture is displayed. The second trigger signal line EIN provides a trigger signal for the j +1 th stage second shift register 102, so that each row of sub-pixels PX (i.e., the p +1 th row of sub-pixels to the last 1 th row of sub-pixels) in the second display area AA2 can normally emit light, and the second display area AA2 displays a picture. Therefore, by only displaying the picture in the second display area AA2, although the resolution is reduced, the data writing time of each row of sub-pixels in the second display area AA2 is increased, so that the problem of poor display effect of the display panel due to insufficient data writing time can be solved.

For example, the number of rows (or row resolution) of the sub-pixels in the display panel 10 is 3120, and the number of rows of the sub-pixels in the second display area AA2 is 2600.

Before the technical solution provided by the embodiment of the present application is not adopted, the line period of each line of sub-pixels of the display panel when the display panel displays a picture at 120Hz is:

wherein us denotes microsecond, 10⁶Representing a scaling factor between seconds and microseconds.

Before the technical solution provided by the embodiment of the present application is not adopted, the line period of each line of sub-pixels of the display panel when the display panel displays a picture at 144Hz is:

after the technical solution provided by the embodiment of the present application is adopted, the line period of each line of sub-pixels of the display panel when the display panel displays a picture at 144Hz is:

as can be seen from the above expressions (3) and (4), the embodiments of the present application can increase the data writing time of each row of sub-pixels by reducing the resolution without reducing the refresh rate, and improve the problem of poor display effect caused by insufficient data writing time.

As can be seen from the above expressions (2) and (4), in the embodiment of the present application, it can be ensured that the refresh rate of the display panel is increased under the condition that the data writing time of each row of sub-pixels is not changed, for example, the refresh rate is increased from 120Hz to 144 Hz.

Fig. 2 is a diagram showing the effect of the embodiment shown in fig. 1a and 1 b. As shown in fig. 2, corresponding to the embodiment shown in fig. 1a and fig. 1b, the first display area AA1 where the sub-pixels in the row 1 to the row p are located may keep a black state, and the second display area AA2 where the sub-pixels in the row p +1 to the last row 1 are located may display a picture, that is, display an effect of "black-top-bottom-bright".

As shown IN fig. 3a and 3b, according to other embodiments of the present application, optionally, unlike the embodiment shown IN fig. 1a and 1b, IN the embodiment shown IN fig. 3a and 3b, the second terminal of the fourth switching element K4 may be electrically connected to the input terminal IN of the j +1 th stage second shift register 101, and accordingly, the second trigger signal line is used to provide a trigger signal for the 1 st stage second shift register, so that the display panel 10 may exhibit a display effect of "bright top and dark bottom".

Specifically, the first switching element K1 may be provided, for example, between the i-th stage first shift register 101 and the i + 1-th stage first shift register 101. The third switching element K3 may be provided, for example, between the j-th stage second shift register 102 and the j + 1-th stage second shift register 102. When the display panel 10 displays a picture at the first refresh rate, the first switching element K1 is turned off in response to the off level output from the first control signal line S1, thereby disconnecting the cascade relationship between the first shift registers 101 of the plurality of stages in the first scan driving circuit S1 ', such as the cascade relationship between the first shift register 101 of the i-th stage and the first shift register 101 of the i + 1-th stage in the first scan driving circuit S1'. Likewise, the third switching element K2 is turned off in response to the turn-off level of the third control signal line S3, thereby turning off the cascade relationship between the plurality of stages of the second shift register 102 in the second scan driving circuit S2 ', such as the cascade relationship between the j-th stage of the second shift register 102 and the j + 1-th stage of the second shift register 102 in the second scan driving circuit S2'. Thus, the display panel 10 is divided into two display areas, such as a first display area AA1 and a second display area AA2, which can be independently displayed.

Meanwhile, the second switching element K2 is turned on IN response to the on level of the second control signal line S2, and transmits the first trigger signal of the first trigger signal line SIN to the input terminal IN of the i +1 th stage first shift register 101. In this way, the i +1 th stage first shift register 101 and the 1 st stage first shift register 101 may receive the first trigger signal at the same time, and it is ensured that the p +1 th row of sub-pixels and the 1 st row of sub-pixels perform data writing at the same time, for example, it may be implemented that the first display area AA1 is scanned by using the original one-frame time for scanning the entire display area (the sum of the first display area AA1 and the second display area AA 2), so as to increase the data writing time of each row of sub-pixels in the first display area AA 1.

Meanwhile, the fourth switching element K4 is turned on IN response to the on level of the fourth control signal line S4, transmitting the off level of the off-level power supply signal line VGH to the input terminal IN of the j +1 th stage second shift register 102. Since the second shift register 102 controls the sub-pixels PX to emit light, by transmitting the off-level to the input terminal IN of the j +1 th stage second shift register 102, the respective rows of sub-pixels PX (i.e., the p +1 th row of sub-pixels to the last 1 row of sub-pixels) IN the second display area AA2 may be maintained IN the black state, and no picture is displayed. The second trigger signal line EIN provides a trigger signal for the second shift register 102 at level 1, so that each row of sub-pixels PX (i.e. the sub-pixels at row 1 to the sub-pixels at row p) in the first display area AA1 can normally emit light, and the first display area AA1 can display a picture. Therefore, by only displaying the picture in the first display area AA1, although the resolution is reduced, the data writing time of each row of sub-pixels in the first display area AA1 is increased, so that the problem of poor display effect of the display panel due to insufficient data writing time can be solved.

Fig. 4 is a diagram showing the effect of the embodiment shown in fig. 3a and 3 b. As shown in fig. 4, corresponding to the embodiment shown in fig. 3a and fig. 3b, the first display area AA1 where the sub-pixels in the row 1 to the sub-pixels in the row p are located may display a picture, and the second display area AA2 where the sub-pixels in the row p +1 to the sub-pixels in the row last 1 are located may maintain a black state, that is, display effect of "bright top and black bottom" is presented.

It is easily understood that the parameter i in the embodiment shown in fig. 1a and 1b is not equal to the parameter i in the embodiment shown in fig. 3a and 3b, i may be equal to 520 if the scheme of "light-up-black-down" in the embodiment shown in fig. 1a and 1b is adopted, and i may be equal to 2600 if the scheme of "light-up-black-down" in the embodiment shown in fig. 3a and 3b is adopted. Similarly, the parameter j in the embodiment shown in fig. 1a and 1b is not equal to the parameter j in the embodiment shown in fig. 3a and 3b, and the parameter p in the embodiment shown in fig. 1a and 1b is not equal to the parameter p in the embodiment shown in fig. 3a and 3 b.

As shown in fig. 5a and 5b, according to further embodiments of the present application, optionally, unlike the embodiment shown in fig. 1a and 1b, the display panel 10 may further include a third display area AA 3. The second display area AA2 has a third critical pixel row q, i.e. a q-th row of sub-pixels PX. The third display area AA3 has a fourth critical pixel row q +1, i.e., a q +1 th row of sub-pixels PX. The x-th stage first shift register 101 and the y-th stage second shift register 102 are connected to the third critical pixel row q. The x +1 th stage first shift register 101 and the y +1 th stage second shift register 102 are connected to a fourth critical pixel row q +1, where x, y, and q are positive integers, x ≠ i, q ≠ p, and y ≠ j.

The fifth switching element K5 is provided between any adjacent first shift register 101 in the x-th stage first shift register 101 to the last stage first shift register 101. For example, the fifth switching element K5 may be disposed between the x-th stage first shift register 101 and the x + 1-th stage first shift register 101. The sixth switching element K6 is disposed between the first trigger signal line SIN and the x +1 th stage first shift register 101. The seventh switching element K7 is provided between any adjacent second shift registers 102 in the y-th stage second shift register 102 to the last stage second shift register 102. For example, the seventh switching element K7 may be disposed between the y-th stage second shift register 102 to the y + 1-th stage second shift register 102. The eighth switching element K8 is disposed between the off-level power supply signal line VGH and the y +1 th stage second shift register 102.

When the fifth switching element K5 and the seventh switching element K7 are turned on and the sixth switching element K6 and the eighth switching element K8 are turned off, the third display area AA3 displays the information. When the fifth switching element K5 and the seventh switching element K7 are turned off and the sixth switching element K6 and the eighth switching element K8 are turned on, the third display area AA3 stops operating. Thus, by controlling the fifth switching element K5, the sixth switching element K6, the seventh switching element K7 to be turned on and the eighth switching element K8 to be turned on/off, the independent display or stop of the third display area AA3 may be driven.

In other embodiments of the present application, optionally, the third display area AA3 may further cooperate with the first display area AA1 and the second display area AA2 to achieve a display effect of "black on top and bright black on bottom".

Specifically, in connection with the embodiment shown in fig. 1a and 1b, the fourth switching element K4 is electrically connected to the stage 1 second shift register 102. The first switching element K1 is provided between any adjacent first shift registers 101 in the 1 st to i +1 th stages of first shift registers 101, and the third switching element K3 is provided between any adjacent second shift registers 102 in the 1 st to j +1 th stages of second shift registers 102.

When the first, third, fifth, and seventh switching elements K1, K3, K5, and K7 are turned on and the second, fourth, sixth, and eighth switching elements K2, K4, K6, and K8 are turned off, the first, second, and eighth display areas AA1, AA2 and AA3 are commonly displayed. When the first, third, fifth and seventh switching elements K1, K3, K5 and K7 are turned off and the second, fourth, sixth and eighth switching elements K2, K4, K6 and K8 are turned on, the first and third display areas AA1 and AA3 are simultaneously turned off to realize a display effect of "black on top and black on middle and bright on black on bottom".

For ease of understanding, the circuit structure shown in fig. 5a and 5b will be described in detail below.

Taking an example IN which the fifth switching element K5 is disposed between the x-th stage first shift register 101 and the x + 1-th stage first shift register 101, the seventh switching element K7 is disposed between the y-th stage second shift register 102 and the y + 1-th stage second shift register 102, a control terminal of the fifth switching element K5 is electrically connected to the fifth control signal line S5, a first terminal of the fifth switching element K5 is electrically connected to the output terminal Gout of the x-th stage first shift register 101, a second terminal of the fifth switching element K5 is electrically connected to the input terminal IN of the x + 1-th stage first shift register 101, the x-th stage first shift register 101 is used to control writing of data signals of the sub-pixels PX of the q-th row, and x and q are positive integers. In the embodiment of the present application, x ≠ i, q ≠ p, that is, the x-th stage first shift register and the i-th stage first shift register are different stages of first shift registers, and the q-th row sub-pixels and the p-th row sub-pixels are different rows of sub-pixels.

A control terminal of the sixth switching element K6 is electrically connected to the sixth control signal line S6, a first terminal of the sixth switching element K6 is electrically connected to the first trigger signal line SIN, and a second terminal of the sixth switching element K6 is electrically connected to the input terminal IN of the x +1 th stage first shift register 101. A control terminal of the seventh switching element K7 is electrically connected to the seventh control signal line S7, a first terminal of the seventh switching element K7 is electrically connected to the output terminal Gout of the y-th stage second shift register 102, a second terminal of the seventh switching element K7 is electrically connected to the input terminal IN of the y + 1-th stage second shift register 102, the y-th stage second shift register 102 is configured to provide a light emission control signal to the sub-pixels IN the q-th row, and y is a positive integer. It should be noted that, in the embodiment of the present application, y ≠ j, that is, the y-th stage second shift register and the j-th stage second shift register are different stages of second shift registers. Alternatively, y may be equal to x. A control terminal of the eighth switching element K8 is electrically connected to the eighth control signal line S8, a first terminal of the eighth switching element K8 is electrically connected to the off-level power supply signal line VGH, and a second terminal of the eighth switching element K8 is electrically connected to the input terminal IN of the y +1 th stage second shift register 102.

Next, the operation states of the respective switching elements when the display panel 10 displays a screen at the first refresh rate will be described.

When the display panel 10 displays a screen at the first refresh rate, the first switching element K1, the third switching element K3, the fifth switching element K5, and the seventh switching element K7 are turned off (turned off). Thus, the display panel 10 may be divided into three sub-regions, such as the first display area AA1, the second display area AA2 and the third display area AA3, which can be independently displayed.

Meanwhile, the second switching element K2 and the sixth switching element K6 are turned on. Thus, the i +1 th stage first shift register 101 may receive the first trigger signal simultaneously with the 1 st stage first shift register 101 and the x +1 th stage first shift register 101, so as to ensure that the p +1 th row of sub-pixels, the 1 st row of sub-pixels, and the q +1 th row of sub-pixels perform data writing simultaneously, for example, it may be implemented to scan the second display area AA2 by using a frame time of originally scanning the entire display area (the sum of the first display area AA1, the second display area AA2, and the third display area AA 3), thereby increasing the data writing time of each row of sub-pixels in the second display area AA 2.

Meanwhile, the fourth switching element K4 is turned on IN response to the on level of the fourth control signal line S4, transmitting the off level of the off-level power supply signal line VGH to the input terminal IN of the 1 st stage second shift register 102. The eighth switching element K8 is turned on IN response to the on level of the eighth control signal line S8, and transmits the off level of the off-level power supply signal line VGH to the input terminal IN of the y +1 th stage second shift register 102. Since the second shift register 102 controls the sub-pixels PX to emit light, by transmitting an off-level to the input terminal IN of the 1 st stage second shift register 102 and the input terminal IN of the y +1 th stage second shift register 102, it is possible to make each row of sub-pixels PX (i.e., the 1 st row sub-pixels to the p th row sub-pixels) IN the first display area AA1 and each row of sub-pixels PX (the q +1 th row sub-pixels to the last 1 row sub-pixels) IN the third display area AA3 maintain a black state, and not to display a picture. The second trigger signal line EIN provides a trigger signal for the j +1 th stage second shift register 102, so that each row of sub-pixels PX (i.e., the p +1 th row of sub-pixels to the q-th row of sub-pixels) in the second display area AA2 can normally emit light, and the second display area displays a picture. Therefore, only the second display area is reserved for displaying the picture, the resolution is reduced, but the data writing time of each row of sub-pixels in the second display area is increased, and the problem of poor display effect of the display panel caused by insufficient data writing time can be solved.

Fig. 6 is a diagram showing the effect of the embodiment shown in fig. 5a and 5 b. As shown in fig. 6, corresponding to the embodiment shown in fig. 5a and 5b, the first display area AA1 where the sub-pixels in the row 1 to the row p are located may be kept in a black state, the second display area AA2 where the sub-pixels in the row p +1 to the row q are located may display a picture, and the third display area AA3 where the sub-pixels in the row q +1 to the last row 1 are located may be kept in a black state, that is, a display effect of "black-up, middle-bright and black-down" is presented.

As shown in fig. 7, according to some embodiments of the present application, the display panel 10 may further optionally include a ninth switching element K9, the ninth switching element K9 being disposed between the second trigger signal line EIN and the 1 st stage second shift register 102. Specifically, a control terminal of the ninth switching element K9 is electrically connected to the ninth control signal line S9, a first terminal of the ninth switching element K9 is electrically connected to the second trigger signal line EIN, and a second terminal of the ninth switching element K9 is electrically connected to the input terminal IN of the 1 st stage second shift register 102.

When the display panel 10 displays a screen at the first refresh rate higher than the preset refresh rate threshold, the fourth switching element K4 is turned on IN response to the on level output from the fourth control signal line S4, transmitting the off level of the off-level power supply signal line VGH to the input terminal IN of the 1 st stage second shift register 102. The ninth switching element K9 is turned off in response to the off level output from the ninth control signal line S9, and prevents the second trigger signal output from the second trigger signal line EIN from entering the second shift register 102 of the 1 st stage, thereby preventing the second trigger signal from interfering with the off level of the off level power supply signal line VGH output, and ensuring the stability of the sub-pixel in the first display region to maintain the black state.

When the display panel 10 displays a picture at the second refresh rate lower than the preset refresh rate threshold, the fourth switching element K4 is turned off in response to the turn-off level output by the fourth control signal line S4, the ninth switching element K9 is turned on in response to the turn-on level output by the ninth control signal line S9, and the second trigger signal output by the second trigger signal line EIN is transmitted to the 1 st-stage second shift register 102, so as to implement full-screen display.

In this way, the ninth switching element K9 is added to not only realize full-screen display, but also avoid the interference of the second trigger signal to the cut-off level output by the cut-off level power signal line VGH when the display panel 10 displays a picture at the first refresh rate.

As shown in fig. 8, according to some embodiments of the present application, the display panel 10 may further optionally include a tenth switching element K10, the tenth switching element K10 being disposed between the second trigger signal line EIN and the j +1 th stage second shift register 102. Specifically, a control terminal of the tenth switching element K10 is electrically connected to the tenth control signal line S10, a first terminal of the tenth switching element K10 is electrically connected to the second trigger signal line EIN, and a second terminal of the tenth switching element K10 is electrically connected to the input terminal IN of the j +1 th stage second shift register 102.

When the display panel 10 displays a picture at the first refresh rate, the tenth switching element K10 is turned on IN response to the on level output from the tenth control signal line S10, and transmits the second trigger signal output from the second trigger signal line EIN to the input terminal IN of the j +1 th stage second shift register 102, so that the second display region displays a picture. When the display panel 10 displays a picture at the second refresh rate, the tenth switching element K10 is turned off IN response to the turn-off level output by the tenth control signal line S10, and the second trigger signal output by the second trigger signal line EIN is prevented from entering the input terminal IN of the j +1 th stage second shift register 102, so that the signal disorder during full-screen display is avoided.

As shown in fig. 9a and 9b, according to some embodiments of the present application, optionally, in a case where a first display region in which the sub-pixels in the row 1 to the row p are located maintains a black state, and a second display region in which the sub-pixels in the row p +1 to the last row 1 are located displays a picture, the first display region may be used as the target display region a. Accordingly, the display panel 10 may further include a plurality of eleventh switching elements K11, a plurality of twelfth switching elements K12, a plurality of thirteenth switching elements K13, and a plurality of fourteenth switching elements K14.

The eleventh switching element K11 is provided between the output terminal of the first shift register 101 corresponding to the sub-pixels of the even rows in the target display area a and the input terminal of the first shift register 101 corresponding to the sub-pixels of the odd rows in the target display area a. Specifically, a control terminal of the eleventh switching element K11 is electrically connected to the eleventh control signal line S11, a first terminal of the eleventh switching element K11 is electrically connected to the output terminal Gout of the first shift register 101 corresponding to the even-row sub-pixels of the target display area a, and a second terminal of the eleventh switching element K11 is electrically connected to the input terminal IN of the first shift register 101 corresponding to the odd-row sub-pixels of the target display area a. For example, a first terminal of one of the eleventh switching elements K11 is electrically connected to the output terminal Gout of the first shift register 101 corresponding to the 2 nd row of sub-pixels of the target display area a, and a second terminal thereof is electrically connected to the input terminal IN of the first shift register 101 corresponding to the 3 rd row of sub-pixels of the target display area a. For another example, a first terminal of one of the eleventh switching elements K11 is electrically connected to the output terminal Gout of the first shift register 101 corresponding to the 4 th row of sub-pixels of the target display area a, and a second terminal thereof is electrically connected to the input terminal IN of the first shift register 101 corresponding to the 5 th row of sub-pixels of the target display area a.

The twelfth switching element K12 is disposed between the first trigger signal line SIN and the first shift register 101 corresponding to the sub-pixels in the odd rows in the target display area a. Specifically, a control terminal of the twelfth switching element K12 is electrically connected to the twelfth control signal line S12, a first terminal of the twelfth switching element K12 is electrically connected to the first trigger signal line SIN, and a second terminal of the twelfth switching element K12 is electrically connected to the input terminal IN of the first shift register 101 corresponding to the sub-pixels IN the odd-numbered rows of the target display area a. For example, a second terminal of one of the twelfth switching elements K12 is electrically connected to the input terminal IN of the first shift register 101 corresponding to the 3 rd row of sub-pixels of the target display area a. For another example, the second terminal of one of the twelfth switching elements K12 is electrically connected to the input terminal IN of the first shift register 101 corresponding to the sub-pixel of the 5 th row of the target display area a.

It should be noted that, in the embodiment of the present application, the first shift register corresponding to the nth row of sub-pixels in the target display area refers to a first shift register that controls writing of data signals of the nth row of sub-pixels, for example, the first shift register corresponding to the 2 nd row of sub-pixels in the target display area refers to a first shift register that controls writing of data signals of the 2 nd row of sub-pixels, and n is a positive integer.

The thirteenth switching element K13 is provided between the output terminal of the second shift register corresponding to the sub-pixel of the even row in the target display area and the input terminal of the second shift register corresponding to the sub-pixel of the odd row in the target display area. Specifically, a control terminal of the thirteenth switching element K13 is electrically connected to the thirteenth control signal line S13, a first terminal of the thirteenth switching element K13 is electrically connected to the output terminal Gout of the second shift register 102 corresponding to the even-row sub-pixels of the target display area a, and a second terminal of the thirteenth switching element K13 is electrically connected to the input terminal IN of the second shift register 102 corresponding to the odd-row sub-pixels of the target display area a.

The fourteenth switching element K14 is disposed between the off-level power supply signal line and the second shift register corresponding to the sub-pixels of the odd-numbered row in the target display area. Specifically, a control terminal of the fourteenth switching element K14 is electrically connected to the fourteenth control signal line S14, a first terminal of the fourteenth switching element K14 is electrically connected to the off-level power supply signal line VGH, and a second terminal of the fourteenth switching element K14 is electrically connected to the input terminal IN of the second shift register 102 corresponding to the odd-numbered sub-pixels of the target display area a.

When the display panel 10 displays a picture at the first refresh rate, the eleventh switching element K11 is turned off in response to the off level output from the eleventh control signal line S11, thereby disconnecting the cascade relationship between the first shift register 101 corresponding to the sub-pixels of the even rows in the target display area a and the first shift register 101 corresponding to the sub-pixels of the odd rows in the target display area a. The thirteenth switching element K13 is turned off in response to the off level output from the thirteenth control signal line S13, thereby disconnecting the cascade relationship between the second shift register 102 corresponding to the sub-pixels of the even rows in the target display area a and the second shift register 102 corresponding to the sub-pixels of the odd rows in the target display area a. The twelfth switching element K12 is turned on IN response to the on level of the twelfth control signal line S12, and transmits the first trigger signal of the first trigger signal line SIN to the input terminal IN of the first shift register 101 corresponding to the sub-pixels on the odd-numbered rows of the target display area a. The fourteenth switching element K14 is turned on IN response to the on level output from the fourteenth control signal line S14, transmits the off level of the off-level power supply signal line VGH to the input terminals IN of the second shift register 102 corresponding to the odd-numbered rows of sub-pixels of the target display area a to transmit the light emission control signal to each row of sub-pixels IN the target display area a IN the state of the off level with the cascade relationship between the shift registers being disconnected, so that each row of sub-pixels PX IN the target display area a maintains the black state.

It should be noted that, in the embodiment of the present application, the eleventh switching element K11 is disposed between the first shift register 101 corresponding to the even-row sub-pixels of the target display area a and the first shift register 101 corresponding to the odd-row sub-pixels of the target display area a, and the thirteenth switching element K13 is disposed between the second shift register 102 corresponding to the even-row sub-pixels of the target display area a and the second shift register 102 corresponding to the odd-row sub-pixels of the target display area a, because in practice, the two shift registers are in one group, and one group of shift registers belongs to the same electronic device, i.e., one electronic device includes two shift registers, the eleventh switching element K11 and the thirteenth switching element K13 are disposed between the two electronic devices. It is easily understood that, in the case where one shift register is a stand-alone device, the eleventh switching element K11 and the thirteenth switching element K13 may be disposed between shift registers corresponding to sub-pixels of adjacent rows, and the twelfth switching element K12 and the fourteenth switching element K14 may be disposed at an input terminal of a shift register corresponding to a sub-pixel of each row in the target display area.

As shown in fig. 10a and 10b, according to other embodiments of the present application, alternatively, different from the embodiments shown in fig. 9a and 9b, in a case that a first display region where the sub-pixels in the row 1 to the row p are located displays a picture, and a second display region where the sub-pixels in the row p +1 to the row last 1 are located maintains a black state, the second display region may be used as the target display region a. Accordingly, the display panel 10 may further include a plurality of eleventh switching elements K11, a plurality of twelfth switching elements K12, a plurality of thirteenth switching elements K13, and a plurality of fourteenth switching elements K14. The connection and operation of the eleventh, twelfth, thirteenth and fourteenth switching elements K11, K12, K13 and K14 in the embodiment shown in fig. 10a and 10b are similar to those in the embodiment shown in fig. 9a and 9b, and therefore, for brevity of description, they will not be described again.

As shown in fig. 11a and 11b, according to further embodiments of the present application, optionally, different from the embodiments shown in fig. 9a and 9b, a first display area where the sub-pixels in the row 1 to the row p are located is kept in a black state, a second display area where the sub-pixels in the row p +1 to the row q are located is used for displaying a picture, and a third display area where the sub-pixels in the row q +1 to the last row 1 are located is kept in a black state, the first display area and the third display area may be used as the target display area a. Accordingly, the display panel 10 may further include a plurality of eleventh switching elements K11, a plurality of twelfth switching elements K12, a plurality of thirteenth switching elements K13, and a plurality of fourteenth switching elements K14.

The eleventh switching element K11, the twelfth switching element K12, the thirteenth switching element K13 and the fourteenth switching element K14 in the embodiment shown in fig. 11a and 11b are connected in a similar manner and in an operating state to the embodiment shown in fig. 9a and 9 b.

The following describes the display panel according to the embodiment of the present application with reference to specific examples shown in fig. 12a and 12 b.

As shown in fig. 12a and 12b, according to some embodiments of the present application, optionally, control signal lines controlling the first switching element and the third switching element to be turned on or off are multiplexed, and/or control signal lines controlling the second switching element and the fourth switching element to be turned on or off are multiplexed. In some more specific embodiments, control signal lines that control the first, third, fifth, and seventh switching elements to be turned on or off are multiplexed, and/or control signal lines that control the second, fourth, sixth, and eighth switching elements to be turned on or off are multiplexed. Specifically, at least two of the first control signal line S1, the third control signal line S3, the fifth control signal line S5, the seventh control signal line S7, the ninth control signal line S9, the eleventh control signal line S11, and the thirteenth control signal line S13 may be multiplexed. Similarly, at least two of the second control signal line S2, the fourth control signal line S4, the sixth control signal line S6, the eighth control signal line S8, the tenth control signal line S10, the twelfth control signal line S12, and the fourteenth control signal line S14 may be multiplexed.

Therefore, the control signal lines are multiplexed, so that the number of the control signal lines in the display panel can be reduced, the occupied space of wiring is reduced, and the production cost is reduced.

With continued reference to fig. 12a and 12b, in practical applications, in addition to the first trigger signal line SIN, the first shift register 101 of each stage may be electrically connected to the first clock signal line SCK1 and the second clock signal line SCK2 to control the output terminal Gout of the first shift register 101 to output an on level or an off level. Similarly, in addition to the second shift register 102 of each stage being connected to the second trigger signal line EIN, the second shift register 102 of each stage may be electrically connected to the third clock signal line ECK1 and the fourth clock signal line ECK2 to control the output terminal Gout of the second shift register 102 to output an on level or an off level.

With continued reference to fig. 12a and 12b, according to some embodiments of the present application, optionally, the first switching element K1 may include a first transistor T1, a gate of the first transistor T1 is electrically connected to the first control signal line S1, a first pole of the first transistor T1 is electrically connected to the output terminal Gout of the i-th stage first shift register 101, and a second pole of the first transistor T1 is electrically connected to the input terminal IN of the i + 1-th stage first shift register 101.

The second switching element K2 may include a second transistor T2, a gate of the second transistor T2 being electrically connected to the second control signal line S2, a first pole of the second transistor T2 being electrically connected to the first trigger signal line SIN, and a second pole of the second transistor T2 being electrically connected to the input terminal IN of the i +1 th stage first shift register 101.

The third switching element K3 may include a third transistor T3, a gate of the third transistor T3 being electrically connected to the third control signal line S3, a first pole of the third transistor T3 being electrically connected to the output terminal Gout of the j-th stage second shift register 101, and a second pole of the third transistor T3 being electrically connected to the input terminal IN of the j + 1-th stage second shift register 101.

The fourth switching element K4 may include a fourth transistor T4, a gate of the fourth transistor T4 being electrically connected to the fourth control signal line S4, a first pole of the fourth transistor T4 being electrically connected to the off-level power supply signal line VGH, and a second pole of the fourth transistor T4 being electrically connected to the input terminal IN of the 1 st-stage second shift register 101.

The first trigger signal line SIN may be electrically connected to the input terminal IN of the 1 st stage first shift register 101 to provide a first trigger signal to the 1 st stage first shift register 101. The second trigger signal line EIN may be electrically connected to the input terminal IN of the j +1 th stage second shift register 102 to provide a second trigger signal to the j +1 th stage second shift register 102.

The fifth switching element K5 may include a fifth transistor T5, a gate of the fifth transistor T5 being electrically connected to the fifth control signal line S5, a first pole of the fifth transistor T5 being electrically connected to the output terminal Gout of the x-th stage first shift register 101, and a second pole of the fifth transistor T5 being electrically connected to the input terminal IN of the x + 1-th stage first shift register 101.

The sixth switching element K6 may include a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the sixth control signal line S6, a first pole of the sixth switching element K6 is electrically connected to the first trigger signal line SIN, and a second pole of the sixth switching element K6 is electrically connected to the input terminal IN of the x +1 th stage first shift register 101.

The seventh switching element K7 may include a seventh transistor T7, a gate of the seventh transistor T7 being electrically connected to the seventh control signal line S7, a first pole of the seventh transistor T7 being electrically connected to the output terminal Gout of the y-th stage second shift register 102, and a second pole of the seventh transistor T7 being electrically connected to the input terminal IN of the y + 1-th stage second shift register 102.

The eighth switching element K8 may include an eighth transistor T8, a gate of the eighth transistor T8 being electrically connected to the eighth control signal line S8, a first pole of the eighth transistor T8 being electrically connected to the off-level power supply signal line VGH, and a second pole of the eighth transistor T8 being electrically connected to the input terminal IN of the y +1 th stage second shift register 102.

The ninth switching element K9 may include a ninth transistor T9, a gate of the ninth transistor T9 being electrically connected to the ninth control signal line S9, a first pole of the ninth transistor T9 being electrically connected to the second trigger signal line EIN, and a second pole of the ninth transistor T9 being electrically connected to the input terminal IN of the 1 st stage second shift register 102.

The tenth switching element K10 may include a tenth transistor T10, a gate of the tenth transistor T10 electrically connected to the tenth control signal line S10, a first pole of the tenth transistor T10 electrically connected to the second trigger signal line EIN, and a second pole of the tenth transistor T10 electrically connected to the input terminal IN of the j +1 th stage second shift register 102.

The eleventh switching element K11 may include an eleventh transistor T11, a gate of the eleventh transistor T11 being electrically connected to the eleventh control signal line S11, a first pole of the eleventh transistor T11 being electrically connected to the output terminal Gout of the first shift register 101 corresponding to the even-row sub-pixels of the target display area a, and a second pole of the eleventh transistor T11 being electrically connected to the input terminal IN of the first shift register 101 corresponding to the odd-row sub-pixels of the target display area a.

The twelfth switching element K12 may include a twelfth transistor T12, a gate of the twelfth transistor T12 is electrically connected to the twelfth control signal line S12, a first pole of the twelfth transistor T12 is electrically connected to the first trigger signal line SIN, and a second pole of the twelfth transistor T12 is electrically connected to the input terminal IN of the first shift register 101 corresponding to the sub-pixels of the odd-numbered row of the target display area a.

The thirteenth switching element K13 may include a thirteenth transistor T13, a gate of the thirteenth transistor T13 being electrically connected to the thirteenth control signal line S13, a first pole of the thirteenth transistor T13 being electrically connected to the output terminal Gout of the second shift register 102 corresponding to the even-row sub-pixels of the target display area a, and a second pole of the thirteenth transistor T13 being electrically connected to the input terminal IN of the second shift register 102 corresponding to the odd-row sub-pixels of the target display area a.

The fourteenth switching element K14 may include a fourteenth transistor T10, a gate of the fourteenth transistor T10 being electrically connected to the fourteenth control signal line S14, a first pole of the fourteenth transistor T10 being electrically connected to the off-level power supply signal line VGH, and a second pole of the fourteenth transistor T10 being electrically connected to the input terminal IN of the second shift register 102 corresponding to the odd-numbered row of subpixels of the target display area a.

When the display panel 10 displays a picture at the second refresh rate lower than the preset refresh rate threshold, the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned on under the control of the first control signal line S1, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 are turned off. The first trigger signal output by the first trigger signal line SIN enters the first shift register 101 at the 1 st level, the second trigger signal output by the second trigger signal line EIN enters the second shift register 102 at the 1 st level, and full-screen display is realized through signal transmission between the cascade wiring lines.

When the display panel 10 displays a picture at a first refresh rate higher than a preset refresh rate threshold, the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned off under the control of the first control signal line S1, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 are turned on under the control of the second control signal line S2. The second transistor T2 transmits the first trigger signal of the first trigger signal line SIN to the input terminal IN of the i +1 th stage first shift register 101. The sixth transistor T6 transmits the first trigger signal of the first trigger signal line SIN to the input terminal IN of the x +1 th stage first shift register 101. Thus, the i +1 th stage first shift register 101 can receive the first trigger signal simultaneously with the 1 st stage first shift register 101 and the x +1 th stage first shift register 101, so as to ensure that the p +1 th row of sub-pixels, the 1 st row of sub-pixels and the q +1 th row of sub-pixels perform data writing simultaneously, for example, the second display area can be scanned by using one frame time of originally scanning the whole display area (the sum of the first display area and the second display area), thereby increasing the data writing time of each row of sub-pixels in the second display area.

Meanwhile, the fourth transistor T4 transmits the off-level of the off-level power supply signal line VGH to the input terminal IN of the 1 st stage second shift register 102. The eighth transistor T8 transmits the off-level of the off-level power supply signal line VGH to the input terminal IN of the y +1 th stage second shift register 102. Since the second shift register 102 controls the sub-pixels PX to emit light, by transmitting an off level to the input terminal IN of the 1 st stage second shift register 102 and the input terminal IN of the j +1 th stage second shift register 102, it is possible to cause each row of the sub-pixels PX (i.e., the 1 st row sub-pixels to the p th row sub-pixels) IN the first display area and each row of the sub-pixels PX (the q +1 th row sub-pixels to the last 1 row sub-pixels) IN the third display area to maintain a black state, and not to display a picture. The tenth transistor T10 transmits the second trigger signal output from the second trigger signal line EIN to the j +1 th stage second shift register 102, so that each row of sub-pixels PX (i.e., the p +1 th to q-th rows of sub-pixels) in the second display region can normally emit light, and the second display region displays a picture. Therefore, only the second display area is reserved for displaying the picture, the resolution is reduced, but the data writing time of each row of sub-pixels in the second display area is increased, and the problem of poor display effect of the display panel caused by insufficient data writing time can be solved.

It should be noted that, in addition to the single-side driving (or called single-side scanning) manner shown in fig. 12a and 12b, the display panel 10 of the embodiment of the present invention may also adopt a double-side driving (or called double-side scanning) manner. That is, in addition to the first scan driving circuit S1 'provided in the non-display region on the left side of the display panel 10 shown in fig. 12a, the same first scan driving circuit S1' as the left side may be provided in the non-display region on the right side of the display panel 10, and the connection relationship of the respective transistors in the first scan driving circuit S1 'provided on the right side may be the same as the connection relationship of the respective transistors in the first scan driving circuit S1' provided on the left side. Likewise, in addition to the second scan driving circuit S2 'provided in the non-display region on the left side of the display panel 10 shown in fig. 12b, the same second scan driving circuit S2' as the left side may be provided in the non-display region on the right side of the display panel 10, and the connection relationship of the respective transistors in the second scan driving circuit S2 'provided on the right side may be the same as the connection relationship of the respective transistors in the second scan driving circuit S2' provided on the left side.

Based on the display panel 10 provided in the foregoing embodiment, correspondingly, the present application further provides a driving method applied to the display panel 10 provided in the foregoing embodiment, which mainly includes:

when the display panel displays the picture at a first refresh rate higher than a preset refresh rate threshold, the first switch element and the third switch element are controlled to be closed, and the second switch element and the fourth switch element are controlled to be opened, so that any one of the first display area and the second display area stops working.

Specifically, when the display panel displays a picture at a first refresh rate higher than a preset refresh rate threshold, the first control signal line and the third control signal line output a turn-off level, and the second control signal line and the fourth control signal line output a turn-on level; the first switching element is turned off in response to an off level of the first control signal line; the second switch element is turned on in response to the on level of the second control signal line, and transmits the first trigger signal of the first trigger signal line to the input end of the (i + 1) th stage first shift register; the third switching element turns off in response to an off level of the third control signal line; the fourth switching element is turned on in response to an on level of the fourth control signal line, and transmits an off level of the off level power supply signal line to the input terminal of the 1 st stage second shift register or the input terminal of the j +1 th stage second shift register.

According to the driving method provided by the embodiment of the application, under the condition that the refresh rate is not reduced, the data writing time of each row of sub-pixels is increased by reducing the resolution, and the problem of poor display effect caused by insufficient data writing time is solved.

According to some embodiments of the present application, optionally, as shown in fig. 5a and 5b, the display panel 10 may further include a third display area AA3, see the above description. Accordingly, the driving method may further include: when the display panel displays a picture at a first refresh rate higher than a preset refresh rate threshold, controlling the first display area and the third display area to stop working at the same time; the first display area and the third display area are respectively positioned at two sides of the second display area.

Specifically, the fifth control signal line and the seventh control signal line output off levels, and the sixth control signal line and the eighty-four control signal line output on levels; a fifth switching element turned off in response to an off level of the fifth control signal line; the sixth switching element is turned on in response to the on level of the sixth control signal line, and transmits the first trigger signal of the first trigger signal line to the input terminal of the x +1 th stage first shift register; a seventh switching element turned off in response to an off level of the seventh control signal line; the eighth switching element is turned on in response to an on level of the eighth control signal line, and transmits an off level of the off level power supply signal line to an input terminal of the j +1 th stage second shift register.

According to some embodiments of the present application, optionally, the display panel 10 may further include a ninth switch element K9, please refer to the above description for details of connection relationship. Accordingly, the driving method may further include: the ninth switching element is turned off in response to the turn-off level of the ninth control signal line output. Thus, the second trigger signal output by the second trigger signal line can be prevented from entering the second shift register of the 1 st stage, so that the interference of the second trigger signal on the cut-off level output by the cut-off level power signal line is avoided, and the stability of keeping the sub-pixels in the first display area in a black state is ensured.

According to some embodiments of the present application, the display panel 10 may further optionally include a tenth switching element K10, and the specific connection relationship is described above. Accordingly, the driving method may further include: the tenth switching element is turned on in response to the on level output from the tenth control signal line, and transmits the second trigger signal output from the second trigger signal line to the input terminal of the j +1 th stage second shift register.

According to some embodiments of the present application, optionally, the display panel 10 may further include a plurality of eleventh switching elements K11, a plurality of twelfth switching elements K12, a plurality of thirteenth switching elements K13 and a plurality of fourteenth switching elements K14, and the specific connection relationship is described above. Accordingly, the driving method may further include: the eleventh switching element turns off in response to an off level of the eleventh control signal line output; the twelfth switching element is turned on in response to the turn-on level of the twelfth control signal line, and transmits the first trigger signal of the first trigger signal line to the input end of the first shift register corresponding to the sub-pixels in the odd rows of the target display area; the thirteenth switching element is turned off in response to the turn-off level of the thirteenth control signal line output; the fourteenth switching element is turned on in response to the on level output from the fourteenth control signal line, and transmits the off level of the off level power supply signal line to the input terminal of the second shift register corresponding to the odd-numbered row of sub-pixels of the target display area.

The specific process of the driving method has been described in detail in the above display panel embodiment, and is not repeated herein for brevity.

Based on the display panel provided by the above embodiment, correspondingly, the application further provides a display device. As shown in fig. 13, the display device 100 may include a device body 20 and the display panel 10 in the above embodiment, and the display panel 10 is covered on the device body 20. The apparatus body 20 may be provided with various devices, such as a sensing device, a processing device, and the like, but is not limited thereto. The display device 100 may be a device having a display function, such as a mobile phone, a computer, a tablet computer, a digital camera, a television, and electronic paper, and is not limited herein.

It should be clear that the embodiments in this specification are described in a progressive manner, and the same or similar parts in the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. For the display panel embodiment and the display device embodiment, the related matters can be referred to the description parts of the pixel driving circuit embodiment and the array substrate embodiment. The present application is not limited to the particular structures described above and shown in the figures. Those skilled in the art may make various changes, modifications and additions after comprehending the spirit of the present application. Also, a detailed description of known techniques is omitted herein for the sake of brevity.

It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantities relate to "a" and "an" but do not exclude a plurality; the terms "first" and "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A display panel is characterized by comprising a first scanning driving circuit, a second scanning driving circuit and a plurality of rows of sub-pixels, wherein the first scanning driving circuit comprises a first trigger signal line and a cascaded multi-stage first shift register, the second scanning driving circuit comprises a second trigger signal line and a cascaded multi-stage second shift register, each stage of the first shift register is electrically connected with at least one row of sub-pixels, and each stage of the second shift register is electrically connected with at least one row of sub-pixels;

the display panel comprises a first display area and a second display area, wherein the first display area is provided with a first critical pixel row p, and the second display area is provided with a second critical pixel row p + 1; the ith stage first shift register and the jth stage second shift register are connected to the first critical pixel row p; the (i + 1) th stage first shift register and the (j + 1) th stage second shift register are connected to the second critical pixel row p + 1;

the first switching elements are arranged between adjacent first shift registers; the second switching element is arranged between the first trigger signal line and the (i + 1) th stage first shift register; the third switching element is arranged between the adjacent second shift registers; a fourth switching element is provided between the off-level power supply signal line and the j +1 th stage second shift register or between the off-level power supply signal line and the 1 st stage second shift register;

when the first switching element and the third switching element are turned on and the second switching element and the fourth switching element are turned off, the first display region and the second display region are displayed together; when the first switching element and the third switching element are turned off and the second switching element and the fourth switching element are turned on, the first display area or the second display area stops operating.

2. The display panel of claim 1, wherein the display panel further comprises a third display area, the second display area having a third critical pixel row q, the third display area having a fourth critical pixel row q + 1; the x-th stage first shift register and the y-th stage second shift register are connected to the third critical pixel row q; the x +1 th-stage first shift register and the y +1 th-stage second shift register are connected to the fourth critical pixel row q +1, x, y and q are positive integers, x is not equal to i, q is not equal to p, and y is not equal to j;

the fifth switch element is arranged between any adjacent first shift registers from the x-th stage first shift register to the last stage first shift register; the sixth switching element is arranged between the first trigger signal line and the x +1 th stage first shift register; the seventh switching element is arranged between any adjacent second shift registers from the y-th-stage second shift register to the last-stage second shift register; the eighth switching element is disposed between the off-level power supply signal line and the (y + 1) th stage second shift register;

when the fifth switch element and the seventh switch element are turned on and the sixth switch element and the eighth switch element are turned off, the third display area displays; and when the fifth switch element and the seventh switch element are closed and the sixth switch element and the eighth switch element are opened, the third display area stops working.

3. The display panel according to claim 2, wherein the fourth switching element is electrically connected to a1 st stage second shift register;

the first switching element is arranged between any adjacent first shift registers in the 1 st-stage first shift register to the i +1 th-stage first shift register, and the third switching element is arranged between any adjacent second shift registers in the 1 st-stage second shift register to the j +1 th-stage second shift register;

when the first, third, fifth, and seventh switching elements are turned on and the second, fourth, sixth, and eighth switching elements are turned off, the first, second, and third display regions are commonly displayed; when the first, third, fifth, and seventh switching elements are turned off and the second, fourth, sixth, and eighth switching elements are turned on, the first and third display regions simultaneously stop operating.

4. The display panel according to claim 1, wherein the fourth switching element is electrically connected to a1 st stage second shift register;

the display panel further includes a ninth switching element and a tenth switching element, the ninth switching element being disposed between the second trigger signal line and the 1 st stage second shift register; the tenth switching element is provided between the second trigger signal line and the j +1 th stage second shift register.

5. The display panel according to claim 1, wherein the fourth switching element is electrically connected to a j +1 th stage second shift register;

the first switching element is disposed between the i-th stage first shift register and the i + 1-th stage first shift register, and the third switching element is disposed between the j-th stage second shift register and the j + 1-th stage second shift register.

6. The display panel according to claim 1,

under the condition that the fourth switching element is electrically connected with the 1 st-stage second shift register, the first display area is a target display area; under the condition that the fourth switching element is electrically connected with the j +1 th-stage second shift register, the second display area is a target display area;

the display panel further includes:

a plurality of eleventh switching elements disposed between output terminals of the first shift registers corresponding to sub-pixels of even rows in the target display area and input terminals of the first shift registers corresponding to sub-pixels of odd rows in the target display area;

a plurality of twelfth switching elements disposed between the first trigger signal line and the first shift register corresponding to the sub-pixels of the odd-numbered rows in the target display area;

a plurality of thirteenth switching elements disposed between output terminals of the second shift registers corresponding to sub-pixels of even rows in the target display area and input terminals of the second shift registers corresponding to sub-pixels of odd rows in the target display area;

a plurality of fourteenth switching elements disposed between the off-level power supply signal line and the second shift register corresponding to the sub-pixels of the odd-numbered row in the target display area.

7. The display panel according to claim 1, wherein control signal lines for controlling the first switching element and the third switching element to be turned on or off are multiplexed, and/or control signal lines for controlling the second switching element and the fourth switching element to be turned on or off are multiplexed.

8. A driving method applied to the display panel according to any one of claims 1 to 7, the driving method comprising:

when the display panel displays a picture at a first refresh rate higher than a preset refresh rate threshold, controlling the first switch element and the third switch element to be closed, and controlling the second switch element and the fourth switch element to be opened, so that any one of the first display area and the second display area stops working.

9. The method according to claim 8, wherein in the case where the display panel further includes a third display region, the driving method includes:

when the display panel displays a picture at a first refresh rate higher than a preset refresh rate threshold, controlling the first display area and the third display area to stop working at the same time; the first display area and the third display area are respectively positioned on two sides of the second display area.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 7.