CN114333950B

CN114333950B - Storage device

Info

Publication number: CN114333950B
Application number: CN202011065021.3A
Authority: CN
Inventors: 林哲逸
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2025-01-28
Anticipated expiration: 2040-09-30
Also published as: CN114333950A

Abstract

The invention provides a memory device, which comprises a memory cell array and a voltage generating circuit. The voltage generating circuit is electrically connected with the memory cell array and comprises an active voltage circuit and a sensing circuit. The active voltage circuit is used for outputting an operating voltage to the memory cell array when the memory device is in an active mode. The sensing circuit is used for sensing the operating voltage when the memory device is in the standby mode and briefly starting the active voltage circuit to raise the operating voltage after the operating voltage drops below a critical value.

Description

Storage device

Technical Field

The present invention relates to electronic circuits, and more particularly, to a memory device.

Background

With the evolution of electronic technology, nonvolatile memory, which can provide a long-lasting and large-volume data storage function, is becoming a main data storage medium, and flash memory is one of the more dominant storage devices. In order to improve the energy efficiency of the electronic device, the flash memory has a standby mode (standby mode) with low power consumption in addition to an active mode (active mode) when the electronic device is to access data.

However, in order for the flash memory to quickly switch from the standby mode back to the active mode, the voltage generator circuit still needs to operate to provide a high voltage to the word line coupled to the memory array in the standby mode.

In order to save power, the flash memory circuit is generally configured with two voltage generating circuits for an active mode and a standby mode, wherein the voltage generating circuit for the standby mode has lower power consumption. In this way, although the power consumption of the flash memory can be reduced, the additional voltage generating circuit causes an increase in the circuit area of the memory and an increase in the electronic components required to be used.

Disclosure of Invention

In view of the above, the present invention provides a memory device having the advantages of reduced circuit area, simplified circuit components and reduced standby current.

The embodiment of the invention provides a memory device, which comprises a memory array and a voltage generating circuit. The voltage generating circuit is electrically connected with the memory cell array and comprises an active voltage circuit and a sensing circuit. The active voltage circuit is used for outputting an operating voltage to the memory cell array when the memory device is in an active mode. The sensing circuit is used for sensing the operating voltage when the memory device is in the standby mode and briefly starting the active voltage circuit to raise the operating voltage after the operating voltage drops below a critical value.

Based on the above, the memory device according to the embodiment of the invention has a sensing circuit for detecting the change of the operation voltage in the standby mode, and the sensing circuit briefly starts the active voltage circuit to pull up the operation voltage whenever the operation voltage drops below the threshold value. Therefore, the circuit of the memory device can be simplified, and the circuit area can be reduced.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a voltage generation circuit according to an embodiment of the invention;

fig. 3 is a schematic signal waveform diagram of a voltage generating circuit according to an embodiment of the invention.

Detailed Description

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, the memory device 100 may be a NOR flash memory, but the present invention is not limited thereto. The memory device 100 includes at least a memory cell array 102, a controller 104, and a voltage generation circuit 106. The controller 104 is electrically connected to the memory cell array 102 and the voltage generation circuit 106. The controller 104 can control the memory cell array 102 to perform an active mode or a standby mode. The voltage generation circuit 106 correspondingly provides an operating voltage to the word line of the memory cell array 102 according to the active mode or the standby mode. The memory device 100 may further include a word line decoding circuit, a bit line decoding circuit, a driving circuit, a sense amplifying circuit, etc., which are not shown in fig. 1, and those skilled in the art will understand the configuration and implementation of the above components.

Fig. 2 is a circuit diagram of a voltage generation circuit according to an embodiment of the invention. Referring to fig. 2, the circuit structure of fig. 2 can be used to illustrate the voltage generation circuit 106. The voltage generation circuit 106 includes an active voltage circuit 110 and a sensing circuit 120. The active voltage circuit 110 is used for outputting an operating voltage RV to the memory cell array 102 when the memory device 100 is in the active mode. The operating voltage RV is exemplified herein as a read voltage. When the memory device 100 is in the standby mode, the active voltage circuit 110 outputs the operating voltage RV as well, but the difference is that the active voltage circuit 110 is continuously in an enable (enabled) state in the active mode to stabilize the output operating voltage RV, but the active voltage circuit 110 is only intermittently in the enable state in the standby mode, so that power can be saved. In the standby mode, the sensing circuit 120 senses the operating voltage RV and briefly activates the active voltage circuit 110 to pull up the operating voltage RV after the operating voltage RV falls below a threshold.

The active voltage circuit 110 includes a charge pump 112 (charge pump) and a voltage regulator circuit 114 (voltage regulator), and the charge pump 112 is electrically connected to the voltage regulator circuit 114. The charge pump 112 outputs an operating voltage RV, and the voltage regulator 114 is used to maintain the voltage value of the operating voltage RV.

The voltage regulator 114 of fig. 2 includes a high voltage switch HVSW, a transistor T, a voltage divider 116 including a plurality of resistors and at least one transistor, a bandgap reference circuit BGR, and a voltage comparison amplifier 118. The high voltage switch HVSW is coupled between the output terminal of the active voltage circuit 110 and the control terminal of the transistor T. The transistor T and the voltage divider 116 are connected in series between the output terminal of the active voltage circuit 110 and ground (ground). The voltage comparison amplifier 118 receives the output signal of the bandgap reference circuit BGR and the divided voltage of the voltage dividing circuit 116 to output the boost enable signal en_pump. The charge PUMP 112 boosts the operating voltage RV according to the boost enable signal en_pump.

It is noted here that the circuit architecture of the voltage regulating circuit 114 in fig. 2 is merely an example, and the present invention is not limited to the embodiment of the voltage regulating circuit 114.

The sensing circuit 120 includes a capacitor C, a sensing transistor DT, a start transistor AT and a switch transistor ST. One end of the capacitor C is coupled to the output end of the active voltage circuit 110 to receive the operating voltage RV, and the other end is coupled to a sensing node D. One end of the sensing transistor DT receives the reference voltage VDD through the transistor P1, the other end is coupled to the reaction node A, and the control end is coupled to the sensing node D. In other words, the voltage at one end of the capacitor C is the operating voltage RV, and the other end is coupled to the control end of the sensing transistor DT, so that the voltage at the sensing node D varies with the operating voltage RV during the sensing period, and when the operating voltage RV is lower than the threshold value, the sensing transistor is turned on and the sensing period is ended.

One end of the start-up transistor AT receives the reference voltage VDD through the transistor P2, the other end is coupled to the reaction node a, and the control end is coupled to the sensing node D. One end of the switch transistor ST is coupled to the sensing node D, the other end is coupled to the reaction node a, and the control end thereof receives the control signal PG0 together with the control end of the transistor P2. In the present embodiment, the sensing transistor DT, the enabling transistor AT, the switching transistor ST, the transistor P1 and the transistor P2 are PMOS transistors, but not limited thereto.

The sensing circuit 120 enters the start-up period after the sensing period ends. During the start-up period, the switching transistor ST is turned on to correspondingly turn on the start-up transistor AT and turn off (cut off) the sensing transistor DT, and the active voltage circuit 110 is also turned on to pull the operating voltage RV back to the target voltage value.

The sensing circuit 120 further includes a discharge switch 122 and a pull-down circuit 124. One end of the discharging switch 122 is coupled to the reaction node a, and the other end is grounded, wherein the discharging switch 122 is turned on to output leakage current during the start-up period and turned off during the sensing period. One end of the pull-down circuit 124 is coupled to the reaction node a, and the other end is grounded, wherein the pull-down circuit 124 is turned off during the start-up period and turned on during the sensing period to pull down the voltage of the reaction node a.

Specifically, in the present embodiment, the discharge switch 122 includes a transistor NB and a transistor N0. The transistor NB and the transistor N0 are connected in series between the reaction node a and ground, wherein the control terminals of the transistor NB and the transistor N0 respectively receive the control signal NBIAS and the control signal NG0. One skilled in the art will determine the current level of the leakage current by selecting the appropriate transistor NB. The pull-down circuit 124 of the present embodiment is implemented as a single transistor. The control terminal of the pull-down circuit 124 receives the control signal NG1. The transistors NB and N0 and the pull-down circuit 124 are NMOS transistors, but are not limited thereto.

Fig. 3 is a signal waveform diagram of a voltage generating circuit according to an embodiment of the invention. The signal waveform diagram of fig. 3 is applicable to the embodiments of fig. 1 and 2, and the following description refers to fig. 3 with reference to fig. 2.

Between time t1 and time t2 is a sensing period DETECT. At time t1, the operating voltage RV has been boosted to the target voltage value V0 by the charge pump 112. During the sensing period DETECT, the active voltage circuit 110 is not activated, i.e., is in an disabled state, so the operating voltage RV gradually starts to decrease. The sensing circuit 120 monitors the change in the operating voltage RV.

In addition, the switching transistor ST, the start transistor AT, the transistor P2, the discharge switch 122 and the pull-down circuit 124 are in an off state during the sensing period DETECT. The capacitor C couples the operating voltage RV to the sensing node D, so the voltage of the sensing node D varies with the operating voltage RV. The sense transistor DT is in an off state at the beginning (time point t 1). The absolute value of the threshold voltage (threshold voltage) of the sense transistor DT is denoted by Vth 1. At time t2, the voltage of the sensing node D drops below VDD-Vth1, so the sensing transistor DT is turned on, which also indicates that the operating voltage RV is below a threshold.

Between time t2 and time t3, the voltage of the reaction node A is pulled up by the reference voltage VDD through the sensing transistor DT and the transistor P1. The switching transistor ST, the enable transistor AT, the transistor P2, the discharge switch 122 and the pull-down circuit 124 remain in the off state AT this time.

Between time t3 and time t4 is a start-up period ACT. In the start period ACT, the control signal PG0, the control signal NBIAS, and the control signal NG0 are switched to the enable state in response to the voltage rise of the reaction node a, and the switching transistors ST, P2, and the discharge switch 122 are turned on. The pull-down circuit 124 remains in the off state. Since the switching transistor ST is turned on, the reaction node a is common to the sensing node D, and the start-up transistor AT and the sensing transistor DT are connected in the form of diodes (diodes). The absolute value of the threshold voltage of the enable transistor AT is denoted by Vth2. Specifically, the absolute value Vth1 of the threshold voltage of the sensing transistor DT of the present embodiment is larger than the absolute value Vth2 of the threshold voltage of the start-up transistor AT, so the start-up transistor AT is turned on, and the sensing transistor DT is not turned on. The voltages of the reaction node A and the sense node D are maintained AT the start-up voltage VDD-Vth2 by the start-up transistor AT. Meanwhile, the discharge switch 122 allows the reaction node a to output leakage current to the ground.

During the start-up period ACT, the reaction node a outputs the enable signal EN through the inverter INV. The enable signal EN is used to activate the active voltage circuit 110, such as the voltage divider 116, the voltage comparison amplifier 118 and the bandgap reference circuit BGR in the charge pump 112 and the voltage regulator 114. The voltage regulating circuit 114 is activated to perform a voltage stabilizing function. The voltage comparison amplifier 118 outputs a boost enable signal en_pump to cause the charge PUMP 112 to pull back the operating voltage RV to the target voltage value V0. In other words, by enabling the transistor AT, the voltages of the reactive node A and the sensing node D are changed to the enabling voltage VDD-Vth2 to enable the active voltage circuit 110.

In short, the operating voltage RV is attenuated from the target voltage V0, and when the operating voltage RV is lower than the threshold, the active voltage circuit 110 returns the operating voltage RV to the target voltage V0. The ripple (ripple) of the operating voltage RV is determined by the difference Δvth between the threshold voltages of the sensing transistor DT and the enabling transistor AT, where Δvth=vth1-Vth 2. The threshold is V0-DeltaVth.

Between time t4 and time t5, the sensing period DETECT is returned. At the beginning of the sensing period DETECT (time point t 4), the discharge switch 122 is turned off and the pull-down circuit 124 is turned on during the initial period In. Fig. 3 shows an enable period of the control signal NG1 In an initial period In. The initial period In is shorter than the sensing period DETECT. The discharge switch 122 pulls down the voltage of the reaction node a to ground during the initial period In to initialize the voltage of the reaction node a. After the initial period In, the discharge switch 122 is turned off again.

When the operating voltage RV increases to be substantially equal to the target voltage V0 (time t 4), the control signal PG0, the control signal NBIAS and the control signal NG0 are switched back to the disabled state, so that the discharge switch 122 is turned off, and the switching transistors ST, P2 and the discharge switch 122 are also switched to the off state. The above embodiments of the detection period DETECT and the start period ACT are repeated. Whether to re-enter the active voltage circuit 110 during the start-up period ACT is determined by whether the sense transistor DT is turned on or not.

Specifically, the start period ACT is shorter than the sensing period DETECT. In addition, the on time of the sensing transistor DT is also very short, as is shorter than the sensing period DETECT.

In the standby mode, the sensing circuit 120 only briefly activates the active voltage circuit 110, and most of the time the active voltage circuit 110 is not activated, so that the whole device does not consume too much power, and the power saving requirement can be achieved. In addition, the sensing circuit 120 does not need to have a circuit component with high power consumption such as a voltage comparison amplifier or a charge pump, and does not need to have a voltage division circuit composed of a plurality of resistors, so that the standby current is reduced and the circuit area is reduced.

In summary, the embodiments of the present invention provide a memory device. The storage device does not need to configure a low-power voltage generating circuit for the standby mode, but can intermittently start the voltage generating circuit of the active mode through the sensing circuit to achieve the effect of low-power output operation voltage, so that the original voltage generating circuit can be applied to the standby mode. The memory device of the embodiment of the invention has the advantages of reduced circuit area, simplified circuit components and reduced standby current.

Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention, which is accordingly defined in the appended claims.

Claims

1. A storage device, comprising:

a memory cell array; and

A voltage generating circuit is electrically connected to the memory cell array and includes:

an active voltage circuit for outputting an operating voltage to the memory cell array when the memory device is in an active mode; and

A sensing circuit is used to sense the operating voltage when the storage device is in a standby mode and to briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a critical value, wherein the sensing circuit comprises:

a capacitor having one end coupled to the output end of the active voltage circuit and the other end coupled to the sensing node; and

A sensing transistor, one end of which is used to receive a reference voltage, the other end of which is coupled to a reaction node, and a control end of which is coupled to the sensing node.

In the sensing period, the voltage on the sensing node varies with the operating voltage, and when the operating voltage is lower than the critical value, the sensing transistor is turned on.

2. The memory device according to claim 1, wherein the sensing circuit comprises:

A start-up transistor, one end of which is used to receive the reference voltage, the other end of which is coupled to the reaction node, and the control end of which is coupled to the sensing node;

A switch transistor, one end of which is coupled to the sensing node, and the other end of which is coupled to the reaction node,

In the startup period, the switch transistor is turned on to correspondingly turn on the startup transistor and turn off the sensing transistor, and the active voltage circuit is activated to pull the operating voltage back to the target voltage value.

3 . The memory device according to claim 2 , wherein an absolute value of a threshold voltage of the sensing transistor is greater than an absolute value of a threshold voltage of the start-up transistor.

4. The memory device according to claim 2, wherein during the startup period, the voltages of the reaction node and the sensing node are changed to a startup voltage through the startup transistor to start the active voltage circuit, and during the sensing period, the active voltage circuit is not started.

5. The memory device according to claim 2, wherein the sensing circuit further comprises:

a discharge switch having one end coupled to the reaction node and the other end grounded, wherein the discharge switch is turned on during the startup period to output the leakage current and is turned off during the sensing period; and

A pull-down circuit has one end coupled to the reaction node and the other end grounded, wherein the pull-down circuit is disconnected during the startup period and turned on during the sensing period to pull down the voltage of the reaction node.

6 . The memory device according to claim 5 , wherein at the beginning of the sensing period, the discharge switch is turned off and the pull-down circuit is turned on during an initial period, wherein the initial period is shorter than the sensing period.

The memory device according to claim 2 , wherein the activation period is shorter than the sensing period.

8 . The memory device according to claim 2 , wherein when the memory device is in the standby mode, a ripple size of the operating voltage is determined by a difference between a threshold voltage of the sensing transistor and a threshold voltage of the start-up transistor.

9 . The memory device according to claim 8 , wherein the critical value is the target voltage value minus the difference value.