CN114360423A - Display panel and display device - Google Patents
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Abstract
The embodiment of the invention discloses a display panel and a display device, wherein the display panel comprises: a plurality of scanning signal lines and a first gate driving circuit; the first gate driving circuit comprises a plurality of cascaded first shift register units, a plurality of first scanning source lines and a plurality of multi-path selection units, wherein the first scan source lines are distributed along the column direction, the output end of the first shift register unit at one stage is electrically connected with one first scanning source line, one first scanning source line is correspondingly and electrically connected with N scanning signal lines through one multi-path selection unit, N is greater than or equal to 2, and the first scanning source line is used for providing scanning signals. The embodiment of the invention can solve the problem of large frame size in the existing display panel and realize a narrow frame.
Description
Technical Field
The present invention relates to display technologies, and in particular, to a display panel and a display device.
Background
In the 3D display panel, the pixel array includes gate scan lines and data lines that are staggered horizontally and vertically. In order to realize progressive scanning of a pixel array, a shift register circuit is generally used to drive pixel units in the pixel array. With the rapid development of display technologies, the requirements of users on the narrow frame of the display panel and the resolution of the display panel are higher and higher.
The prior art can not effectively reduce the size of a frame for the design of a 3D display panel.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for solving the problem that the size of a frame in the conventional display panel is large.
An embodiment of the present invention provides a display panel, including:
a plurality of scanning signal lines and a first gate driving circuit;
the first gate driving circuit comprises a plurality of cascaded stages of first shift register units, a plurality of first scanning source lines and a plurality of multi-path selection units, wherein the plurality of first scanning source lines are distributed along the column direction, the output end of one stage of first shift register unit is electrically connected with one first scanning source line, one first scanning source line is correspondingly and electrically connected with N rows of scanning signal lines through one multi-path selection unit, N is greater than or equal to 2, and the first scanning source line is used for providing scanning signals.
The embodiment of the invention also provides a display device which comprises the display panel.
In the embodiment of the invention, the first gate driving circuit is formed by cascading a plurality of stages of first shift register units, the output ends of the plurality of stages of first shift register units are electrically connected with a plurality of first scanning source lines which are arranged along the column direction in a one-to-one correspondence manner, the plurality of first scanning source lines are electrically connected with a plurality of multi-path selecting units in a one-to-one correspondence manner, so that scanning signals output by each stage of first shift register unit are provided to the multi-path selecting units through the first scanning source lines, each multi-path selecting unit is also electrically connected with N rows of scanning signal lines in a corresponding manner, N is greater than or equal to 2, so that the scanning signals provided by the first scanning source lines are respectively output to the N rows of scanning lines through the multi-path selecting units to provide scanning signals for the N rows of scanning lines in a time sharing manner, for example, the scanning signals are provided row by row, so that one first shift register unit can correspond to the N rows of scanning lines through one multi-path selecting unit, the total number of the first shift register units is reduced, narrow frame of the display panel is facilitated, and influence on display quality is avoided.
Drawings
To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.
Fig. 1 is a schematic structural diagram of a display panel provided in the related art;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 8 is a timing diagram of a first gate driving circuit according to an embodiment of the invention;
fig. 9 is a timing diagram of another first gate driving circuit according to an embodiment of the invention;
fig. 10 is a timing diagram of a first gate driving circuit according to another embodiment of the invention;
fig. 11 is a timing diagram of a first gate driving circuit according to another embodiment of the present invention;
FIG. 12 is a schematic view of a display panel according to an embodiment of the present invention;
fig. 13 is a timing diagram of a first gate driving circuit according to another embodiment of the invention;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the basic idea disclosed and suggested by the embodiments of the present invention, are within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel provided in the related art, and as shown in fig. 1, a display panel 100 'includes a display area AA' and a non-display area NA ', wherein the display area AA' includes a plurality of pixel units 30 'defined by a plurality of scanning signal lines 10' and a plurality of data signal lines 20 'crossing each other, and the plurality of pixel units 30' are arranged in a plurality of rows and columns in an array. The pixel cells 30 'may be red (R), green (G) or blue (B) pixels, and a plurality of adjacent pixel cells 30' constitute one display pixel, for example, one display pixel may include R, G and B three pixel cells. The non-display area NA ' includes a gate driving circuit 40 ', the gate driving circuit 40 ' includes a plurality of cascade-connected shift register units 41 ', and a signal output terminal of each shift register unit 41 ' is electrically connected to each scanning signal line 10 ' in a one-to-one correspondence, so as to provide a scanning signal to each scanning signal line 10 ' in a one-to-one correspondence.
Generally, the image displayed on the display panel 100 ' is composed of multiple frames of display frames, each frame of display frame includes a scan period, in which the scan signal output by each shift register unit 41 ' is sequentially scanned line by line, and then the data signal is output through each data signal line 20 ' to charge a row of pixel units 30 ' connected to the scan signal line 10 ' being scanned. Since each scanning signal line 10 ' is electrically connected to a corresponding shift register unit 41 ', the frame size of the non-display area NA ' in the display panel 100 is large, which is not favorable for the narrow frame design of the display panel, and in addition, as the resolution of the display panel 100 ' is improved, the risk of insufficient charging of the pixel unit 30 ' is easily generated.
Based on the above technical problem, an embodiment of the present invention provides a display panel, including: a plurality of scanning signal lines and a first gate driving circuit; the first gate driving circuit comprises a plurality of cascaded first shift register units, a plurality of first scanning source lines and a plurality of multi-path selection units, wherein the first scan source lines are distributed along the column direction, the output end of the first shift register unit at one stage is electrically connected with one first scanning source line, one first scanning source line is correspondingly and electrically connected with N scanning signal lines through one multi-path selection unit, N is greater than or equal to 2, and the first scanning source line is used for providing scanning signals.
By adopting the technical scheme, the first grid driving circuit is formed by cascading a plurality of stages of first shift register units, the output ends of the plurality of stages of first shift register units are electrically connected with a plurality of first scanning source lines which are distributed along the column direction in a one-to-one corresponding manner, the plurality of first scanning source lines are electrically connected with a plurality of multi-path selection units in a one-to-one corresponding manner, so that scanning signals output by each stage of first shift register unit are provided to the multi-path selection units through the first scanning source lines, each multi-path selection unit is also electrically connected with N rows of scanning signal lines correspondingly, N is more than or equal to 2, so that the scanning signals provided by the first scanning source lines are respectively output to the N rows of scanning lines through the multi-path selection units to provide scanning signals for the N rows of scanning lines in a time-sharing manner, for example, the scanning signals are provided row by row, thus, one first shift register unit can correspond to the N rows of scanning lines through one multi-path selection unit, the total number of the first shift register units is reduced, narrow frame of the display panel is facilitated, and influence on display quality is avoided.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 2, the display panel 100 includes a plurality of rows of scanning signal lines 10 and a first gate driving circuit 40; the first gate driving circuit 40 includes cascaded multiple stages of first shift register units 41, multiple first scan source lines CKV arranged along the column direction, and multiple multi-path selection units 42, an output end of the first shift register unit 41 at a stage is electrically connected to one first scan source line CKV, one first scan source line CKV is correspondingly electrically connected to N rows of scan signal lines 10 through one multi-path selection unit 42, N is greater than or equal to 2, and the first scan source line CKV is used for providing scan signals.
It can be understood that the display panel 100 is defined by a plurality of scanning signal lines 10 and a plurality of data signal lines 20 crossing each other to form a plurality of sub-pixels 30, the plurality of sub-pixels 30 are arranged in a plurality of rows and a plurality of columns in an array, one row of scanning signal lines 10 is electrically connected to one row of sub-pixels 30, and one column of data signal lines 20 is electrically connected to one column of sub-pixels 30.
The image displayed on the display panel 100 is composed of multiple frames of display frames, each frame of display frame includes a scan period, in one scan period, the signal output by each shift register unit 41 is provided to a multi-path selection unit 42 through a first scan source line CKV, and the multi-path selection unit 42 is electrically connected to N rows of scan signal lines 10, so that the scan signal can be provided to each row of scan signal lines 10 in a time-sharing manner, that is, the multi-path selection unit 42 is electrically connected to N rows of scan signal lines 10. In other words, the scan signals Ckv provided by the first scan source line CKV are the same in one frame of the display screen, and can be provided to the N rows of scan signal lines 10 in a time-sharing manner through the multiplexer 42, and the specific time-sharing manner is not limited in this embodiment, for example, the scan signals can be provided to the N rows of scan signal lines 10 in a time-sharing manner, row by row, or alternatively, the scan signals can be provided to the N rows of scan signal lines 10 in a staggered manner (for example, first open 1, 3, and 5 rows, and then open 2, 4, and 6 rows). Then, each data signal line 20 outputs a data signal S (S1, S2 … … Sm-1, Sm) to charge the subpixels 30 in one row connected to the scanning signal line 10 being scanned, thereby displaying a display screen.
Fig. 3 is a specific structural diagram of a display panel according to an embodiment of the present invention, as shown in fig. 3, fig. 3 exemplarily shows a structural diagram of a display panel with N being 6, such that a scanning signal output by each shift register unit 41 is provided to a multi-path selecting unit 42 through a first scanning source line CKV, the multi-path selecting unit 42 is electrically connected to 6 rows of scanning signal lines 10 to provide a scanning signal for each row of scanning signal line in a time-sharing manner, the color of the sub-pixels 30 in the 6 rows corresponding to the multi-path selecting unit 42 may be arranged in a manner that the colors of the sub-pixels 30 in two adjacent rows are the same, the sub-pixels 30 in the 6 rows are sequentially a red sub-pixel (R), a green sub-pixel (G), a blue sub-pixel (B), and a blue sub-pixel (B), or the sub-pixels 30 in the 6 rows are sequentially rgb, the embodiment of the present invention is not limited to this.
Optionally, fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 4, two opposite first gate driving circuits 40, one first gate driving circuit 40 is disposed at a first end of a row of scanning signal lines 10, and the other first gate driving circuit 40 is disposed at a second end of the same row of scanning signal lines 10; two ends of the same scanning signal line 10 are electrically connected to two first scanning source lines CKV, which are respectively located in the two first gate driving circuits 40 opposite to each other, and are configured to provide the same scanning signal to the same scanning signal line 10.
It can be understood that the same row of the scanning signal line 10 is electrically connected to a plurality of sub-pixels 30, and the scanning signal provided by the scanning signal line 10 simultaneously drives the plurality of sub-pixels 30 to be turned on, so as to charge the plurality of sub-pixels 30 to the data signal line 20.
Fig. 4 exemplarily shows a structural schematic diagram of a display panel with N being 6, two first gate driving circuits 40 are disposed on two sides of a sub-pixel array in the display panel 100, the two first gate driving circuits 40 are symmetrically disposed, and two ends of the same scanning signal line 10 are respectively electrically connected to two first scanning source lines CKV (e.g., CKV1), so that the two first scanning source lines CKV can simultaneously provide scanning signals (e.g., Ckv1) to the same scanning signal line 10, thereby improving the driving capability of the scanning signal line and improving the quality of a display picture.
Optionally, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 5, two opposite first gate driving circuits 40 are provided, one first gate driving circuit 40 is disposed at a first end of a row of scanning signal lines 10, and the other first gate driving circuit 40 is disposed at a second end of the row of scanning signal lines 10; each adjacent N rows of scanning signal lines in the multiple rows of scanning signal lines 10 form a line group; the first gate driving circuit 40 at the first terminal is used for driving the odd line groups, and the first gate driving circuit 40 at the second terminal is used for driving the even line groups.
Specifically, fig. 5 exemplarily shows a structural diagram of the display panel with N being 6, wherein the scan signal lines in the 1 st to 6 th rows form a line group, which can be regarded as a first line group, and the scan signal is provided by the first scan source line CKV1, and similarly, the scan signal lines in the 7 th to 12 th rows form a line group, which can be regarded as a second line group, and the scan signal is provided by the first scan source line CKV 2. By analogy, each adjacent 6 rows of scanning signal lines in the multiple rows of scanning signal lines 10 may form a line group, the odd line group is driven by the first gate driving circuit 40 located at one end of the scanning signal line 10, and the even line group is driven by the first gate driving circuit 40 located at the other end of the scanning signal line 10, so that the line layout is more reasonable, mutual interference is avoided, and a narrow frame of the display panel is facilitated.
For convenience of description, in the embodiments of the present invention, the display panel shown in fig. 5 is taken as an example to exemplarily describe the technical solution of the embodiments of the present invention without special description.
Optionally, fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and as shown in fig. 6, the first gate driving circuit 40 further includes a 1 st to an nth timing control line CKH; the multiplexing unit 42 includes the 1 st to nth control terminals C; an ith control terminal Ci in the multiplexing unit 42 is electrically connected to an ith timing control line CKHi for transmitting a scanning signal to an ith scanning signal line in the N rows of scanning signal lines when turned on, wherein i is greater than or equal to 1 and less than or equal to N.
Specifically, on the basis of the structure shown in fig. 5, fig. 6 exemplarily shows a structural diagram of a display panel with N being 6, each of the multiple selecting units 42 includes the 1 st to 6 th control terminals C (C1, C2 … … C6), wherein the 1 st control terminal C1 is electrically connected to the 1 st timing control line CKH1, the 2 nd control terminal C2 is electrically connected to the 2 nd timing control line CKH2, and so on. Thus, for example, when the timing control signal Ckh2 outputted from the 2 nd timing control line CKH2 controls the corresponding scan signal line in the multiplexer unit 42 to be turned on through the 2 nd control terminal C2, the scan signal Ckv1 provided by the first scan source line CKV1 may be transmitted to the 2 nd scan signal line in the N rows of scan signal lines, so that the plurality of sub-pixels 30 electrically connected to the row of scan signal lines are turned on, and the sub-pixels 30 are charged by the data signal S provided by each data signal line 30. Therefore, the structure of the first gate driving circuit can be effectively simplified under the condition that the display quality of the display panel is not influenced, so that the size of the frame of the display panel is reduced, and the narrow frame of the display panel is realized.
It should be noted that the timing control line CKH controls the conduction of the 1 st to nth control terminals C in the multiplexing unit 42 in a time-sharing manner, so as to avoid that the scanning signals are all transmitted to the N rows of scanning signal lines at the same time to affect the normal display of the display frame.
Optionally, fig. 7 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, and as shown in fig. 7, the multiplexing unit 42 includes 1 st to nth switching devices T; the control end of the ith switching device Ti is the ith control end Ci of the multi-path selection unit 42, the input end is electrically connected to the first scanning source line CKV, and the output end is electrically connected to the ith scanning signal line, and is used for being turned on or off under the control of the ith timing control line CKHi.
Specifically, fig. 7 exemplarily shows a structural diagram of a display panel in which N is 6, a control terminal of a 1 st switching device T1 in the multi-path selection unit 42 is C1, and C1 is electrically connected to a 1 st timing control line CKH1, an input terminal of the 1 st switching device T1 is electrically connected to the first scan source line CKV, and an output terminal of the 1 st switching device T1 is electrically connected to the 1 st scan signal line; similarly, the control terminal of the 2 nd switching device T2 is C2, and C2 is electrically connected to the 2 nd timing control line CKH2, the input terminal of the 2 nd switching device T2 is electrically connected to the first scan source line CKV, the output terminal of the 2 nd switching device T2 is electrically connected to the 2 nd scan signal line, and so on. As such, for example, when the timing control signal Ckh2 outputted from the 2 nd timing control line CKH2 controls the 2 nd switching device T2 to be turned on through the 2 nd control terminal C2, the scan signal Ckv1 provided by the first scan source line CKV1 may transmit the 2 nd scan signal line to enable the plurality of sub-pixels 30 electrically connected to the 2 nd scan signal line to be turned on, so that the data signal S provided by each data signal line 30 starts to charge the sub-pixels 30. Therefore, the structure of the first gate driving circuit 40 can be effectively simplified without affecting the display quality of the display panel, so that the size of the frame of the display panel is reduced, and the narrow frame of the display panel is realized.
Optionally, with continued reference to fig. 7, the switching devices T of the multiplexing unit 42 are both N-type transistors or both P-type transistors.
Specifically, when the switching device T of the multi-path selection unit 42 is an N-type transistor, the timing control signal Ckh for controlling the switching device T to be turned on is all at a high level, and the timing control signal Ckh for controlling the switching device T to be turned off is all at a low level; when the switching device T of the multiplexing unit 42 is a P-type transistor, the timing control signal Ckh for controlling the switching device T to be turned on is at a low level, and the timing control signal Ckh for controlling the switching device T to be turned off is at a high level. In this embodiment, the switching devices T of the multi-path selection unit 42 are all N-type transistors or all P-type transistors, so that the time-limited control lines of the first gate driving circuit can be simplified, the size of the frame of the display panel can be reduced, and the narrow frame of the display panel can be realized.
Optionally, fig. 8 is a timing diagram of a first gate driving circuit according to an embodiment of the present invention, and with reference to fig. 6 and 8, an operation process of any timing control line CKH in the first gate driving circuit 40 includes a first turn-on phase t1(ii) a At the first start-up period t of the ith timing control line CKHi1The multiplexer unit 42 transmits the scanning signalTo the ith scanning signal line.
Specifically, fig. 8 exemplarily shows a timing diagram of the first gate driving circuit with N being 6, and the display panel 100 further includes a first start signal line STV1 and a second start signal line STV2 (both not shown in the figure), and at the beginning of each scan cycle, the first start signal line STV1 outputs the driving signal STV1 and transmits the driving signal STV1 to one first gate driving circuit 40, and the second start signal line STV2 outputs the driving signal STV2 and transmits the driving signal STV 3538 to another first gate driving circuit 40, so that the first shift register unit 41 in the first gate driving circuit 40 starts to operate. When the first scan source line CKV is active (e.g. high), the first scan source line CKV provides the scan signal Ckv for the multiplexer unit 42, and the operation process of any timing control line CKH includes a first start-up phase t1At the first turn-on stage t of the ith timing control line CKHi1When the timing control signal CKHi provided by the ith timing control line CKHi is an active signal (e.g., high level), the corresponding scan signal line is controlled to be turned on by the ith control terminal Ci of the multiplexing unit 42, so that the multiplexing unit 42 transmits the scan signal Ckv to the ith scan signal line, and the data signal S output by each data signal line 30 charges each sub-pixel 30 electrically connected to the ith scan signal line, thereby displaying a corresponding display image.
It should be noted that, at the stage when the first scan source line CKV outputs the valid signal, the timing control line CKH controls the scan signal line to be turned on in a time-sharing manner, and the specific scan timing of the embodiment of the present invention is not particularly limited, and may be, for example, line-by-line scanning or line-crossing scanning.
Illustratively, when the first scan source line CKV1 is an active signal (e.g., high level), the first scan source line CKV1 provides the scan signal Ckv1 to the multiplexing unit 42, and during the first on-phase t1 of the 1 st timing control line CKH1, the timing control signal Ckh1 provided by the 1 st timing control line CKH1 is an active signal (high level), and the multiplexing unit 42 transmits the scan signal Ckv1 to the 1 st scan signal line, so that each data signal line 30 outputs the data signal S to charge each sub-pixel 30 electrically connected to the 1 st scan signal line. Then, the 2 nd timing control line CKH2 enters the first onStarting phase t1And the output timing control signal Ckh2 is an active signal (high level), the multiplexing unit 42 transmits the scan signal Ckv1 to the 2 nd scan signal line, so that each data signal line 30 outputs the data signal S to charge each sub-pixel 30 electrically connected to the 2 nd scan signal line. And so on until the multiplexing unit 42 transmits the scan signal Ckv1 to the 6 th scan signal line and causes each data signal line 30 to output the data signal S to charge each sub-pixel 30 electrically connected to the 6 th scan signal line.
Then, based on the same principle, after the first scan source line CKV1 outputs the valid signal, the first scan source line CKV2 outputs the valid signal (for example, high level), and performs scanning according to a set scanning manner, for example, progressive scanning, and transmits the scan signal Ckv2 output by the first scan source line CKV2 to the 7 th to 12 th scan lines, which is not described herein again in detail.
Optionally, fig. 9 is a timing diagram of another first gate driving circuit according to an embodiment of the invention, and as shown in fig. 9, the operation process of at least one timing control line CKH further includes a first turn-on period t1Preceding pre-opening phase t0(ii) a At the first start-up period t of the ith timing control line CKHi1Before the end, the (i + 1) th timing control line CKHi + 1 enters the pre-start stage t0(ii) a At the first start-up period t of the ith timing control line CKHi1And pre-start phase t of the (i + 1) th timing control line CKHi + 10The multiplexing unit 42 transmits the scanning signals to the ith scanning signal line and the (i + 1) th scanning signal line, respectively.
Specifically, fig. 9 exemplarily shows a timing diagram of the first gate driving circuit with N being 6, when the first scan source line CKV is an active signal (e.g. high level), the first scan source line CKV provides the scan signal Ckv for the multi-path selecting unit 42, and at this time, the operation process of at least one timing control line CKH further includes during the first turn-on period t1Preceding pre-opening phase t0At the first turn-on stage t of the ith timing control line CKHi1Before the end, the (i + 1) th timing control line CKHi + 1 enters the pre-start stage t0. In other words, the ith timing controlLine CKHi is in the first turn-on phase t1When an active signal (e.g., high level) is outputted to control the ith control terminal Ci of the multiplexer unit 42 to be turned on, the ith +1 th timing control line CKHi + 1 enters the pre-start-up stage t0And outputs an active signal (e.g., a high level) to control the i +1 th control terminal Ci +1 of the multiplexing unit 42 to be turned on, so that the scan signal Ckv provided from the first scan source line CKV is transmitted to the i-th scan signal line and the i + 1-th scan signal line, respectively, through the multiplexing unit 42. In this way, when the scan signal Ckv provided by the first scan source line CKV is transmitted to the scan signal line of the current row, the sub-pixels 30 of the current row are driven to be turned on, so that the data signal line 20 provides the data signal S to charge the sub-pixels 30 on the row; meanwhile, before the scanning is finished, the same scanning signal Ckv is provided to the scanning signal line of the next row, so that the charging time of the sub-pixels 30 of the next row is prolonged, the charge quantity of the storage capacitors in the sub-pixels 30 is increased, the stability of the display picture is ensured, and the display quality is improved.
Illustratively, when the first scan source line CKV1 is active (e.g., high), the first scan source line CKV1 provides the scan signal Ckv1 to the multiplexer unit 42 during the first turn-on period t of the 1 st timing control line CKH11The timing control signal Ckh1 provided by the 1 st timing control line CKH1 is an active signal (high level), and the multiplexing unit 42 transmits the scan signal Ckv1 to the 1 st scan signal line, so that each data signal line 30 outputs the data signal S to charge each sub-pixel 30 electrically connected to the 1 st scan signal line. Before the end of the first row scan, the 2 nd timing control line CKH2 enters the pre-start phase t0And the output timing control signal Ckh2 is an active signal (high level), at this time, the multiplexing unit 42 transmits the scan signal Ckv1 to the 2 nd scan signal line, so that each data signal line 30 outputs the data signal S to charge each sub-pixel 30 electrically connected to the 2 nd scan signal line. It is apparent that the charging time period of each sub-pixel 30 electrically connected to the 2 nd scanning signal line is equal to the total time period of the first turn-on period plus the pre-turn-on period, extending the charging time of the plurality of sub-pixels 30 electrically connected to the 2 nd scanning signal line.
Alternatively, with continued reference to FIG. 9, of the ith timing control lineFirst opening phase t1Is earlier than or equal to the pre-start period t of the (i + 1) th timing control line0The starting time of (c).
Specifically, the first start-up stage t of the ith timing control line1May be earlier than the pre-start period t of the (i + 1) th timing control line1In other words, the first turn-on period t of the ith timing control line1Is in the pre-start stage t of the (i + 1) th timing control line0Before the start time of (c). Referring to FIG. 9, at this time, the pre-start period t of the (i + 1) th timing control line0First start-up period t of ith timing control line1The overlapping of the partial time periods can also meet the requirement of prolonging the charging time of the sub-pixels 30 in the row where the scanning signal line controlled by the (i + 1) th time sequence control line is positioned, thereby improving the stability of the display picture.
In addition, in another embodiment, the first turn-on period t of the ith timing control line1And the pre-start stage t of the (i + 1) th timing control line0The starting time of (2) is the same, as shown in fig. 10. At this time, the pre-start stage t of the (i + 1) th timing control line0First start-up period t of ith timing control line1The overlap is complete, and compared with fig. 9, the charging time of the sub-pixels 30 in the row where the scanning signal line controlled by the (i + 1) th timing control line is located can be further prolonged, thereby improving the stability of the display screen.
Optionally, with continued reference to fig. 9 or 10, one or more of the 2 nd to nth timing control lines CKH2 and CKH include a pre-turn-on stage t0。
For example, when N is 6, only one timing control line CKH (e.g., CKH4) of the 2 nd to 6 th timing control lines CKH2 to CKH6 or a plurality of timing control lines CKH (e.g., a plurality of timing control lines CKH2, CKH4 and CKH6) may include a pre-turn-on stage t0The embodiment of the present invention does not specifically limit this, and may be selectively set according to actual conditions. Thus, it includes a pre-opening stage t0The timing control line CKH, especially the charging time of the sub-pixels 30 in the row of the turned-on scanning signal line, can be controlled by the pre-start-up staget0The display screen is prolonged, and the stability of the display screen is improved.
Preferably, the 2 nd to 6 th timing control lines CKH2 to CKH6 may each include a pre-start phase t0Therefore, the picture stability of the whole display panel in one scanning period is ensured, and the display quality of the display panel is improved.
Alternatively, as shown in fig. 6, 9 and 10, a plurality of columns of data signal lines 20 and a plurality of rows of sub-pixels 30, a row of scanning signal lines 10 is electrically connected to a row of sub-pixels 30, and a column of data signal lines 20 is electrically connected to a column of sub-pixels 30; n rows of sub-pixels 30 are driven by N rows of scanning signal lines 10 corresponding to one first scanning source line CKV; the operation of a row of sub-pixels 30 comprises a charging phase t2(ii) a Charging phase t of i-th row of sub-pixels 30 in N rows of sub-pixels 302The ith timing control line CKHi enters the first start-up stage t1The first scan source line CKV provides an effective scan signal to the ith scan signal line 10, and the data signal line 20 provides a corresponding ith row of data signals to the ith row of sub-pixels 30.
It is understood that a plurality of scan signal lines 10 and a plurality of data signal lines 20 intersect to define a plurality of pixels 30, and the plurality of sub-pixels 30 are arranged in a plurality of rows and columns in an array. N rows of scanning signal lines are correspondingly connected to one first scanning source line CKV through one multiplexing unit 42, so that the scanning signal Ckv of the first scanning source line CKV is transmitted to the N rows of scanning signal lines 10 in a time-sharing manner through the multiplexing unit 42 to drive the N rows of sub-pixels 30.
Specifically, as shown with reference to FIG. 9 or FIG. 10,
for example, the charging period t is defined as the active signal (high level) period of the timing control signal Ckh1 provided by the 1 st timing control line CKH12At this time, the 1 st timing control line CKH1 enters the first turn-on stage t1The first scan source line CKV provides an active scan signal (high level) to the 1 st scan signal line 10 to drive the sub-pixels 30 electrically connected to the 1 st scan signal line to be turned on, and the data signal line 20 outputs the corresponding 1 st row data signal S (S1, S2 … … Sm) and transmits the data signals to the sub-pixels 30 in the 1 st row for charging.
Optionally, as shown in fig. 6, 9 and 10, the charging phase t of the ith row of sub-pixels in the N rows of sub-pixels2If the ith timing control line enters the pre-start stage t of the (i + 1) th timing control line0The first scan source line CKV further provides an effective scan signal to the (i + 1) th scan signal line, and the data signal line 20 further provides the (i + 1) th row of data signals to the sub-pixels of the (i + 1) th row.
Specifically, the operation process of at least one timing control line CKH further includes a first start-up period t1Preceding pre-opening phase t0The ith timing control line CKHi is in the first start-up stage t1When an active signal (e.g., high level) is outputted to control the ith control terminal Ci of the multiplexer unit 42 to be turned on, the ith +1 th timing control line CKHi + 1 enters the pre-start-up stage t0And outputs an active signal (e.g., a high level) to control the i +1 th control terminal Ci +1 of the multiplexing unit 42 to be turned on, so that the scan signal Ckv provided from the first scan source line CKV is transmitted to the i-th scan signal line and the i + 1-th scan signal line, respectively, through the multiplexing unit 42. At this time, since the data signal output from the data signal line 20 is a data signal corresponding to the i-th row of sub-pixels, the data signal is pre-turned on at the i-th timing control line and the i + 1-th timing control line in the pre-turn-on period t0In the overlapping time period, the ith row data signal output by the data signal line 20 is also provided to the (i + 1) th row sub-pixels, so as to charge the (i + 1) th row sub-pixels. Thus, the i +1 th timing control line includes a pre-start stage t0And in the pre-start-up period t0The first scanning source line CKV also provides an effective scanning signal for the (i + 1) th scanning signal line, so that the data signal line 20 also provides the (i) th row of data signals for the (i + 1) th row of sub-pixels, the charging time of the (i + 1) th row of sub-pixels is prolonged, the charge quantity of the storage capacitor in the sub-pixel 30 is increased, the stability of a display picture is ensured, and the display quality is improved.
It should be noted that the ith row data signal and the (i + 1) th row data signal may be the same or different, and are specifically related to the color of the sub-pixel 30 and the picture to be presented, and the embodiment of the present invention is not limited herein.
Illustratively, referring to fig. 9, the input is at the first scan source line CKV1When the active scan signal is asserted (Ckv 1 is high), the active signal (high) period of the timing control signal Ckh1 provided by the 1 st timing control line CKH1 is the charging period t2At this time, the 1 st timing control line CKH1 enters the first turn-on stage t1The first scan source line CKV1 provides an active scan signal (high level) to drive the sub-pixels 30 electrically connected to the 1 st scan signal line to turn on, and the data signal line 20 outputs the corresponding 1 st row data signal S, and transmits the data signal S to the 1 st row sub-pixels 30 respectively to charge the sub-pixels. When the 1 st time sequence control line enters and the 2 nd time sequence control line pre-start period t0The first scan source line CKV1 also provides an active scan signal (high level) to the 2 nd scan signal line, and the data signal line 20 also provides the 1 st row data signal S to the 2 nd row sub-pixels, and transmits them to the 2 nd row sub-pixels 30 respectively to charge them.
Optionally, fig. 11 is a timing diagram of another first gate driving circuit according to an embodiment of the invention, and as shown in fig. 11, the 2 i-th timing control line CKH2i includes a precharge stage t3And the 2i-1 th timing control line CKH2i-1 does not include the precharge phase t3I is less than or equal to N/2.
Specifically, fig. 11 exemplarily shows a timing diagram of the first gate driving circuit where N is 6, and the even number timing control lines CKH2i include a precharge phase t3Charging phase t3Comprising a pre-opening phase t0The odd number of timing control lines CKH2i-1 do not include the precharge phase t3. In a stage where the first scan source line CKV outputs the active scan signal, a 2i-1 th timing control line CKH2i-1 among the odd number of timing control lines CKH is in a first turn-on stage t1When an active signal (e.g., high level) is outputted to control the 2i-1 control terminal C2i-1 of the multi-way selection unit 42 to be turned on, the even-numbered timing control line CKH2i of the 2i-1 timing control line CKH2i-1 has entered the pre-start stage t0And outputs an active signal (e.g., a high level) to control the 2i control terminal C2i of the multiplexing unit 42 to be turned on, so that the scan signal Ckv provided by the first scan source line CKV is transmitted to the 2i-1 th scan signal line and the 2i scan signal line through the multiplexing unit 42, respectively. Then, the number of data signal line 20 outputsThe signals are transmitted to the sub-pixels in the 2i-1 th row and the sub-pixels in the 2i-1 th row, the sub-pixels in the 2i-1 th row are normally charged to present a corresponding display picture, and meanwhile, the sub-pixels in the 2i-1 th row are pre-charged to prolong the charging time of the sub-pixels in the 2i-1 th row and improve the stability of the display picture and the display quality of the display panel.
It should be noted that, the first turn-on period t of the 2i-1 th timing control line CKH2i-1 and the 2 i-2 th timing control line CKH2i, and the 2i-1 th timing control line CKH2i-1 are adjacent to each other1Is earlier than or the same as the pre-start period t of the 2 i-th timing control line CKH2i-10The start time of the present invention is not particularly limited in this respect. Preferably, referring to FIG. 11, the first turn-on phase t of the 2i-1 th timing control line CKH2i-11And the pre-start period t of the 2 i-th timing control line CKH2i0The starting time of the first row sub-pixels is the same time, so that the sub-pixels in the 2i-1 th row on the 2i scanning line controlled to be conducted by the 2i timing control line CKH2i can be ensured to have sufficient charging time, the stability of a display picture can be ensured, and the display quality is improved.
In this embodiment, the even number of timing control lines CKH2i are set to include a precharge phase t3The odd number of timing control lines CKH2i-1 do not include the precharge phase t3Therefore, the abnormal phenomenon of the display picture caused by the larger difference between the 2 i-th row data signal and the next row data signal can be avoided.
Optionally, with continued reference to fig. 9 and 11, the first turn-on phase t of the 2 i-th timing control line1Is earlier than the pre-start period t of the 2i +2 th timing control line0The starting time of (c).
Specifically, the first start-up period t of the 2 i-th timing control line1Pre-start stage t of 2i +2 time sequence control line0With a certain time interval, Gap, to prevent the first turn-on period t of the 2 i-th timing control line1The 2i +2 th time sequence control line enters the pre-starting stage t0. If the charging time of the two is overlapped, the 2i row data signal output by the data signal line charges the 2i row sub-pixel 30 and also charges the 2i +2 row sub-pixel 30Charging, which will cause the display to be abnormal. Especially, the sub-pixels in the 2i th row are not adjacent to the sub-pixels in the 2i +2 th row, when the difference between the data signal in the 2i th row and the data signal in the 2i +2 th row is large, the display of the display panel is seriously affected, and the display quality is reduced.
Alternatively, as shown in fig. 6 and fig. 11, a plurality of columns of data signal lines 20 and a plurality of rows of sub-pixels 30, a row of scanning signal lines 10 electrically connected to a row of sub-pixels 30, and a column of data signal lines 20 electrically connected to a column of sub-pixels 30; n rows of sub-pixels 30 are driven by N rows of scanning signal lines 10 corresponding to one first scanning source line CKV; the operation of a row of sub-pixels 30 comprises a charging phase t 2; charging phase t of i-th row of sub-pixels in N rows of sub-pixels 302The ith timing control line enters the first start-up stage t1The first scan source line CKV provides an effective scan signal to the ith scan signal line 10, and the data signal line 20 provides a corresponding ith row of data signals to the ith row of sub-pixels.
Optionally, with continued reference to FIG. 11, during the charging phase of the sub-pixels in the 2i-1 th row of the N rows of sub-pixels, if the 2i-1 st timing control line CKH2i-1 enters the pre-start phase t of the 2i timing control line CKH2i1The first scan source line CKV also provides an effective scan signal to the 2 i-th scan signal line, and the data signal line 20 also provides the 2i-1 th row of data signals to the 2 i-th row of sub-pixels.
Specifically, the 2i-1 th timing control line CKH2i-1 is in the first turn-on period t1When the valid signal (e.g., high level) is outputted to control the conduction of the 2i-1 control terminal C2i-1 of the multi-way selection unit 42, the 2 i-th timing control line CKH2i has entered the pre-start-up period t0And outputs an active signal (e.g., a high level) to control the 2i control terminal C2i of the multiplexing unit 42 to be turned on, so that the scan signal Ckv provided by the first scan source line CKV is transmitted to the 2i-1 th scan signal line and the 2i scan signal line through the multiplexing unit 42, respectively. At this time, the data signal outputted from the data signal line 20 is a data signal corresponding to the 2i-1 th scanning signal line, and therefore, the pre-start period t is set in the 2i-1 st timing control line and the 2 i-th timing control line0Coincidence period, which is output from the data signal line 20 and corresponds to the 2i-1 th scanning signal lineThe data signal is also provided to the sub-pixels of the 2i th row, and the sub-pixels of the 2i th row are charged.
Thus, since the 2 i-th timing control line includes the pre-turn-on period t0And in the pre-start-up period t0The first scanning source line CKV also provides an effective scanning signal for the 2 i-th scanning signal line, so that the data signal line 20 also provides a 2i-1 th row of data signals for the 2 i-th row of sub-pixels, the charging time of the 2 i-th row of sub-pixels is prolonged, the charge amount of the storage capacitor in the sub-pixel 30 is increased, the stability of a display picture is ensured, and the display quality is improved.
Optionally, fig. 12 is a schematic structural diagram of another display panel provided in this embodiment, as shown in fig. 12, in the N rows of sub-pixels 30, the 2j-1 th row of sub-pixels and the 2j row of sub-pixels have the same color, and j is greater than or equal to 1 and less than or equal to N/2.
It can be understood that the 3D display panel is generally used for displaying 3D stereoscopic effects, and the stereoscopic vision is generated by separating display frames of the display panel viewed by left and right eyes of a person and observing a difference in angles of an object with both eyes of the person. Therefore, when the sub-pixels in the 3D event panel are arranged, the pixels in two adjacent rows are the same pixels for the left and right eyes, and in actual use, the difference in the display screen of the display panel seen by the left and right eyes is small, that is, the difference in the potential of the sub-pixels in two adjacent rows is small. Therefore, the voltage value difference of the data signals for charging the adjacent sub-pixels is relatively large, so that the stability of a display picture is ensured, and the display quality of the display panel is improved.
Specifically, in the N rows of sub-pixels 30, the 2j-1 th row of sub-pixels and the 2j row of sub-pixels have the same color, so that the odd rows of sub-pixels can be used for presenting the picture seen by the left eye of a person, and the even rows of sub-pixels can be used for presenting the picture seen by the right eye of the person, so that the 3D display panel presents a stereoscopic visual picture.
It should be noted that the arrangement of the subpixels 30 in the N rows is AABBCC, wherein specific colors of the subpixels 30 represented by A, B and C are not particularly limited in the embodiment of the present invention, and can be selectively set according to practical applications. For example ABC, is RGB in sequence.
Optionally, N ═ 6; for the N rows of sub-pixels, the N rows of sub-pixels comprise two adjacent rows of red sub-pixels (R), two adjacent rows of green sub-pixels (G) and two adjacent rows of blue sub-pixels (B).
Specifically, fig. 12 exemplarily shows a structural diagram of a display panel with N being 6, in each 6 rows of sub-pixels 30, the sub-pixels in the 2j-1 th row and the sub-pixels in the 2j th row have the same color, and j is greater than or equal to 1 and less than or equal to N/2. For example, the arrangement order of the sub-pixels 30 in the 6 rows is RRGGBB, which is not particularly limited in this embodiment of the present invention, and other arrangement manners may also be used. Thus, the 1 st, 3 rd and 5 th row sub-pixels may constitute one display pixel corresponding to presentation of a display screen to the left eye of a person; the sub-pixel of the 2 nd row, the sub-pixel of the 4 th row and the sub-pixel of the 6 th row can form another display pixel corresponding to the display picture of the right eye of a person, so that the 3D display panel can display a stereoscopic visual picture.
For example, fig. 13 is a timing diagram of another first gate driving circuit according to an embodiment of the invention, and in a period when the first scan source line CKV1 outputs an active scan signal (i.e. Ckv1 is a high level period), the 1 st timing control line CKH1 enters a first turn-on period t shown in fig. 12 and 131(i.e. charging phase t)2) The first scan source line CKV1 provides an active scan signal (high level) to drive the sub-pixels 30 electrically connected to the 1 st scan signal line to be turned on, and the data signal line 20 outputs the corresponding 1 st row data signal S of 4.6V, and transmits the data signal S to the 1 st row sub-pixels 30 respectively to charge the sub-pixels. When the 1 st time sequence control line enters and the 2 nd time sequence control line pre-start period t0Overlap period of (i.e. precharge phase t)3) The first scan source line CKV1 also provides an active scan signal (high level) to the 2 nd scan signal line, and the 1 st row data signal S (4.6V) output from the data signal line 20 also charges the 2 nd row sub-pixels 30. When the 1 st time sequence control line is in the first start stage t1After the end, the 2 nd time sequence control line enters the first opening stage t1(i.e. charging phase t)2) At this time, the first scan source line CKV1 provides an active scan signal (high level) to drive the sub-pixels 30 of the 2 nd row to be continuously turned onThe data signal line 20 outputs the row 2 data signal S of 3.5V, which is transmitted to the row 2 sub-pixels 30 to charge the same.
Because the difference between the voltage value of the data signal S in row 1 and the voltage value of the data signal S in row 2 is small, the potential of the sub-pixel 30 in row 2 can be quickly restored to the correct potential (3.5V), and compared with the case that the potential of the sub-pixel 30 in row 2 is directly from 0V to 3.5V, the transient time for stabilizing the potential of the sub-pixel is saved, and the storage amount of charges in the sub-pixel is increased, thereby improving the stability of the display picture.
Based on the same inventive concept, the embodiment of the invention also provides a structural schematic diagram of a display device, and the display device comprises the display panel. Exemplarily, fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 14, the display device 200 includes the display panel 100.
The display device 200 provided by the embodiment of the invention can be any electronic product with a display function, including but not limited to the following categories: the present disclosure relates to a mobile phone, a television, a notebook computer, a desktop display, a tablet computer, and the like.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (19)
1. A display panel, comprising:
a plurality of scanning signal lines and a first gate driving circuit;
the first gate driving circuit comprises a plurality of cascaded stages of first shift register units, a plurality of first scanning source lines and a plurality of multi-path selection units, wherein the plurality of first scanning source lines are distributed along the column direction, the output end of one stage of first shift register unit is electrically connected with one first scanning source line, one first scanning source line is correspondingly and electrically connected with N rows of scanning signal lines through one multi-path selection unit, N is greater than or equal to 2, and the first scanning source line is used for providing scanning signals.
2. The display panel according to claim 1, comprising: two opposite first gate driving circuits, one of the first gate driving circuits is arranged at the first end of one row of the scanning signal lines, and the other first gate driving circuit is arranged at the second end of the same row of the scanning signal lines;
two ends of the same scanning signal line are respectively and electrically connected with two first scanning source lines, and the two first scanning source lines are respectively positioned in the two first gate driving circuits which are opposite to each other and used for providing the same scanning signal for the same scanning signal line.
3. The display panel according to claim 1, comprising: two opposite first gate driving circuits, one of the first gate driving circuits is arranged at a first end of one row of the scanning signal lines, and the other of the first gate driving circuits is arranged at a second end of one row of the scanning signal lines;
every adjacent N rows of scanning signal lines in a plurality of rows of scanning signal lines form a line group;
the first gate driving circuit at the first end is used for driving odd line groups, and the first gate driving circuit at the second end is used for driving even line groups.
4. The display panel according to claim 1, wherein the first gate driver circuit further includes 1 st to nth timing control lines; the multi-path selection unit comprises 1 st to Nth control ends;
and an ith control end in the multi-path selection unit is electrically connected with an ith timing control line and used for transmitting the scanning signals to an ith scanning signal line in the N rows of scanning signal lines when the multi-path selection unit is switched on, wherein i is greater than or equal to 1 and less than or equal to N.
5. The display panel according to claim 4, wherein the multiplexing unit includes 1 st to nth switching devices;
the control end of the ith switching device is the ith control end of the multi-path selection unit, the input end of the ith switching device is electrically connected with the first scanning source line, and the output end of the ith switching device is electrically connected with the ith scanning signal line and is used for being switched on or switched off under the control of the ith timing control line.
6. The display panel according to claim 5, wherein the switching devices of the multiplexing unit are all N-type transistors or all P-type transistors.
7. The display panel according to claim 4, wherein the operation of any one of the timing control lines in the first gate driving circuit comprises a first turn-on phase;
in a first turn-on stage of the ith timing control line, the multiplexing unit transmits the scan signal to the ith scan signal line.
8. The display panel according to claim 7, wherein the operation of at least one of the timing control lines further comprises a pre-turn-on phase prior to the first turn-on phase;
before the first starting stage of the ith timing control line is finished, the (i + 1) th timing control line enters a pre-starting stage;
and in the coincidence time period of the first starting stage of the ith timing control line and the pre-starting stage of the (i + 1) th timing control line, the multi-path selection unit transmits the scanning signals to the ith scanning signal line and the (i + 1) th scanning signal line respectively.
9. The display panel according to claim 8, wherein the start time of the first turn-on phase of the ith timing control line is earlier than or equal to the start time of the pre-turn-on phase of the (i + 1) th timing control line.
10. The display panel according to claim 8, wherein one or more of the 2 nd to nth timing control lines comprise a pre-turn-on stage.
11. The display panel according to claim 10, further comprising: the scanning signal line is electrically connected with the sub-pixels in one row, and the data signal line is electrically connected with the sub-pixels in one column;
the N rows of scanning signal lines corresponding to one first scanning source line drive N rows of sub-pixels;
the working process of a row of sub-pixels comprises a charging phase;
in a charging stage of the ith row of sub-pixels in the N rows of sub-pixels, the ith timing control line enters a first starting stage, the first scanning source line provides an effective scanning signal for the ith scanning signal line, and the data signal line provides a corresponding ith row of data signals for the ith row of sub-pixels.
12. The display panel of claim 11, wherein during the charging phase of the ith row of sub-pixels in the N rows of sub-pixels,
and if the ith time sequence control line enters a superposition time period of a pre-starting stage of the ith +1 time sequence control line, the first scanning source line also provides an effective scanning signal for the (i + 1) th scanning signal line, and the data signal line also provides the ith row of data signals for the (i + 1) th row of sub-pixels.
13. The display panel of claim 8, wherein the 2 i-th timing control line includes a precharge phase and the 2 i-1-th timing control line does not include a precharge phase, i being less than or equal to N/2.
14. The display panel according to claim 13, further comprising: the scanning signal line is electrically connected with the sub-pixels in one row, and the data signal line is electrically connected with the sub-pixels in one column;
the N rows of scanning signal lines corresponding to one first scanning source line drive N rows of sub-pixels;
the working process of a row of sub-pixels comprises a charging phase;
in a charging stage of the ith row of sub-pixels in the N rows of sub-pixels, the ith timing control line enters a first starting stage, the first scanning source line provides an effective scanning signal for the ith scanning signal line, and the data signal line provides a corresponding ith row of data signals for the ith row of sub-pixels.
15. The display panel of claim 14, wherein during the charging phase of the 2i-1 row of subpixels in the N rows of subpixels,
and if the 2i-1 time sequence control line enters a superposition time period of a pre-starting stage of the 2i time sequence control line, the first scanning source line also provides an effective scanning signal for the 2i scanning signal line, and the data signal line also provides a 2i-1 row data signal for the 2i row of sub-pixels.
16. The display panel according to claim 10 or 13, wherein an end time of the first turn-on phase of the 2 i-th timing control line is earlier than a start time of the pre-turn-on phase of the 2i + 2-th timing control line.
17. The display panel of claim 14, wherein the sub-pixels in the 2j-1 th row and the sub-pixels in the 2j row have the same color, and j is greater than or equal to 1 and less than or equal to N/2.
18. The display panel according to claim 17, wherein N-6; for the N rows of sub-pixels,
the N rows of sub-pixels comprise two adjacent rows of red sub-pixels, two adjacent rows of green sub-pixels and two adjacent rows of blue sub-pixels.
19. A display device characterized by comprising the display panel according to any one of claims 1 to 18.
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| CN105139798A (en) * | 2015-10-20 | 2015-12-09 | 京东方科技集团股份有限公司 | Driving circuit for touch screen, embedded touch screen and display device |
| WO2018188020A1 (en) * | 2017-04-13 | 2018-10-18 | Boe Technology Group Co., Ltd. | Shift register circuit and driving method thereof, gate driver on array circuit, and touch sensing display panel |
| CN108648711A (en) * | 2018-06-08 | 2018-10-12 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
| CN109935212A (en) * | 2019-02-28 | 2019-06-25 | 合肥京东方卓印科技有限公司 | Display panel, display device and driving method |
| CN111445824A (en) * | 2020-03-10 | 2020-07-24 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113470559A (en) * | 2021-06-29 | 2021-10-01 | 厦门天马微电子有限公司 | Driving circuit, driving method, display panel and device |
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