CN114361160A - Semiconductor device, dynamic random access memory and electronic equipment - Google Patents

Abstract

The present disclosure provides a semiconductor device, a dynamic random access memory, and an electronic apparatus, the semiconductor device including a semiconductor substrate, a trench isolation layer, a gate oxide layer, a first barrier layer, a second barrier layer, a first conductive layer, a second conductive layer, and the like. The semiconductor substrate is provided with a first groove and a second groove, the groove isolation layer is attached to the bottom wall and the side wall of the first groove, and the gate oxide layer is attached to the bottom wall and the side wall of the second groove. The first barrier layer is deposited on the groove isolation layer, the second barrier layer is deposited on the gate oxide layer, and the height of the upper surface of the first barrier layer is smaller than that of the upper surface of the second barrier layer. The first conducting layer is filled in a first space surrounded by the first barrier layer, and the second conducting layer is filled in a second space surrounded by the second barrier layer. The memory includes the semiconductor device of the present disclosure, and the electronic device includes the memory. The present disclosure can effectively suppress the problem of gate-induced drain leakage current by a brand new semiconductor device structure.

Description

A semiconductor device, dynamic random access memory and electronic equipment

technical field

The present disclosure relates to the technical field of semiconductor devices, and more particularly, the present disclosure relates to a semiconductor device, a dynamic random access memory, and an electronic device.

Background technique

With the design rule shrinking of integrated circuits, the dimensions of circuits are continuously reduced, and the distance between adjacent structures (eg, between adjacent word lines WL, etc.) is continuously reduced. Among them, the problem of Gate Induced Drain Leakage (GIDL), which has a great influence on devices such as Dynamic Random Access Memory (DRAM), has become more and more serious, which greatly affects semiconductor devices. The refresh (Refresh) performance. Some people have proposed a scheme to increase the depth of a recessed channel (Recess Channel), but this scheme cannot meet the requirements of miniaturization of semiconductor devices. Although the existing technology can reduce a certain amount of leakage current by improving the dopant profile of the semiconductor substrate, this method has a limited impact on the leakage current, and it is actually difficult to meet the actual design requirements of semiconductor devices whose dimensions are shrinking. . Therefore, the problem of gate-induced drain leakage current needs to be solved urgently.

SUMMARY OF THE INVENTION

In order to solve the problems that the existing solutions for increasing the channel depth cannot meet the miniaturization design requirements of semiconductor devices and the way to improve the doping distribution of the semiconductor substrate is still limited in reducing the gate-induced drain leakage current, the present disclosure provides a semiconductor device. , dynamic random access memory and electronic equipment. The present disclosure adopts the improved device structure design, and achieves the purpose of effectively suppressing the gate-induced drain leakage current without increasing the size of the device.

To achieve the above technical purpose, the present disclosure provides a semiconductor device. The semiconductor device may include, but is not limited to, a semiconductor substrate, a trench isolation layer, a gate oxide layer, a first barrier layer, a second barrier layer, a first conductive layer, a second conductive layer, and the like. A first groove and a second groove are arranged on the semiconductor substrate, the trench isolation layer is attached to the bottom wall and side wall of the first groove, and the gate oxide layer is attached to the bottom wall and side wall of the second groove on the wall. The first barrier layer is deposited on the trench isolation layer, the second barrier layer is deposited on the gate oxide layer, and the height of the upper surface of the first barrier layer is smaller than the height of the upper surface of the second barrier layer. The first conductive layer is filled in the first space enclosed by the first barrier layer, and the second conductive layer is filled in the second space enclosed by the second barrier layer.

To achieve the above technical purpose, the present disclosure can also provide a semiconductor device. The semiconductor device may include, but is not limited to, a semiconductor substrate, a trench isolation layer, a gate oxide layer, a first barrier layer, a second barrier layer, a first conductive layer, a second conductive layer, a polysilicon layer, and the like. A first groove and a second groove are arranged on the semiconductor substrate, the trench isolation layer is attached to the bottom wall and side wall of the first groove, and the gate oxide layer is attached to the bottom wall and side wall of the second groove on the wall. The first barrier layer is deposited on the trench isolation layer, the second barrier layer is deposited on the gate oxide layer, and the height of the upper surface of the first barrier layer is equal to the height of the upper surface of the second barrier layer. The polysilicon layer is disposed on top of the second conductive layer.

To achieve the above technical purpose, the present disclosure also provides a dynamic random access memory. The dynamic random access memory includes, but is not limited to, the semiconductor device in any of the embodiments of the present disclosure.

To achieve the above technical purpose, the present disclosure can also provide an electronic device, which may include, but is not limited to, the dynamic random access memory in any embodiment of the present disclosure.

The beneficial effects of the present disclosure are that the technical solutions provided by the present disclosure can effectively suppress the gate-induced drain leakage current through a new semiconductor device structure design, thereby better solving many problems existing in the prior art. By directly or indirectly reducing the height of the first conductive layer and/or the first barrier layer, the electric field intensity is reduced, that is, the electric field intensity between the field-pass gate and the main gate is effectively reduced, so as to significantly reduce the gate induced drain purpose of leakage current.

Description of drawings

FIG. 1 shows a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device in Embodiment 1 of the present disclosure.

FIG. 2 shows a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device in Embodiment 2 of the present disclosure.

FIG. 3 shows a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device in Embodiment 3 of the present disclosure.

FIG. 4 is a schematic top-view structural diagram of a semiconductor device provided with a photoresist layer having a circular through hole pattern in some embodiments of the present disclosure.

FIG. 5 is a schematic top-view structural schematic diagram of a semiconductor device provided with a photoresist layer having a strip pattern according to other embodiments of the present disclosure.

In the figure,

100. A semiconductor substrate.

101. A first groove.

102. The second groove.

200. A trench isolation layer.

300. Gate oxide layer.

400. A first barrier layer.

401. A second barrier layer.

500. A first conductive layer.

501. A second conductive layer.

502. A polysilicon layer.

600. Photoresist layer.

WL, word line.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and those skilled in the art will Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

Example 1:

As shown in FIG. 1 , this embodiment can provide a semiconductor device. The semiconductor device includes, but is not limited to, a semiconductor substrate 100, a trench isolation layer (Trench Isolation) 200, a gate oxide layer (GOX, Gate Oxide) 300, a first barrier layer 400, a second barrier layer 401, a first conductive layer 500 and The second conductive layer 501 and the like. Specifically, a first groove 101 and a second groove 102 are formed on the semiconductor substrate 100 . A trench isolation layer 200 is disposed in the first groove 101 , and the trench isolation layer 200 is attached to the bottom wall and the side wall of the first groove 101 . A gate oxide layer 300 is disposed in the second groove 102 , and the gate oxide layer 300 is attached to the bottom wall and the side wall of the second groove 102 . The first barrier layer 400 is deposited on the trench isolation layer 200 to dispose the barrier layer 400 in the space surrounded by the trench isolation layer 200 . The second barrier layer 401 is deposited on the gate oxide layer 300 to dispose the second barrier layer 401 in the space surrounded by the gate oxide layer 300 . A first conductive layer 500 is disposed on the first barrier layer 400, the first conductive layer 500 is filled in the first space surrounded by the first barrier layer 400, and the height of the first conductive layer 500 can be greater than or equal to the first barrier layer 400 height. And a second conductive layer 501 is disposed on the second barrier layer 401 , and the second conductive layer 501 is filled in the second space surrounded by the second barrier layer 401 . The height of the upper surface of the first barrier layer 400 is smaller than the height of the upper surface of the second barrier layer 401 , and the height of the upper surface of the first conductive layer 500 is smaller than the height of the upper surface of the second conductive layer 501 . In this embodiment, the first conductive layer 500 is a pass gate, and the second conductive layer 501 is a main gate. Based on the above improved structural design, the present embodiment can effectively increase the distances between the first barrier layer 400 and the field pass gate, respectively, and the storage node (not shown in the figure) that can be disposed above the device layer, thereby effectively reducing the Minimize the Electric Field between the main gate and the field pass gate to significantly reduce the possibility of GIDL problems between the field pass gate and the main gate. Therefore, on the premise of effectively reducing the gate-induced drain leakage current, this embodiment can be applied to design solutions such as sub-20nm DRAM cells. The greatest advantage of this embodiment is that the gate-induced drain leakage current can be minimized, which can be achieved by dry etching. The semiconductor substrate 100 in this embodiment may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a III-V compound semiconductor substrate A substrate or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG), the present disclosure can form an Active Region on the substrate. The material of the trench isolation layer 200 may be, for example, silicon dioxide, and the material of the gate oxide layer 300 may be, for example, silicon dioxide. The materials of the first conductive layer 500 and the second conductive layer 501 may be conductive metals such as metal tungsten, and the materials of the first barrier layer 400 and the second barrier layer 401 may be titanium nitride or the like.

As shown in FIG. 4 , in order to partially etch the first conductive layer 500 and the first barrier layer 400 in FIG. 1 , a photoresist layer 600 having a circular pattern (islandtype) may be used as an etching mask in this embodiment.

As shown in FIG. 5 , in order to partially etch the first conductive layer 500 and the first barrier layer 400 in FIG. 1 , in this embodiment, a photoresist layer 600 having a line type may be used as an etching mask.

Embodiment 2:

Based on the same concept as the first embodiment, this embodiment can also provide a semiconductor device. As shown in FIG. 2 , the semiconductor device includes, but is not limited to, a semiconductor substrate 100 , a trench isolation layer 200 , a gate oxide layer 300 , a first barrier layer 400 , a second barrier layer 401 , a first conductive layer 500 and a second conductive layer 501 etc. Specifically, a first groove 101 and a second groove 102 may be formed on the semiconductor substrate 100 , the trench isolation layer 200 is attached to the bottom wall and sidewall of the first groove 101 , and the gate oxide layer 300 is attached on the bottom wall and side wall of the second groove 102 . The first barrier layer 400 is deposited on the trench isolation layer 200 , and the second barrier layer 401 is deposited on the gate oxide layer 300 . The first conductive layer 500 is filled in the first space surrounded by the first barrier layer 400 , the height of the first conductive layer 500 may be greater than the height of the first barrier layer 400 , and the second conductive layer 501 is filled in the second barrier layer 401 . into the second space. The height of the upper surface of the first barrier layer 400 is smaller than the height of the upper surface of the second barrier layer 401 , and the height of the upper surface of the first conductive layer 500 is equal to the height of the upper surface of the second conductive layer 501 . More specifically, the first conductive layer 500 in this embodiment is a field-pass gate, and the second conductive layer 501 is a main gate. This embodiment can effectively increase the distance between the first barrier layer 400 and the storage node (not shown in the figure) that can be disposed above the device layer, thereby effectively reducing the electric field between the main gate and the field pass gate , to significantly reduce the possibility of GIDL problems between the field pass gate and main gate. In this embodiment, the first barrier layer 400 can be partially etched by dry etching or wet etching. The biggest advantage of this embodiment is that the device refresh performance is improved without increasing the field-pass gate resistance, and there is no need to consider Field pass gate contact redesign. The semiconductor substrate 100 in this embodiment may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a III-V compound semiconductor substrate A substrate or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG), and an active region can be formed on the substrate. The material of the trench isolation layer 200 may be, for example, silicon dioxide, and the material of the gate oxide layer 300 may be, for example, silicon dioxide. The material of the first conductive layer 500 and the second conductive layer 501 can be both metal tungsten, and the material of the first barrier layer 400 and the second barrier layer 401 can be both titanium nitride.

As shown in FIG. 4 , in order to partially etch the first conductive layer 500 and the first barrier layer 400 in FIG. 2 , in this embodiment, a photoresist layer 600 having a circular pattern (island type) can be used as an etching mask .

As shown in FIG. 5 , in order to partially etch the first conductive layer 500 and the first barrier layer 400 in FIG. 2 , a photoresist layer 600 with a line type can be used as an etching mask in this embodiment. .

Embodiment three:

Based on the same technical concept as Embodiment 1 or Embodiment 2, this embodiment can also provide a semiconductor device. As shown in FIG. 3 , the semiconductor device includes, but is not limited to, a semiconductor substrate 100 , a trench isolation layer 200 , a gate oxide layer 300 , a first barrier layer 400 , a second barrier layer 401 , a first conductive layer 500 , and a second conductive layer 501 and the polysilicon layer 502, etc. Specifically, in this embodiment, a first groove 101 and a second groove 102 are formed on the semiconductor substrate 100 , the trench isolation layer 200 is attached to the bottom wall and sidewall of the first groove 101 , the gate oxide layer 300 is It is attached to the bottom wall and the side wall of the second groove 102 . The first barrier layer 400 is deposited on the trench isolation layer 200 , and the second barrier layer 401 is deposited on the gate oxide layer 300 . The first conductive layer 500 is filled in the first space surrounded by the first barrier layer 400 , the height of the first conductive layer 500 can be equal to the height of the first barrier layer 400 , and the second conductive layer 501 is filled in the second barrier layer 401 . into the second space. The polysilicon layer 502 is disposed on top of the second conductive layer 501 . The polysilicon layer 502 in this embodiment is also used as a conductive layer, which is equivalent to indirectly reducing the heights of the first conductive layer 500 and the first barrier layer 400 . The height of the upper surface of the first barrier layer 400 is equal to the height of the upper surface of the second barrier layer 401 , and the height of the upper surface of the first conductive layer 500 is equal to the height of the upper surface of the second conductive layer 501 . As shown in FIG. 3 , the polysilicon layer 502 is also disposed on top of the second barrier layer 401 , that is, the polysilicon layer 502 can be deposited over the second barrier layer 401 and the second conductive layer 501 at the same time and disposed in the space surrounded by the gate oxide layer 300 Inside. Compared with the semiconductor device structure in FIG. 1 or the semiconductor device structure in FIG. 2 , the top surfaces of the first barrier layer 400 , the first conductive layer 500 , the second barrier layer 401 and the second conductive layer 501 in this embodiment are lower. Therefore, this embodiment can effectively increase the distance between the first barrier layer 400 and the field pass gate and the storage node (not shown in the figure) that can be disposed above the device layer, thereby effectively reducing the main gate and the field pass electric field between the gates to significantly reduce the likelihood of induced drain leakage current problems between the field pass gate and the main gate. The advantage of this embodiment is that, while solving the GIDL problem, the polysilicon layer 502 is used as a conductive layer, which can be better applied to the dual work function gate of the sub-20 nm DRAM cell. The semiconductor substrate 100 in this embodiment may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a III-V compound semiconductor substrate A substrate or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG), and an active region can be formed on the substrate. The material of the trench isolation layer 200 may be, for example, silicon dioxide, and the material of the gate oxide layer 300 may be, for example, silicon dioxide. The material of the first conductive layer 500 and the second conductive layer 501 can be both metal tungsten, and the material of the first barrier layer 400 and the second barrier layer 401 can be both titanium nitride.

As shown in FIG. 4 , in order to partially etch the first conductive layer 500 and the first barrier layer 400 in FIG. 3 , in this embodiment, a photoresist layer 600 having a circular pattern (island type) may be used as an etching mask .

As shown in FIG. 5 , in order to partially etch the first conductive layer 500 and the first barrier layer 400 in FIG. 3 , in this embodiment, a photoresist layer 600 having a line type may be used as an etching mask .

Embodiment 4:

This embodiment can provide a dynamic random access memory, and the dynamic random access memory may include the semiconductor device in any of the embodiments of the present disclosure. Among them, the semiconductor device may have Buried Channel Array Transistor (BCAT, Buried Channel Array Transistor).

Embodiment 5:

This embodiment can provide an electronic device, which may include the dynamic random access memory or the semiconductor device in any of the embodiments of the present disclosure. The electronic devices include, but are not limited to, smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, power banks, and the like.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:

the semiconductor device comprises a semiconductor substrate, a first groove and a second groove, wherein the first groove and the second groove are both arranged on the semiconductor substrate;

the groove isolation layer is attached to the bottom wall and the side wall of the first groove;

the gate oxide layer is attached to the bottom wall and the side wall of the second groove;

a first barrier layer deposited on the trench isolation layer;

the second barrier layer is deposited on the gate oxide layer; the height of the upper surface of the first barrier layer is smaller than that of the upper surface of the second barrier layer;

the first conducting layer is filled in a first space surrounded by the first barrier layer;

and the second conducting layer is filled in a second space surrounded by the second barrier layer.

2. The semiconductor device according to claim 1,

the height of the upper surface of the first conducting layer is smaller than that of the upper surface of the second conducting layer.

3. The semiconductor device according to claim 1,

the height of the upper surface of the first conducting layer is equal to that of the upper surface of the second conducting layer.

4. The semiconductor device according to claim 1,

the first conductive layer is a field-pass gate.

5. The semiconductor device according to claim 1,

the second conductive layer is a main gate.

6. A semiconductor device, comprising:

the semiconductor device comprises a semiconductor substrate, a first groove and a second groove, wherein the first groove and the second groove are both arranged on the semiconductor substrate;

the groove isolation layer is attached to the bottom wall and the side wall of the first groove;

the gate oxide layer is attached to the bottom wall and the side wall of the second groove;

a first barrier layer deposited on the trench isolation layer;

the second barrier layer is deposited on the gate oxide layer; the height of the upper surface of the first barrier layer is equal to that of the upper surface of the second barrier layer;

the first conducting layer is filled in a first space surrounded by the first barrier layer;

the second conducting layer is filled in a second space surrounded by the second barrier layer; the height of the upper surface of the first conducting layer is equal to that of the upper surface of the second conducting layer;

and the polycrystalline silicon layer is arranged on the top of the second conducting layer.

7. The semiconductor device according to claim 6,

the polycrystalline silicon layer is also arranged on the top of the second barrier layer.

8. A dynamic random access memory comprising the semiconductor device of any one of claims 1 to 7.

9. An electronic device comprising the dynamic random access memory according to claim 8.

10. The electronic device of claim 9, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

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