CN114373673A - Preparation method of semiconductor structure - Google Patents

Abstract

The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, and sequentially forming a metal layer and a patterned photoresist layer on the substrate, wherein the metal layer comprises copper and aluminum; judging whether the graphical photoresist layer needs to be reworked or not; when the graphical photoresist layer needs to be reworked, sequentially executing an ashing process and a wet cleaning process to remove the graphical photoresist layer; and performing an annealing process on the substrate. By adding an annealing process after photoetching rework, theta phase of aluminum which is difficult to etch and is generated in the metal layer due to temperature change in the ashing process is converted into other space structures which are easy to etch, the etching speed of each part of the metal layer is uniform, and metal residue and hillock defects are avoided.

Description

A kind of preparation method of semiconductor structure

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a semiconductor structure.

Background technique

With the development of semiconductor technology and the improvement of chip integration, metal interconnection lines have become thinner, narrower, and thinner, and the distance between the metal interconnection lines has also become narrower. In the actual production process, the photolithography process often performs photolithography rework, that is, it is necessary to remove all the wrong photoresist. The photoresist in the prior art is generally an organic substance, and the traditional photolithography rework process usually uses an ashing process to remove the photoresist, then performs wet cleaning, and then performs photolithography again.

FIG. 1 is a schematic structural diagram of a method for preparing a semiconductor structure. As shown in FIG. 1 , a substrate 100 is provided, and a metal layer 102 and a photoresist layer to be removed are formed on the substrate 100 . The metal layer 102 The material is aluminum-copper alloy; the photoresist above the metal layer 102 is subjected to an ashing process, and the temperature of the ashing process is usually 250° C. to 300° C. At this temperature, the metal layer 102 is prone to produce aluminum theta (θ) phase, the theta phase of the aluminum is copper dialuminide, the copper dialuminide particles 104 are difficult to remove, which will cause the copper dialuminide particles to be etched again when the metal layer 102 is etched again. The metal layer 102 below 104 cannot be completely etched away (the circled part in the figure). As shown in FIG. 2 , when the dielectric layer 106 and the passivation layer 108 are conformally formed on the metal layer 102 , the metal residues on the surface of the semiconductor device corresponding to the positions of the copper dichalcogenide particles 104 may be raised. FIG. 3 is a visual inspection diagram of defects in a normal batch of semiconductor devices, and FIG. 4 is a visual inspection diagram of defects in the semiconductor device in FIG. 2 . The hillock defect generated by the bump shown in FIG. 4 will affect the performance and good quality of the semiconductor device. rate has an impact.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for preparing a semiconductor structure, which can eliminate the metal residues and hillock defects generated during the rework of the photoresist layer.

In order to achieve the above object, the present invention provides a method for preparing a semiconductor structure, comprising:

providing a substrate on which a metal layer and a patterned photoresist layer are sequentially formed, the metal layer comprising copper and aluminum;

determining whether the patterned photoresist layer needs to be reworked;

When it is determined that the patterned photoresist layer needs to be reworked, an ashing process and a wet cleaning process are sequentially performed to remove the patterned photoresist layer;

An annealing process is performed on the substrate.

Optionally, after forming the metal layer and before forming the patterned photoresist layer, the method further includes:

A titanium deposition layer and a titanium nitride layer are sequentially formed on the metal layer.

Optionally, the thickness of the titanium deposition layer is greater than

Optionally, the steps of forming the titanium deposition layer and the titanium nitride layer include:

placing the substrate in a vacuum chamber, and feeding a titanium-containing gas into the vacuum chamber to form the titanium deposition layer on the metal layer;

Nitrogen gas was introduced into the vacuum chamber to form a titanium nitride layer on the titanium deposition layer.

Optionally, the steps of forming the titanium deposition layer and the titanium nitride layer include:

forming a first titanium deposition layer on the substrate;

The substrate is placed in a vacuum chamber, and a titanium-containing gas is introduced into the vacuum chamber to form a second titanium deposition layer on the first titanium deposition layer, the first titanium deposition layer and the first titanium deposition layer. The titanium deposition layer constitutes the titanium deposition layer;

Nitrogen gas was introduced into the vacuum chamber to form a titanium nitride layer on the titanium deposition layer.

Optionally, the flow rate of nitrogen gas is 3000 sccm to 3600 sccm.

Optionally, before the ashing process is performed on the photoresist layer, the method further includes:

An anti-reflection layer is formed on the titanium nitride layer, and the anti-reflection layer covers the titanium nitride layer.

Optionally, a barrier layer is further formed between the substrate and the metal layer.

Optionally, after the annealing process is performed on the substrate, the method further includes:

Re-form patterned photoresist;

etching the titanium nitride layer, the titanium deposition layer and the metal layer, and the remaining titanium nitride layer, the titanium deposition layer and the metal layer constitute a metal wiring layer;

A dielectric layer and a passivation layer are sequentially formed on the metal wiring layer.

Optionally, the temperature of the annealing process is 340°C to 600°C.

The present invention provides a method for preparing a semiconductor structure, comprising: providing a substrate, and sequentially forming a metal layer and a patterned photoresist layer on the substrate, the metal layer comprising copper and aluminum; Whether the photoresist layer needs to be reworked; when it is determined that the patterned photoresist layer needs to be reworked, an ashing process and a wet cleaning process are sequentially performed to remove the patterned photoresist layer; The substrate is subjected to an annealing process. By adding a one-step annealing process after photolithography rework, the theta phase of aluminum in the metal layer, which is difficult to etch due to temperature changes in the ashing process, is transformed into other spatial structures that are easy to etch, and the metal layer is uniform. Etch speed everywhere to avoid metal residue and hillock defects.

In addition, the thickness of the titanium deposition layer is increased to avoid cracks in the titanium nitride layer and the titanium deposition layer during the annealing process, so as to prevent the developer from passing through the cracks when the metal layer is etched again. It reacts with the metal layer to form aluminum oxide which is difficult to etch, which further ensures the performance of the semiconductor device.

Description of drawings

1 is a schematic structural diagram of a method for preparing a semiconductor structure;

Fig. 2 is the scanning electron microscope topography of the metal layer of the semiconductor device shown in Fig. 1;

Fig. 3 is a defect visual inspection diagram of a normal batch of semiconductor devices;

Fig. 4 is a defect visual inspection diagram of the semiconductor device in Fig. 2;

FIG. 5 is a flowchart of a method for fabricating a semiconductor structure provided in Embodiment 1 of the present invention;

6 to 9 are schematic structural diagrams corresponding to corresponding steps of a method for preparing a semiconductor structure provided in Embodiment 1 of the present invention;

10 is a schematic structural diagram of a semiconductor structure according to Embodiment 2 of the present invention;

11-12 are scanning electron microscope topography diagrams of the semiconductor device when the titanium nitride layer is cracked;

Among them, the accompanying drawings are as follows:

100, 200-substrate; 204-barrier layer; 206, 102-metal layer; 208-titanium deposition layer; 208a-first titanium deposition layer; 208b-second titanium deposition layer; 210-titanium nitride layer; 104, 207-copper dialuminide particles; 106-dielectric layer; 108-passivation layer.

Detailed ways

The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

In the following, the terms "first," "second," etc. are used to distinguish between similar elements, and are not necessarily used to describe a particular order or temporal order. It is to be understood that these terms so used may be substituted under appropriate circumstances. Similarly, if a method described herein includes a series of steps, the steps presented herein are not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and/or some others not described by the text Steps can be added to the method.

Example 1

FIG. 5 is a flowchart of a method for preparing a semiconductor structure provided in this embodiment. As shown in FIG. 5 , the present invention provides a method for preparing a semiconductor structure, including:

Step S1: providing a substrate, and sequentially forming a metal layer and a patterned photoresist layer on the substrate, the metal layer comprising copper and aluminum;

Step S2: judging whether the patterned photoresist layer needs to be reworked;

Step S3: when it is determined that the patterned photoresist layer needs to be reworked, an ashing process and a wet cleaning process are sequentially performed to remove the patterned photoresist layer;

Step S4: performing an annealing process on the substrate.

6 to 9 are schematic structural diagrams corresponding to corresponding steps of a method for preparing a semiconductor structure provided in this embodiment. The following describes the method for preparing a semiconductor structure provided in this embodiment in more detail with reference to FIGS. 6 to 9 . Alternative embodiments of the present invention are illustrated therein.

As shown in FIG. 6 , a substrate 200 is provided, and a metal layer 206 is formed on the substrate 200 . The material of the metal layer 206 includes copper and aluminum, for example, an aluminum-copper alloy. A device structure may be formed in the substrate 200 , and the metal layer 206 and the device structure may be electrically connected through a plug structure.

A barrier layer 204 may also be formed between the substrate 200 and the metal layer 206, and the material of the barrier layer 204 may be titanium metal or titanium nitride, and the barrier layer 204 may make the metal layer 206 and the A good electrical connection is formed between the substrate 200 and the plug structure.

所述金属层206的厚度为

Wherein, the thickness of the barrier layer 204 is

The thickness of the metal layer 206 is

As shown in FIG. 7 , a titanium deposition layer 208 and a titanium nitride layer 210 are formed on the metal layer 206 .

Specifically, a first titanium deposition layer 208a is formed on the metal layer 206 through a chemical vapor deposition process or a physical vapor deposition process. The substrate 200 is then placed in a vacuum chamber, and a titanium-containing gas is introduced into the vacuum chamber to form a second titanium deposition layer 208b on the first titanium deposition layer 208a, and the first titanium deposition layer 208a and the second titanium deposition layer 208b constitute the titanium deposition layer 208; finally, nitrogen gas is introduced into the vacuum chamber, and the nitrogen gas reacts with the titanium-containing gas to form the titanium deposition layer 208 the titanium nitride layer 210 .

In this embodiment, the gaseous state of the titanium-containing gas is titanium halide.

通入的所述氮气的流量为3000sccm～3600sccm。Wherein, the thickness of the titanium deposition layer is greater than

The flow rate of the introduced nitrogen gas is 3000 sccm to 3600 sccm.

As shown in FIG. 8 , a patterned photoresist layer is formed on the titanium nitride layer 210 for etching the titanium nitride layer, the titanium deposition layer and the metal layer to form a metal wiring layer mask.

Determine whether the photoresist layer needs to be reworked. When the patterned photoresist layer needs to be reworked, an ashing process is used to remove the patterned photoresist layer, and a wet cleaning process is used to remove residues of the patterned photoresist layer.

Wherein, the temperature of the ashing process is 200°C to 300°C.

Since the material of the metal layer 206 is an aluminum-copper alloy, the spatial structure of the aluminum-copper alloy will change under the temperature condition of 200°C to 300°C, resulting in the theta phase of aluminum, and the theta phase of the aluminum is copper dialuminide, The copper dialuminide particles are difficult to be etched, and if the copper dialuminide particles are not eliminated and the photolithography is carried out directly again, metal residues and hillock defects will be generated at the corresponding positions of the copper dialuminide particles.

As shown in FIG. 9 , an annealing process is performed on the substrate 200 . The temperature of the annealing process is 340°C to 600°C. Under the temperature condition of 340°C to 600°C for the aluminum-copper alloy, the inner surface of the metal layer 206 The theta phase of aluminum will be transformed into other easily etched space structures, thereby eliminating the copper dialuminide particles and uniformizing the etching speed of the metal layer 206 everywhere.

Further, after the annealing process is performed on the substrate, the method further includes:

Re-form a patterned photoresist layer on the titanium nitride layer 210; etch the titanium nitride layer 210, the titanium deposition layer 208 and the metal layer 206, and the remaining titanium nitride layer 210. The titanium deposition layer 208 and the metal layer 206 form a metal wiring layer; and then a dielectric layer and a passivation layer are sequentially formed on the metal wiring layer.

则难以抵所述氮化钛层210产生的应力，使所述氮化钛层210产生裂缝，所述裂缝会暴露出所述金属层206。当对所述氮化钛层210、所述钛沉积层208及所述金属层206进行再次光刻时，显影液会通过所述裂缝与所述金属层206反应产生氧化铝，而氧化铝的性质与铝铜合金不同且不溶于有机溶剂，刻蚀形成所述金属布线层时，难以刻蚀所述氧化铝及所述氧化铝下方的所述金属层206，使各金属布线之间存在金属残留，容易导致半导体器件的短路。与此同时所述金属残留对后续器件的平坦化及膜层厚度的均匀性都会产生影响，进一步影响半导体器件的性能。图11～12为所述氮化钛层产生裂缝时半导体器件的扫描电镜形貌图，如图11及图12所示，产生所述氧化铝的位置在后续的钝化层沉积过程中出现了明显的凸起。It should be noted that when the substrate 200 is subjected to the annealing process, the titanium nitride layer 210 will generate greater stress due to temperature changes, if the titanium deposition layer is smaller than

Then, it is difficult to resist the stress generated by the titanium nitride layer 210 , causing cracks in the titanium nitride layer 210 , and the cracks will expose the metal layer 206 . When the titanium nitride layer 210 , the titanium deposition layer 208 and the metal layer 206 are photoetched again, the developer reacts with the metal layer 206 through the cracks to generate aluminum oxide, and the aluminum oxide The properties are different from that of aluminum-copper alloy and are insoluble in organic solvents. When the metal wiring layer is formed by etching, it is difficult to etch the aluminum oxide and the metal layer 206 under the aluminum oxide, so that there is metal between the metal wirings. Residual, easily lead to short circuit of the semiconductor device. At the same time, the metal residue will affect the planarization of subsequent devices and the uniformity of the film thickness, and further affect the performance of the semiconductor device. Figures 11-12 are SEM topographic views of the semiconductor device when the titanium nitride layer has cracks. As shown in Figures 11 and 12, the position where the aluminum oxide is generated appears in the subsequent passivation layer deposition process. Obvious bulge.

以保证所述钛沉积层208可以在后续工艺中减小所述氮化钛层210的应力，避免产生所述裂缝。In this embodiment, the thickness of the titanium deposition layer 208 is greater than

In order to ensure that the titanium deposition layer 208 can reduce the stress of the titanium nitride layer 210 in the subsequent process, the cracks can be avoided.

In other optional embodiments, an anti-reflection coating (BARC, Bottom Anti-Reflective Coatings) may also be formed on the titanium nitride layer 210, and the anti-reflection coating covers the titanium nitride layer 210, so The anti-reflection coating can protect the underlying metal layer 206 from reacting with the developing solution during the developing process of the photoresist.

Embodiment 2

FIG. 10 is a schematic structural diagram of a semiconductor structure provided in this embodiment. As shown in FIG. 10 , the difference between this embodiment and Embodiment 1 is only that the titanium deposition layer 208 is formed in one step in a vacuum chamber.

Specifically, after the metal layer 206 is formed on the substrate 200 , the substrate 200 is placed in a vacuum chamber, and a gas containing titanium is passed into the vacuum chamber to form the metal layer 206 The titanium deposition layer 208 that meets the thickness requirement, the thickness of the titanium deposition layer 208 is greater than

In conclusion, the present invention provides a method for fabricating a semiconductor structure, including: providing a substrate 200, and sequentially forming a metal layer 206 and a patterned photoresist layer on the substrate 200, the metal layer 206 comprising copper and aluminum; determine whether the patterned photoresist layer needs to be reworked; when it is determined that the patterned photoresist layer needs to be reworked, perform an ashing process and a wet cleaning process in sequence to remove the patterned photoresist layer. a resist layer; an annealing process is performed on the substrate. By adding a one-step annealing process after photolithography rework, the theta phase of aluminum in the metal layer 206 that is difficult to be etched due to temperature changes in the ashing process is transformed into other spatial structures, and the metal layer 206 is uniform throughout high etch rate to avoid metal residues and hillock defects. In addition, the thickness of the titanium deposition layer 208 is increased to avoid cracks in the titanium nitride layer 210 and the titanium deposition layer 208 during the annealing process, thereby preventing the developing solution from etching the metal layer 206 again. The cracks react with the metal layer 206 to form aluminum oxide that is difficult to etch, thereby further ensuring the performance of the semiconductor device.

The above are only preferred embodiments of the present invention, and do not have any limiting effect on the present invention. Any person skilled in the art, within the scope of not departing from the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, and does not depart from the technical solution of the present invention. content still falls within the protection scope of the present invention.

Claims (10)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, and sequentially forming a metal layer and a patterned photoresist layer on the substrate, wherein the metal layer comprises copper and aluminum;

judging whether the graphical photoresist layer needs to be reworked or not;

when the graphical photoresist layer needs to be reworked, sequentially executing an ashing process and a wet cleaning process to remove the graphical photoresist layer;

and performing an annealing process on the substrate.

2. The method of claim 1, wherein after forming the metal layer and before forming the patterned photoresist layer, further comprising:

and sequentially forming a titanium deposition layer and a titanium nitride layer on the metal layer.

3. The method of claim 2, wherein the titanium deposition layer has a thickness greater than the thickness of the titanium deposition layer

4. The method of claim 2, wherein the step of forming the titanium deposition layer and the titanium nitride layer comprises:

placing the substrate in a vacuum cavity, and introducing a titanium-containing gas into the vacuum cavity to form the titanium deposition layer on the metal layer;

and introducing nitrogen into the vacuum cavity to form the titanium nitride layer on the titanium deposition layer.

5. The method of claim 2, wherein the step of forming the titanium deposition layer and the titanium nitride layer comprises:

forming a first titanium deposition layer on the substrate;

placing the substrate in a vacuum chamber, and introducing a titanium-containing gas into the vacuum chamber to form a second titanium deposition layer on the first titanium deposition layer, wherein the first titanium deposition layer and the second titanium deposition layer form the titanium deposition layer;

and introducing nitrogen into the vacuum cavity to form the titanium nitride layer on the titanium deposition layer.

6. The method as claimed in claim 4 or 5, wherein the flow rate of nitrogen gas is 3000sccm to 3600 sccm.

7. The method of claim 2, further comprising, prior to subjecting the photoresist layer to an ashing process:

and forming an anti-reflection layer on the titanium nitride layer, wherein the anti-reflection layer covers the titanium nitride layer.

8. The method of claim 2, further comprising, after the annealing the substrate, the steps of:

reforming the patterned photoresist;

etching the titanium nitride layer, the titanium deposition layer and the metal layer, wherein the residual titanium nitride layer, the residual titanium deposition layer and the metal layer form a metal wiring layer;

and sequentially forming a dielectric layer and a passivation layer on the metal wiring layer.

9. The method of claim 1, further comprising forming a barrier layer between the substrate and the metal layer.

10. The method of claim 1, wherein the temperature of the annealing process is 340 ℃ to 600 ℃.

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