CN114373722B - Wafer level packaging structure and packaging method thereof - Google Patents
Wafer level packaging structure and packaging method thereof Download PDFInfo
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- CN114373722B CN114373722B CN202210018397.1A CN202210018397A CN114373722B CN 114373722 B CN114373722 B CN 114373722B CN 202210018397 A CN202210018397 A CN 202210018397A CN 114373722 B CN114373722 B CN 114373722B
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- 238000000034 method Methods 0.000 title claims abstract description 129
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 429
- 239000011241 protective layer Substances 0.000 claims abstract description 86
- 238000002161 passivation Methods 0.000 claims abstract description 85
- 229910000679 solder Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 103
- 230000008569 process Effects 0.000 claims description 91
- 238000005530 etching Methods 0.000 claims description 55
- 239000004020 conductor Substances 0.000 claims description 24
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 21
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 239000012670 alkaline solution Substances 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 7
- 239000011259 mixed solution Substances 0.000 claims description 7
- 239000003929 acidic solution Substances 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 20
- 239000002184 metal Substances 0.000 abstract description 20
- 239000000243 solution Substances 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001556 precipitation Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- -1 titanium ions Chemical class 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- ICXAPFWGVRTEKV-UHFFFAOYSA-N 2-[4-(1,3-benzoxazol-2-yl)phenyl]-1,3-benzoxazole Chemical compound C1=CC=C2OC(C3=CC=C(C=C3)C=3OC4=CC=CC=C4N=3)=NC2=C1 ICXAPFWGVRTEKV-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 230000002349 favourable effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The wafer level packaging method comprises a substrate, a passivation layer, a seed layer, a wire layer, a protective layer and a solder mask layer, wherein the passivation layer is arranged on the substrate, the seed layer is arranged on part of the passivation layer, the wire layer is arranged on the seed layer, the side wall of the seed layer is sunken relative to the bottom of the side wall of the wire layer, the protective layer is arranged on the surface of the wire layer and the side wall of the seed layer, and the solder mask layer is arranged on the surface of the passivation layer and is also arranged on the surface of the protective layer. The situation that the end part of the protective layer is clamped between the passivation layer and the solder mask layer is avoided, the situation that metal is separated out due to the fact that the protective layer is pulled and deformed is reduced, and further the reliability of device performance is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a wafer level package structure and a method for packaging the same.
Background
Wafer level packaging (WAFER LEVEL PACKAGING, WLP) is one of the chip packaging modes, and is to directly package and test a whole wafer after the whole wafer is produced, and cut the wafer into single chips after the whole wafer is finished without wire bonding or glue filling. The wafer level package has the advantages of small package size and excellent electrical performance after package, is easy to be compatible with wafer manufacturing and chip assembly, can simplify the process from wafer manufacturing to product shipment, and reduces the overall production cost.
Re-Routing (RDL) is to change the contact position (I/O pad) of the IC circuit in the original wafer design by wafer level metal routing or bumping process, so that the IC can be adapted to different package types. The wafer-level metal wiring process is to coat an insulating protection layer on the IC, define a new wire pattern by exposure and development, and then make a new metal circuit by electroplating technology to connect the original aluminum pad and the new bump or pad, so as to achieve the purpose of redistribution of the circuit. The re-wired metal lines are mainly sputtered copper material, and can be plated with nickel or nickel-palladium-gold as required.
However, the existing rewiring structure needs to be further improved.
Disclosure of Invention
The invention solves the technical problem of providing a wafer level packaging structure and a packaging method so as to improve the reliability of packaging interconnection.
In order to solve the technical problems, the technical scheme of the invention provides a wafer level packaging structure, which comprises a substrate, a passivation layer, a seed layer, a wire layer, a protective layer and a solder mask layer, wherein the passivation layer is arranged on the substrate, the seed layer is arranged on part of the passivation layer, the wire layer is arranged on the seed layer, the side wall of the seed layer is sunken relative to the bottom of the side wall of the wire layer, the protective layer is arranged on the surface of the wire layer and the side wall of the seed layer, and the solder mask layer is arranged on the surface of the passivation layer and is also arranged on the surface of the protective layer.
Optionally, a groove is formed in the passivation layer exposed by the protective layer, and the solder mask layer is further located in the groove.
Optionally, the depth of the groove ranges from 2 μm to 4 μm.
Optionally, the depth of the recess of the seed layer sidewall relative to the bottom of the conductive line sidewall ranges from 0.3 μm to 2 μm.
Optionally, the passivation layer has a thickness ranging from 1000A to 4000A, the conductive layer has a thickness ranging from 2 μm to 10 μm, and the protective layer has a thickness ranging from 2 μm to 4 μm.
Optionally, the material of the passivation layer comprises polyimide, the material of the seed layer comprises titanium, the material of the wire layer comprises copper, and the material of the protective layer comprises one or both of nickel and gold.
Optionally, an included angle between the extending direction of the side wall of the wire layer and the normal direction of the substrate surface is in a range of 25 ° to 75 °.
Optionally, the substrate includes a functional device layer, the surface of the substrate exposes a bonding pad electrically coupled to the functional device layer, the passivation layer exposes the bonding pad, and the seed layer is further located on the bonding pad.
Correspondingly, the technical scheme of the invention also provides a wafer level packaging method, which comprises the steps of providing a substrate, forming a passivation layer on the substrate, forming a seed layer and a wire layer positioned on the surface of the seed layer on part of the surface of the passivation layer, enabling the side wall of the seed layer to be sunken relative to the bottom of the side wall of the wire layer, forming a protective layer on the surface of the wire layer and the side wall of the seed layer after forming the seed layer, forming a solder mask layer on the surface of the passivation layer after forming the protective layer, and enabling the solder mask layer to be positioned on the surface of the protective layer.
Optionally, after the protective layer is formed and before the solder mask layer is formed, a groove is formed in the passivation layer exposed by the protective layer, and the solder mask layer is further positioned in the groove.
Optionally, the groove forming process comprises a dry etching process, wherein the process parameters of the dry etching process comprise that etching gas comprises oxygen, the power range is 500-1000W, the air flow range is 100-200 sccm, the cavity pressure range is lower than 1mTorr, and the cavity temperature range is 100-300 ℃.
Optionally, the depth of the groove ranges from 2 μm to 4 μm.
The method for forming the seed layer and the wire layer comprises the steps of forming a seed material layer on the surface of the passivation layer, forming a wire material layer on the surface of the seed material layer, forming a mask layer on the surface of the wire material layer, wherein a part of the surface of the wire material layer is exposed by the mask layer, etching the wire material layer and the seed material layer by taking the mask layer as a mask, forming the wire layer by taking the wire material layer, forming the seed layer by taking the seed material layer, and removing the mask layer after forming the seed layer.
Optionally, the method for etching the wire material layer and the seed material layer comprises the steps of etching the wire material layer and the seed material layer by adopting a first etching process until the surface of the passivation layer is exposed, forming the wire layer by using the wire material layer, forming an initial seed layer by using the seed material layer, and etching the side wall of the initial seed layer by adopting a second etching process to form the seed layer.
Optionally, the first etching process comprises a dry etching process, the second etching process comprises a wet etching process, and the technological parameters of the wet etching process comprise that etching liquid comprises an acidic solution or an alkaline solution, wherein the acidic solution comprises hydrofluoric acid, and the alkaline solution comprises a mixed solution of sodium hydroxide and hydrogen peroxide.
Optionally, the method for etching the wire material layer and the seed material layer comprises the steps of etching the wire material layer by a first etching process until the surface of the seed material layer is exposed, forming the wire layer by the wire material layer, and etching the seed material layer exposed by the wire layer by a second etching process to form the seed layer.
Optionally, the first etching process comprises a dry etching process, the second etching process comprises a wet etching process, and the technological parameters of the wet etching process comprise that etching liquid comprises an acidic solution or an alkaline solution, wherein the acidic solution comprises hydrofluoric acid, and the alkaline solution comprises a mixed solution of sodium hydroxide and hydrogen peroxide.
Optionally, the forming process of the conductive material layer comprises an electroplating process, and the forming process of the seed material layer comprises a physical vapor deposition process.
Optionally, the material of the passivation layer comprises polyimide, the material of the seed layer comprises titanium, the material of the wire layer comprises copper, and the material of the protective layer comprises one or both of nickel and gold.
Optionally, the forming process of the protective layer includes an electroless plating process or an electroplating process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the wafer level packaging method provided by the technical scheme of the invention, the initial seed layer side wall is etched to form the seed layer, the seed layer side wall is sunken relative to the bottom of the wire layer side wall, the surface of the wire layer and the seed layer side wall form the protective layer, the protective layer and the seed layer fully wrap the periphery of the wire layer, the condition that the end part of the protective layer is clamped between the passivation layer and the solder mask layer is avoided, the condition that metal is separated out due to the fact that the protective layer is pulled and deformed is reduced, and the reliability of the device performance is further improved.
And forming a groove in the passivation layer exposed by the wire layer after the protective layer is formed and before the solder mask layer is formed, wherein the solder mask layer is also positioned in the groove, so that the interface between the passivation layer and the solder mask layer is positioned on a different interface with the end part of the protective layer, the probability of metal precipitation of the end part of the protective layer through the interface between the passivation layer and the solder mask layer is reduced, and the reliability of the device performance is further improved.
In the wafer level packaging structure provided by the technical scheme of the invention, the protective layer is positioned on the surface of the wire layer and on the side wall of the seed layer, the protective layer and the seed layer fully wrap the periphery of the wire layer, so that the condition that the end part of the protective layer is clamped between the passivation layer and the solder mask layer is avoided, the condition that metal is separated out due to the fact that the protective layer is pulled and deformed is reduced, and the reliability of the device performance is further improved.
Drawings
FIGS. 1-3 are schematic diagrams illustrating steps of a wafer level packaging method;
Fig. 4 to 10 are schematic structural views illustrating steps of a wafer level packaging method according to an embodiment of the present invention;
Fig. 11 to 12 are schematic structural views illustrating steps of a wafer level packaging method according to another embodiment of the present invention.
Detailed Description
As described in the background, the performance of the package structure formed by the conventional wafer level packaging method is in need of improvement. The analysis will now be described in connection with a wafer level packaging method.
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 to 3 are schematic structural views illustrating steps of a wafer level packaging method.
Referring to fig. 1, a substrate 101 is provided, a passivation layer 102 is formed on the substrate 101, a titanium seed material layer (not shown) is formed on the passivation layer 102, a copper material layer (not shown) is formed on the titanium seed material layer, a mask layer 103 is formed on the copper material layer, the mask layer 103 exposes a part of the surface of the copper material layer, the copper material layer and the titanium seed material layer are etched by taking the mask layer 103 as a mask until the surface of the passivation layer 102 is exposed, a metal layer 104 is formed by the copper material layer, and a seed layer 105 is formed by the titanium seed material layer.
Referring to fig. 2, after the metal layer 104 and the seed layer 105 are formed, the mask layer 103 is removed, and after the mask layer 103 is removed, a cleaning process is performed on the surface of the passivation layer 102.
Referring to fig. 3, a protective layer is formed on the surface of the metal layer 104, wherein the protective layer includes a nickel material layer 106 and a gold material layer 107 on the nickel material layer 106, and after the protective layer is formed, a solder mask layer 108 is formed on the surface of the passivation layer 102 and the surface of the protective layer.
The above method is used in wafer level packaging, the material of the passivation layer 102 is Polyimide (PI), the titanium seed material layer is usually formed by a physical vapor deposition process, in which titanium ions are easily attached to the surface of the passivation layer 102, and the cleaning process is used for removing the titanium ions on the surface of the passivation layer 102. In the cleaning process, the surface of the passivation layer 102 is etched, and since the reaction of the etching liquid is isotropic, the passivation layer 102 under the seed layer 105 may even be laterally etched, forming a pit a (as shown in fig. 2). The protective layer is formed by an electroless plating process, and due to the pit a, the protective layer has a bent-down end portion B (shown in fig. 3) near the side wall of the pit a.
The coefficient of thermal expansion of the protective layer is much smaller than the coefficients of thermal expansion of the passivation layer 102 and the solder resist layer 108. In the reliability test of the package structure, under the conditions of high temperature, high humidity and bias voltage, the protection layer has larger thermal expansion mismatch with the passivation layer 102 and the solder mask layer 108, so that the metal circuit is easy to be pulled and deformed, and especially the end part B is clamped between the passivation layer 102 and the solder mask layer 108, so that the end part B is more easy to be pulled and deformed. Due to the pulling deformation of the metal circuit, the protection layer is easy to generate metal precipitation along the bottom of the opening a (i.e. at the interface between the solder mask layer 108 and the passivation layer 102), so as to cause problems such as abnormal electromigration between the power supply pin (pin) and the wire grounding terminal (GND) pin (pin) metal circuit, current overload burn phenomenon of part of the circuit, and the like, and reduce the reliability of the device performance.
In order to solve the above problems, in the wafer level packaging method provided by the invention, the initial seed layer side wall is etched to form a seed layer, the seed layer side wall is recessed relative to the bottom of the wire layer side wall, a protection layer is formed on the surface of the wire layer and the seed layer side wall, the protection layer and the seed layer fully wrap the periphery of the wire layer, the condition that the end part of the protection layer is clamped between a passivation layer and a solder mask layer is avoided, the condition that metal is separated out due to the fact that bias voltage exists between adjacent circuits and the protection layer is pulled and deformed under the temperature and humidity conditions under the reliability test condition is reduced, and the reliability of the device performance is further improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 10 are schematic structural views illustrating steps of a wafer level packaging method according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and a passivation layer 201 is formed on the substrate 200.
The substrate 200 includes a functional device layer (not shown), a pad (not shown) electrically coupled to the functional device layer is exposed on the surface of the substrate 200, and the passivation layer 201 exposes the pad. Subsequently, a wire layer is formed on the passivation layer as a rewiring layer for wafer level packaging.
The material of the passivation layer 201 includes polyimide. In this embodiment, the passivation layer 201 is made of polyimide. In other embodiments, the material of the passivation layer may be poly-p-phenylene benzobisoxazole or photosensitive benzocyclobutene.
The passivation layer 201 has a thickness ranging from 5 μm to 10 μm. The thickness refers to a dimension along a direction normal to the surface of the substrate 200.
Subsequently, a seed layer and a wire layer on the surface of the seed layer are formed on a part of the surface of the passivation layer 201, and the sidewall of the seed layer is recessed relative to the bottom of the sidewall of the wire layer. Please refer to fig. 5 to fig. 7 for a method for forming the seed layer and the conductive line layer.
Referring to fig. 5, a seed material layer 300 is formed on the surface of the passivation layer 201, a conductive material layer 301 is formed on the surface of the seed material layer 300, a mask layer 204 is formed on the surface of the conductive material layer 301, and a portion of the surface of the conductive material layer 301 is exposed by the mask layer 204.
The material of the seed material layer 300 includes titanium. In this embodiment, the seed material layer 300 is made of titanium.
The formation process of the seed material layer 300 includes a physical vapor deposition process. In this embodiment, the forming process of the seed material layer 300 is a physical vapor deposition process.
The thickness of the seed material layer 300 ranges from 1000A to 4000A.
The material of the wire material layer 301 includes copper. In this embodiment, the material of the conductive material layer 301 is copper.
The forming process of the conductive material layer 301 includes an electroplating process. In this embodiment, the forming process of the conductive material layer 301 is an electroplating process.
Subsequently, the conductive material layer 301 and the seed material layer 300 are etched using the mask layer 204 as a mask, the conductive material layer 301 is used to form the conductive material layer, and the seed material layer 300 is used to form the seed layer. In this embodiment, the method of etching the conductive material layer 301 and the seed material layer 300 is shown in fig. 6 to 7.
Referring to fig. 6, the conductive line material layer and the seed material layer are etched by a first etching process until the surface of the passivation layer 201 is exposed, the conductive line layer 203 is formed by the conductive line material layer, and the initial seed layer 202 is formed by the seed material layer.
Specifically, the initial seed layer 202 is also located on the bonding pad to electrically couple the wire layer 203 with the bonding pad.
The first etching process includes a dry etching process. The dry etching process is advantageous for forming the wire layer 203 with a better morphology.
An angle a between an extending direction of the sidewall of the wiring layer 203 and a normal direction of the surface of the substrate 200 ranges from 25 ° to 75 °.
The thickness of the wiring layer 203 ranges from 2 μm to 10 μm.
The material of the conductive line layer 203 includes copper.
Referring to fig. 7, a second etching process is used to etch the sidewall of the initial seed layer 202 to form a seed layer 205, the sidewall of the seed layer 205 is recessed with respect to the bottom of the sidewall of the conductive line layer 203, and the mask layer 204 is removed after the seed layer 205 is formed.
The material of the seed layer 205 comprises titanium.
The second etching process includes a wet etching process.
The wet etching process comprises the technological parameters that etching liquid comprises acid solution or alkaline solution, wherein the acid solution comprises hydrofluoric acid, and the alkaline solution comprises mixed solution of sodium hydroxide and hydrogen peroxide. In the wet etching process, the initial seed layer 202 and the passivation layer 201 are provided with a larger etching selection ratio, so that damage to the passivation layer 201 in the etching process is reduced, and the initial seed layer 202 and the wire layer 203 are provided with a larger etching selection ratio, so that damage to the wire layer 203 in the etching process is reduced.
In this embodiment, hydrofluoric acid is used as an etching solution to etch the sidewalls of the initial seed layer 202 to form the seed layer 205.
The depth of the recess of the sidewall of the seed layer 205 with respect to the bottom of the sidewall of the conductive line layer 203 ranges from 0.3 μm to 2 μm.
Referring to fig. 8, after the seed layer 205 is formed, a protective layer is formed on the surface of the conductive line layer 203 and the sidewalls of the seed layer 205.
Because the sidewall of the seed layer 205 is recessed relative to the bottom of the sidewall of the conductive layer 203, the protective layer may be formed on the sidewall of the seed layer 205, so that the protective layer and the seed layer 205 fully wrap the periphery of the conductive layer 203, thereby avoiding the situation that the end of the protective layer is clamped between the passivation layer 201 and the solder mask, reducing the situation that metal is separated out due to the pulling deformation of the protective layer, and further improving the reliability of the device performance.
The material of the protective layer comprises one or both of nickel and gold.
The thickness of the protective layer ranges from 2 μm to 4 μm.
Specifically, in this embodiment, the protective layers include a first protective layer 206 and a second protective layer 207 on the first protective layer 206. More specifically, the first protective layer 206 is nickel, the second protective layer 207 is gold, and the first protective layer has a thickness ranging from 2 μm to 3.5 μm and the second protective layer has a thickness ranging from 0.05 μm to 0.15 μm.
In another embodiment, a third protective layer is further arranged between the first protective layer and the second protective layer, the material of the third protective layer comprises palladium, and the thickness of the third protective layer ranges from 0.2 μm to 1 μm.
The forming process of the protective layer comprises an electroless plating process or an electroplating process. In this embodiment, the forming process of the protective layer is an electroplating process.
After the protective layer is formed, a solder resist layer is formed on the surface of the passivation layer 201.
In this embodiment, after the protective layer is formed and before the solder mask layer is formed, a groove is formed in the passivation layer exposed by the protective layer, please refer to fig. 9. In other embodiments, the grooves may not be formed.
Referring to fig. 9, after the protective layer is formed and before the solder mask layer is formed, a recess 208 is formed in the passivation layer 201 exposed by the protective layer.
Subsequently, the solder mask layer is also formed within the recess 208. The grooves 208 enable the interface between the passivation layer 201 and the solder mask layer to be located on different interfaces with the end of the protection layer, so that the probability of metal precipitation of the end of the protection layer through the interface between the passivation layer 201 and the solder mask layer is reduced, and the reliability of device performance is further improved.
The depth of the grooves 208 ranges from 2 μm to 4 μm. The depth range value is selected because it can have an effect of reducing the probability of metal precipitation without affecting the performance of the passivation layer 201.
The recess 208 is formed by a dry etching process. The dry etching process is favorable for forming grooves with good morphology and improves the stability of device performance.
The dry etching process comprises the following process parameters that etching gas comprises oxygen, the power range is 500W to 1000W, the air flow range is 100sccm to 200sccm, the cavity pressure range is lower than 1mTorr, and the cavity temperature range is 100 ℃ to 300 ℃. In this embodiment, the cavity temperature ranges from 100 ℃ to 200 ℃. The reason for selecting the cavity temperature range is that if the cavity temperature range is greater than 300 ℃, the passivation layer 201 may be recessed by more obvious lateral etching, and the device performance is reduced.
Referring to fig. 10, after the protective layer is formed, a solder mask 209 is formed on the surface of the passivation layer 201, and the solder mask 209 is further located on the surface of the protective layer.
In this embodiment, the solder mask 209 is also located in the recess 208.
The solder mask 209 is used for preventing solder overflow in the subsequent welding process from causing circuit short circuit, preventing non-welding points from being polluted by solder, and the like, and can effectively prevent moisture and protect the circuit.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, and please continue to refer to fig. 10, which includes a substrate 200, a passivation layer 201 disposed on the substrate 200, a seed layer 205 disposed on a portion of the passivation layer 201, and a conductive line layer 203 disposed on the seed layer 205, wherein a sidewall of the seed layer 205 is recessed with respect to a bottom of a sidewall of the conductive line layer 203, a protective layer disposed on a surface of the conductive line layer 203 and a sidewall of the seed layer 205, and a solder mask 209 disposed on a surface of the passivation layer 201, and the solder mask 209 is further disposed on a surface of the protective layer.
The protective layer is positioned on the surface of the wire layer 203 and on the side wall of the seed layer 205, and the protective layer and the seed layer 205 fully wrap the periphery of the wire layer 203, so that the situation that the end part of the protective layer is clamped between the passivation layer 201 and the solder mask 209 is avoided, the situation that metal is separated out due to the fact that the protective layer is pulled and deformed is reduced, and the reliability of the device performance is further improved.
In this embodiment, the passivation layer 201 exposed by the protection layer has a groove 208 therein, and the solder mask 209 is also located in the groove 208.
The depth of the grooves 208 ranges from 2 μm to 4 μm.
The depth of the recess of the sidewall of the seed layer 205 with respect to the bottom of the sidewall of the conductive line layer 203 ranges from 0.3 μm to 2 μm.
The passivation layer 201 has a thickness ranging from 5 μm to 10 μm, the seed layer 205 has a thickness ranging from 1000A to 4000A, the conductive line layer 203 has a thickness ranging from 2 μm to 10 μm, and the protective layer has a thickness ranging from 2 μm to 4 μm.
The material of the passivation layer 201 includes polyimide, the material of the seed layer 205 includes titanium, and the material of the wire layer 203 includes copper.
The material of the protective layer comprises one or both of nickel and gold.
In this embodiment, the protection layer includes a first protection layer 206 and a second protection layer 207 on the first protection layer 206. Specifically, the material of the first protection layer 206 is nickel, and the material of the second protection layer 207 is gold.
The angle between the extending direction of the side wall of the wire layer 203 and the normal direction of the surface of the substrate 200 is in the range of 25 ° to 75 °.
The substrate 200 includes a functional device layer (not shown), a pad (not shown) electrically coupled to the functional device layer is exposed on the surface of the substrate 200, the passivation layer 201 exposes the pad, and the seed layer 205 is further located on the pad.
Fig. 11 to 12 are schematic structural views illustrating steps of a wafer level packaging method according to another embodiment of the present invention.
In this embodiment, the method of etching the conductive material layer and the seed material layer is different from the previous embodiment.
Please refer to fig. 11 with continued reference to fig. 5, the conductive material layer 301 is etched by a first etching process until the surface of the seed material layer 300 is exposed, and the conductive material layer 302 is formed by the conductive material layer 301.
In this embodiment, the first etching process includes a dry etching process.
Referring to fig. 12, the seed material layer 300 exposed by the conductive line layer 302 is etched by a second etching process to form the seed layer 303, and the mask layer 204 is removed after the seed layer 303 is formed.
The wet etching process comprises the technological parameters that etching liquid comprises acid solution or alkaline solution, wherein the acid solution comprises hydrofluoric acid, and the alkaline solution comprises mixed solution of sodium hydroxide and hydrogen peroxide.
Specifically, in this embodiment, the seed material layer 300 exposed by the conductive line layer 302 is etched by using a mixed solution of sodium hydroxide and hydrogen peroxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A wafer level package structure, comprising:
a substrate;
a passivation layer on the substrate;
A seed layer positioned on a part of the passivation layer and a wire layer positioned on the seed layer, wherein the side wall of the seed layer is sunken relative to the bottom of the side wall of the wire layer;
The protective layer is positioned on the surface of the wire layer and on the side wall of the seed layer;
and the solder mask layer is positioned on the surface of the passivation layer, the solder mask layer is also positioned on the surface of the protective layer, and the thermal expansion coefficient of the protective layer is smaller than that of the passivation layer and the solder mask layer.
2. The wafer level package structure of claim 1, wherein the passivation layer has a recess therein, and the solder mask layer is further disposed in the recess.
3. The wafer level package structure of claim 2, wherein the depth of the recess ranges from 2 μm to 4 μm.
4. The wafer level package structure of claim 1, wherein a depth of the recess of the seed layer sidewall relative to the bottom of the conductive line layer sidewall ranges from 0.3 μm to 2 μm.
5. The wafer level package structure of claim 1, wherein the passivation layer has a thickness ranging from 5 μm to 10 μm, the seed layer has a thickness ranging from 1000A to 4000A, the wire layer has a thickness ranging from 2 μm to 10 μm, and the protective layer has a thickness ranging from 2 μm to 4 μm.
6. The wafer level package structure of claim 1, wherein the material of the passivation layer comprises polyimide, the material of the seed layer comprises titanium, the material of the wire layer comprises copper, and the material of the protective layer comprises one or both of nickel and gold.
7. The wafer level package structure of claim 1, wherein an angle between an extension direction of the wire layer sidewall and a normal direction of the substrate surface is in a range of 25 ° to 75 °.
8. The wafer level package structure of claim 1, wherein the substrate includes a functional device layer, the substrate surface exposes a bond pad electrically coupled to the functional device layer, the passivation layer exposes the bond pad, and the seed layer is further on the bond pad.
9. A wafer level packaging method, comprising:
Providing a substrate;
Forming a passivation layer on the substrate;
forming a seed layer and a wire layer positioned on the surface of the seed layer on the surface of part of the passivation layer, wherein the side wall of the seed layer is sunken relative to the bottom of the side wall of the wire layer;
Forming a protective layer on the surface of the wire layer and the side wall of the seed layer after forming the seed layer;
After the protective layer is formed, a solder mask layer is formed on the surface of the passivation layer, the solder mask layer is also positioned on the surface of the protective layer, and the thermal expansion coefficient of the protective layer is smaller than that of the passivation layer and the solder mask layer.
10. The wafer level package method of claim 9, further comprising forming a recess in the passivation layer exposed by the protective layer after forming the protective layer and before forming the solder mask layer, the solder mask layer further being located in the recess.
11. The wafer level package method of claim 10, wherein the recess forming process comprises a dry etching process, wherein the dry etching process comprises etching gas comprising oxygen at a power ranging from 500W to 1000W and a gas flow ranging from 100 sccm to 200 sccm, wherein the chamber pressure ranges below 1 mTorr and the chamber temperature ranges from 100 ℃ to 300 ℃.
12. The wafer level packaging method according to claim 10, wherein the depth of the recess ranges from 2 μm to 4 μm.
13. The wafer level packaging method according to claim 9, wherein the forming method of the seed layer and the wire layer comprises forming a seed material layer on the surface of the passivation layer, forming a wire material layer on the surface of the seed material layer, forming a mask layer on the surface of the wire material layer, wherein a part of the surface of the wire material layer is exposed by the mask layer, etching the wire material layer and the seed material layer by using the mask layer as a mask, forming the wire layer by using the wire material layer, forming the seed layer by using the seed material layer, and removing the mask layer after forming the seed layer.
14. The wafer level packaging method as recited in claim 13, wherein the step of etching the conductive material layer and the seed material layer includes etching the conductive material layer and the seed material layer using a first etching process until the passivation layer surface is exposed, forming the conductive layer from the conductive material layer, forming an initial seed layer from the seed material layer, and etching the initial seed layer sidewall using a second etching process to form the seed layer.
15. The wafer level packaging method according to claim 14, wherein the first etching process comprises a dry etching process, the second etching process comprises a wet etching process, and the process parameters of the wet etching process comprise etching liquid comprising an acidic solution or an alkaline solution comprising hydrofluoric acid, and the alkaline solution comprises a mixed solution of sodium hydroxide and hydrogen peroxide.
16. The wafer level packaging method according to claim 13, wherein the method of etching the conductive material layer and the seed material layer comprises etching the conductive material layer by a first etching process until the surface of the seed material layer is exposed, forming the conductive material layer by the conductive material layer, and etching the seed material layer exposed by the conductive material layer by a second etching process, forming the seed layer.
17. The wafer level packaging method according to claim 16, wherein the first etching process comprises a dry etching process, the second etching process comprises a wet etching process, and the process parameters of the wet etching process comprise etching liquid comprising an acidic solution or an alkaline solution comprising hydrofluoric acid, and the alkaline solution comprises a mixed solution of sodium hydroxide and hydrogen peroxide.
18. The wafer level package method of claim 13, wherein the forming of the conductive material layer comprises an electroplating process and the forming of the seed material layer comprises a physical vapor deposition process.
19. The wafer level packaging method as recited in claim 9, wherein the material of the passivation layer comprises polyimide, the material of the seed layer comprises titanium, the material of the wire layer comprises copper, and the material of the protective layer comprises one or both of nickel and gold.
20. The wafer level packaging method according to claim 9, wherein the process of forming the protective layer comprises an electroless plating process or an electroplating process.
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| TWI576869B (en) * | 2014-01-24 | 2017-04-01 | 精材科技股份有限公司 | Passive component structure and manufacturing method thereof |
| KR20160093390A (en) * | 2015-01-29 | 2016-08-08 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Device And Fabricating Method Thereof |
| US10290605B2 (en) * | 2017-06-30 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fan-out package structure and method for forming the same |
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| US12057536B2 (en) * | 2019-08-30 | 2024-08-06 | Boe Technology Group Co., Ltd. | Backplane, backlight source, display device and manufacturing method of backplane |
| CN110649054A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving CIS chip solder mask stress |
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