CN114414882A - Quadratic fitting processing method, system, device, processor and storage medium for reducing detection power error for RF detection module - Google Patents

Abstract

The invention relates to a quadratic fitting processing method for reducing detection power error for an RF detection module, comprising the following steps: performing linear fitting on power data of a calibration voltage point, and eliminating the power of adjacent voltage points at the same calibration frequency point Error: Fit and calculate the values of two adjacent calibration points of non-calibration frequency points to obtain power data. By adopting the quadratic fitting processing method, system, device, processor and computer-readable storage medium for reducing the detection power error for the RF detection module of the present invention, when the power is detected at different frequency points, the error caused during calibration is eliminated. The error caused by the calibration frequency point is improved by the quadratic fitting algorithm to improve the accuracy of the fitted power during RF detection input detection.

Description

Quadratic fitting processing method, system, device, processor and storage medium for reducing detection power error for RF detection module

technical field

The invention relates to the field of radio frequency instruments, in particular to the field of signal source power calibration, and in particular to a quadratic fitting processing method, system, device, processor and computer-readable storage medium for reducing detection power error for an RF detection module .

Background technique

The RF signal under test is applied to the detector. In measurement mode, the output voltage has a linear dB relationship with the input signal level (nominal values should be based on the manual of the selected log detector), and the typical output voltage range is a V to f V (values of a and f should be based on the selected log detector manual). The measurement results are provided as digital codes at the output of a 12-bit ADC, and the output of the RF detector can be seamlessly interfaced with the ADC.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art, and to provide a quadratic fitting processing method and system for reducing the detection power error for an RF detection module that satisfies the requirements of high accuracy, small error and wide application range. , an apparatus, a processor, and a computer-readable storage medium.

In order to achieve the above object, the quadratic fitting processing method, system, device, processor and computer-readable storage medium for reducing the detection power error for the RF detection module of the present invention are as follows:

The main feature of the quadratic fitting processing method for reducing the detection power error for the RF detection module is that the method includes the following steps:

(1) Perform linear fitting on the power data of the calibration voltage point to eliminate the power error of adjacent voltage points at the same calibration frequency point;

(2) Fitting and calculating the values of two adjacent calibration points of non-calibration frequency points to obtain power data.

Preferably, the step (1) specifically includes the following steps:

(1.1) Judging whether the current voltage PowInV is within the voltage range of the detector, that is, judging whether a<current voltage PowInV<f, where the voltage range of the detector is [a, f], if so, continue to step (1.2) ; otherwise, calculate the corresponding power value when the current voltage PowInV<a and the current voltage PowInV>f;

(1.2) Calculate the position interval of the calibration table and the voltage RemainderInV beyond the calibration voltage point;

(1.3) Calculate and obtain the power value PowIndBmSim of the current voltage fitting.

Preferably, the calibration table position interval is calculated in the step (1.2), specifically:

Calculate the calibration table position interval according to the following formula:

Among them, PowInV is the current voltage, StartPowInV is the starting voltage falling into the range, Step is the interval of the voltage range, and add is the accumulated number.

Preferably, in the step (1.2), calculate the voltage amount RemainderInV beyond the calibration voltage point, specifically:

Calculate the voltage beyond the calibration voltage point, RemainderInV, according to the following formula:

RemainderInV=PowInV-StartPowInV-(interval-add)×Step;

Among them, PowInV is the current voltage, StartPowInV is the starting voltage falling into the range, Step is the interval of the voltage range, add is the accumulated number, and interval is the calibration table position.

Preferably, in the step (1.3), the power value PowIndBmSim fitted by the current voltage is calculated and obtained, specifically:

Calculate the power value PowIndBmSim for the current voltage fit according to the following formula:

PowIndBm1=CaliForm[freqLocation][interval-1];

PowIndBm2=CaliForm[freqLocation][interval];

Among them, FreqLocation is the calibration frequency point, interval is the voltage interval, RemainderInV is the voltage beyond the calibration voltage point, Step is the interval of the voltage range, and PowIndBm1 and PowIndBm2 are the power values obtained from the two-dimensional array, respectively.

Preferably, the step (2) specifically includes the following steps:

(2.1) If the set frequency point is the calibration frequency point, calculate the power value PowIndBmSim corresponding to the voltage; if the set frequency point is not on the calibration frequency point and the frequency point is between the calibration points F0 and F1, where F0<F1, then Proceed to step (2.2);

(2.2) Obtain the corresponding voltage power value PowIndBmSim1 when the frequency point is F0, and the corresponding voltage power value PowIndBmSim2 when the frequency point is F1;

(2.3) The power value corresponding to the voltage at the current frequency is obtained by linear fitting.

Preferably, in the step (2.3), the power value corresponding to the voltage is calculated, specifically:

Calculate the power value corresponding to the voltage according to the following formula:

Among them, PowIndBmSim1 is the corresponding voltage power value when the frequency point is F0, PowIndBmSim2 is the corresponding voltage power value when the frequency point is F1, and Freq is the frequency value.

The main feature of the quadratic fitting processing system for reducing the detection power error for the RF detection module is that the system includes a power divider, a detection module and a power meter, and the input end of the power divider is connected to the signal One end of the output end of the power divider is connected to the detection module, and the other end is connected to the power meter, and the detection module calibrates the signal output by the signal source.

The main feature of the quadratic fitting processing device for reducing the detection power error for the RF detection module is that the device includes:

a processor configured to execute computer-executable instructions;

The memory stores one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, each of the above-mentioned quadratic fitting processing methods for reducing the detection power error for the RF detection module is implemented. step.

The main feature of the processor for implementing quadratic fitting processing for reducing the detected power error of the RF detection module is that the processor is configured to execute computer-executable instructions, and the computer-executable instructions are When executed by the processor, each step of the above-mentioned quadratic fitting processing method for reducing the detected power error for the RF detection module is implemented.

The computer-readable storage medium is mainly characterized in that a computer program is stored thereon, and the computer program can be executed by a processor to realize the above-mentioned quadratic fitting processing method for reducing the detection power error for the RF detection module. of the various steps.

By adopting the quadratic fitting processing method, system, device, processor and computer-readable storage medium for reducing the detection power error for the RF detection module of the present invention, when the power is detected at different frequency points, the error caused during calibration is eliminated. The error caused by the calibration frequency point is improved by the quadratic fitting algorithm to improve the accuracy of the fitted power during RF detection input detection. Compared with the prior art, the first fitting eliminates the error caused by the power meter, and provides more accurate power for the second fitting of non-calibrated frequency points. By querying the calibration table, the redundancy and response time will not be increased. will not increase too much.

Description of drawings

FIG. 1 is a schematic diagram of the calibration of the detection module of the quadratic fitting processing system for reducing the detection power error for the RF detection module of the present invention.

FIG. 2 is a schematic flowchart of a quadratic fitting processing method for reducing the detection power error for an RF detection module according to the present invention.

Detailed ways

In order to describe the technical content of the present invention more clearly, further description will be given below with reference to specific embodiments.

The quadratic fitting processing method for reducing the detection power error for the RF detection module of the present invention includes the following steps:

(1) Perform linear fitting on the power data of the calibration voltage point to eliminate the power error of adjacent voltage points at the same calibration frequency point;

(2) Fitting and calculating the values of two adjacent calibration points of non-calibration frequency points to obtain power data.

As a preferred embodiment of the present invention, the step (1) specifically includes the following steps:

(1.1) Judging whether the current voltage PowInV is within the voltage range of the detector, that is, judging whether a<current voltage PowInV<f, where the voltage range of the detector is [a, f], if so, continue to step (1.2) ; otherwise, calculate the corresponding power value when the current voltage PowInV<a and the current voltage PowInV>f;

(1.2) Calculate the position interval of the calibration table and the voltage RemainderInV beyond the calibration voltage point;

(1.3) Calculate and obtain the power value PowIndBmSim of the current voltage fitting.

As a preferred embodiment of the present invention, the calibration table position interval is calculated in the step (1.2), specifically:

Calculate the calibration table position interval according to the following formula:

Among them, PowInV is the current voltage, StartPowInV is the starting voltage falling into the range, Step is the interval of the voltage range, and add is the accumulated number.

As a preferred embodiment of the present invention, in the step (1.2), the voltage amount RemainderInV that exceeds the calibration voltage point is calculated, specifically:

Calculate the voltage beyond the calibration voltage point, RemainderInV, according to the following formula:

RemainderInV=PowInV-StartPowInV-(interval-add)×Step;

Among them, PowInV is the current voltage, StartPowInV is the starting voltage falling into the range, Step is the interval of the voltage range, add is the accumulated number, and interval is the calibration table position.

As a preferred embodiment of the present invention, in the step (1.3), the power value PowIndBmSim of the current voltage fitting is calculated and obtained, specifically:

Calculate the power value PowIndBmSim for the current voltage fit according to the following formula:

PowIndBm1=CaliForm[freqLocation][interval-1];

PowIndBm2=CaliForm[freqLocation][interval];

Among them, FreqLocation is the calibration frequency point, interval is the voltage interval, RemainderInV is the voltage beyond the calibration voltage point, Step is the interval of the voltage range, and PowIndBm1 and PowIndBm2 are the power values obtained from the two-dimensional array, respectively.

As a preferred embodiment of the present invention, the step (2) specifically includes the following steps:

(2.1) If the set frequency point is the calibration frequency point, calculate the power value PowIndBmSim corresponding to the voltage; if the set frequency point is not on the calibration frequency point and the frequency point is between the calibration points F0 and F1, where F0<F1, then Proceed to step (2.2);

(2.2) Obtain the corresponding voltage power value PowIndBmSim1 when the frequency point is F0, and the corresponding voltage power value PowIndBmSim2 when the frequency point is F1;

(2.3) The power value corresponding to the voltage at the current frequency is obtained by linear fitting.

As a preferred embodiment of the present invention, in the step (2.3), the power value corresponding to the voltage is calculated, specifically:

Calculate the power value corresponding to the voltage according to the following formula:

Among them, PowIndBmSim1 is the corresponding voltage power value when the frequency point is F0, PowIndBmSim2 is the corresponding voltage power value when the frequency point is F1, and Freq is the frequency value.

The RF detection module of the present invention realizes a quadratic fitting processing system for reducing detection power error, wherein the system includes a power divider, a detection module and a power meter, and the input end of the power divider is connected to a signal source. One end of the output end of the power divider is connected to the detection module, and the other end is connected to the power meter, and the detection module calibrates the signal output by the signal source.

The present invention is used to realize the quadratic fitting processing device for reducing the detection power error for the RF detection module, wherein the device includes:

a processor configured to execute computer-executable instructions;

The memory stores one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, each of the above-mentioned quadratic fitting processing methods for reducing the detection power error for the RF detection module is implemented. step.

The processor of the present invention for implementing quadratic fitting processing for reducing detected power error for an RF detection module, wherein the processor is configured to execute computer-executable instructions, and the computer-executable instructions are When the processor is executed, each step of the above-mentioned quadratic fitting processing method for reducing the detected power error for the RF detection module is implemented.

The computer-readable storage medium of the present invention stores a computer program therein, and the computer program can be executed by a processor to implement the steps of the above-mentioned quadratic fitting processing method for reducing the detected power error for the RF detection module. .

In a specific embodiment of the present invention, a quadratic fitting algorithm for reducing the detection power error of the RF detection module is provided. The technical scheme adopted in this scheme is to first perform linear fitting on the power data of the calibration voltage point to eliminate the power error of the adjacent voltage points at the same calibration frequency point, and then re-use the data of the calibration frequency point. The fitting calculation is performed by taking the values of two adjacent calibration points, so as to obtain the ideal power.

As shown in Figure 1, the calibration of the detection module uses the output signal of the signal source, and the rear end of the power divider is connected to the power meter, and the other end is connected to the detection module. As shown in Table 1, the frequency to be calibrated is x to y MHz, and the interval between the calibration frequency points is z MHz. As shown in Table 2, the voltage range of the detector in the detection module is [a, f], and the interval of each voltage calibration range is Kn.

Table 1 Calibration frequency points and intervals

Calibration frequency range (unit: MHz) Frequency point interval (unit: MHz) [x,y] z

Table 2 Calibration voltage range and interval

Voltage range (unit: V) Interval (unit: V) [a,b) K1 [b,c) K2 [c,d) K3 [d,e) K4 [e,f] K5

After calibration, record the data in CaliForm[FreqLocation][interval] which is a two-dimensional array of float type [cal1][cal2].

in,

FreqLocation=(y-x)/z+1=cal1;

interval=(b-a)/K1+(c-b)/K2+(d-c)/K3+(e-d)/K4+(f-e)/K5+1=cal2;

Among them, FreqLocation is the calibration frequency point, interval is the voltage interval, and the corresponding parameter in the two-dimensional array represents the power value, and the unit is dBm.

Step 1: Fitting of calibration voltage points:

Determine the voltage range, record the current voltage as PowInV, the starting voltage falling into the range as StartPowInV, and the interval of the range as Step.

When PowInV<a,

PowIndBm=CaliForm[freqLocation][0];

When PowInV>f,

PowIndBm=CaliForm[freqLocation][cal2];

When a<PowInV<f, the calculation formula of calibration table position interval is:

The voltage beyond the calibration voltage point is recorded as RemainderInV, and the calculation formula is:

RemainderInV=PowInV-StartPowInV-(interval-add)×Step;

The floor in the interval calculation formula is the floor function in the C language; add is the accumulated number, and the specific value is obtained according to Table 3 below.

Table 3. add value table

Two power values are obtained according to the above:

PowIndBm1=CaliForm[freqLocation][interval-1];

PowIndBm2=CaliForm[freqLocation][interval];

Get the power value fitted by the current voltage:

Step 2: Fitting of non-calibrated frequency points:

When the set frequency is the calibration frequency, the power value corresponding to the voltage is PowIndBmSim;

When the frequency is not on the calibration frequency, if the frequency is between the calibration points F0 and F1 (F0 < F1);

Take out the corresponding calibration table IF point as F0, the voltage power value PowIndBmSim1; take out the corresponding calibration table IF point as F1, the voltage power value PowIndBmSim2;

The formula for linearly fitting the power corresponding to the voltage at the current frequency is as follows:

The quadratic fitting of the RF detection module to reduce the detection error power is realized in the above manner.

For the specific implementation solution of this embodiment, reference may be made to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

It can be understood that, the same or similar parts in the above embodiments may refer to each other, and the content not described in detail in some embodiments may refer to the same or similar content in other embodiments.

It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for the purpose of description, and should not be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise specified, the meaning of "plurality" means at least two.

Any description of a process or method in the flowcharts or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing a specified logical function or step of the process , and the scope of the preferred embodiments of the present invention includes alternative implementations in which the functions may be performed out of the order shown or discussed, including performing the functions substantially concurrently or in the reverse order depending upon the functions involved, which should It is understood by those skilled in the art to which the embodiments of the present invention belong.

It should be understood that various parts of the present invention may be implemented in hardware, software, firmware or a combination thereof. In the above-described embodiments, various steps or methods may be implemented in software or firmware stored in memory and executed by suitable instruction execution means. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following techniques known in the art: Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.

Those skilled in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the corresponding program can be stored in a computer-readable storage medium, and the program can be executed when the program is executed. , including one or a combination of the steps of the method embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

By adopting the quadratic fitting processing method, system, device, processor and computer-readable storage medium for reducing the detection power error for the RF detection module of the present invention, when the power is detected at different frequency points, the error caused during calibration is eliminated. The error caused by the calibration frequency point is improved by the quadratic fitting algorithm to improve the accuracy of the fitted power during RF detection input detection. Compared with the prior art, the first fitting eliminates the error caused by the power meter, and provides more accurate power for the second fitting of non-calibrated frequency points. By querying the calibration table, the redundancy and response time will not be increased. will not increase too much.

In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be evident that various modifications and changes can still be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (11)

1. A quadratic fit processing method for reducing detection power error aiming at an RF detection module is characterized by comprising the following steps:

(1) performing linear fitting on the power data of the calibration voltage points, and eliminating power errors of adjacent voltage points of the same calibration frequency point;

(2) and performing fitting calculation on two adjacent calibration point values of the non-calibration frequency points to obtain power data.

2. The method according to claim 1, wherein the step (1) specifically comprises the following steps:

(1.1) judging whether the current voltage PowInV is in a voltage range of the detector, namely judging whether a is more than the current voltage PowInV and less than f, wherein the voltage range of the detector is [ a, f ], and if so, continuing the step (1.2); otherwise, calculating corresponding power values under the conditions that the current voltage PowInV is less than a and the current voltage PowInV is greater than f;

(1.2) calculating a calibration table position interval and a voltage amount RemaindenInV exceeding a calibration voltage point;

(1.3) calculating a power value PowIndBmSim for obtaining the current voltage fitting.

3. The method of claim 2, wherein the step (1.2) of calculating the inter-calibration value is specifically:

the calibration table position interval is calculated according to the following formula:

wherein PowInV is the current voltage, StartPowInV is the starting voltage falling within the range, Step is the interval of the voltage range, and add is the cumulative number.

4. The method of claim 2, wherein the step (1.2) of calculating the amount of voltage beyond the calibration voltage point, RemainderInV, is performed by:

calculating the voltage amount RemainderInV beyond the calibration voltage point according to the following formula:

RemainderInV＝PowInV-StartPowInV-(interval-add)×Step；

wherein PowInV is the current voltage, StartPowInV is the initial voltage falling in the range, Step is the interval of the voltage range, add is the cumulative number, and interval is the position of the calibration table.

5. The method according to claim 2, wherein the step (1.3) of calculating the power value powdndbmsmim for obtaining the current voltage fit includes:

calculating a power value PowIndBmSim for obtaining current voltage fitting according to the following formula:

PowIndBm1＝CaliForm[freqLocation][interval－1]；

PowIndBm2＝CaliForm[freqLocation][interval]；

wherein Freqlocation is a calibration frequency point, interval is a voltage interval, RemainderInV is a voltage amount exceeding the calibration voltage point, Step is an interval of a voltage range, and PowIndBm1 and PowIndBm2 are power values obtained according to the two-dimensional array respectively.

6. The method according to claim 1, wherein the step (2) specifically comprises the following steps:

(2.1) if the set frequency point is a calibration frequency point, calculating a power value PowIndBmSim corresponding to the voltage; if the set frequency point is not on the calibration frequency point and the frequency point is between the calibration points F0 and F1, wherein F0 < F1, continuing the step (2.2);

(2.2) obtaining a voltage power value PowIndBmSim1 corresponding to the frequency point F0 and a voltage power value PowIndBmSim2 corresponding to the frequency point F1;

and (2.3) carrying out linear fitting to obtain a power value corresponding to the voltage under the current frequency.

7. The method according to claim 6, wherein the step (2.3) of calculating the power value corresponding to the voltage includes:

and calculating the power value corresponding to the voltage according to the following formula:

the PowIndBmSim1 is a voltage power value corresponding to the frequency point F0, the PowIndBmSim2 is a voltage power value corresponding to the frequency point F1, and Freq is a frequency value.

8. The quadratic fitting processing system for reducing the detection power error aiming at the RF detection module is characterized by comprising a power divider, a detection module and a power meter, wherein the input end of the power divider is connected with a signal source, one end of the output end of the power divider is connected with the detection module, the other end of the output end of the power divider is connected with the power meter, and the detection module calibrates a signal output by the signal source.

9. A quadratic fit processing apparatus for reducing detection power error for an RF detection module, the apparatus comprising:

a processor configured to execute computer-executable instructions;

a memory storing one or more computer-executable instructions that, when executed by the processor, perform the steps of any of claims 1 to 7 for a method of implementing a quadratic fit process for an RF detection module that reduces detection power errors.

10. A processor for implementing a quadratic fit process for reducing detection power errors for an RF detection module, wherein the processor is configured to execute computer executable instructions which, when executed by the processor, implement the steps of the quadratic fit process for reducing detection power errors for an RF detection module of any of claims 1 to 7.

11. A computer-readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method for RF detection module quadratic fit reduction of detected power error of any of claims 1 to 7.

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