CN114420666A - Chip package structure - Google Patents

Abstract

The present application discloses a chip packaging structure. The chip packaging structure includes: a substrate; a first chip layer on one side of the substrate, including one or more chips, the non-functional surfaces of the chips in the first chip layer face the substrate; The wiring layer is located on the side of the first chip layer facing away from the substrate, and is electrically connected to the functional surface of the chip of the first chip layer; the second chip layer is located on the side of the first rewiring layer facing away from the first chip layer, including One or more chips, the functional surface of the chip of the second chip layer faces the first redistribution layer and is electrically connected to the first redistribution layer; the second redistribution layer is located on the second chip layer away from the first redistribution layer. One side is electrically connected to the first redistribution layer; one end of the bonding wire is electrically connected to the second redistribution layer, and the other end is electrically connected to the substrate. The chip packaging structure provided by the present application can realize the vertical vertical stacking of three-dimensional multi-chips, save the lateral space of the substrate, and save the cost.

Description

Chip package structure

technical field

The present application relates to the field of semiconductor technology, and in particular, to a chip packaging structure.

Background technique

The descriptions in this section merely provide background information related to the disclosure in this specification and do not constitute prior art.

In the packaging industry, the horizontal arrangement of devices in the system-in-package is the simplest structure, the easiest to obtain high yield, and therefore the most widely used. However, with the increasing demand for miniaturization of packages, in order to further reduce the volume, it is necessary to stack chips or devices in a vertical direction.

3D packaging is realized by stacking chips, and the interconnection after stacking can usually be realized by wire bonding or through silicon via (TSV). TSV technology has great limitations and high cost, while wire bonding is a more traditional interconnect technology, with mature technology, low cost, and more common use.

The method of stacking chips by wire bonding is a low-cost 3D packaging solution that is relatively easy to implement and is often used in consumer-grade memory products. Commonly used lead interconnects after chip stacking usually include Step-like stack, Stack by spacer, FOW (Film on wire) and FOD (Film over die), as shown in Figure 1 and Figure 1, respectively. 2, as shown in Figure 3 and Figure 4. 1 to 4 show the positional relationship of the substrate 20 , the chip 30 , the pads 40 and the bonding wires 50 , wherein the offset stacking and the pad stacking leave the lead interconnection space by means of offsetting or arranging the pads, FOW and FOD cover the lead or device with a thick adhesive film.

However, when the staggered stacking method is applied to multiple chips, the lateral size of the product package is likely to be large. The way of FOD requires different chip sizes. The method of pad stacking and FOW requires two bonding wires to be placed on the same BondFinger, which requires a larger Bond Finger to be designed on the substrate, which cannot be satisfied by the existing substrate size. At the same time, these two solutions will increase the longitudinal size of the entire package, and the two bonding wires on the same Bond Finger will also bring reliability risks.

It should be noted that the above description of the technical background is only for the convenience of clearly and completely describing the technical solutions of the present specification, and for the convenience of understanding of those skilled in the art. It should not be assumed that the above-mentioned technical solutions are known to those skilled in the art simply because they are described in the background section of this specification.

SUMMARY OF THE INVENTION

The main technical problem to be solved by the present application is to provide a chip packaging structure, which can realize the vertical vertical stacking of three-dimensional multi-chips, save the lateral space of the substrate, and save the cost.

In order to solve the above-mentioned technical problems, a technical solution adopted in the present application is to provide a chip packaging structure, and the chip packaging structure includes:

substrate;

a first chip layer, located on one side of the substrate, the first chip layer includes one or more chips, and the non-functional surfaces of the chips of the first chip layer face the substrate;

a first redistribution layer, located on the side of the first chip layer facing away from the substrate, and the first redistribution layer is electrically connected to the functional surface of the chip of the first chip layer;

The second chip layer is located on the side of the first redistribution layer facing away from the first chip layer, the second chip layer includes one or more chips, and the functional surfaces of the chips of the second chip layer face the first redistribution layer is electrically connected to the first redistribution layer;

a second redistribution layer, located on the side of the second chip layer facing away from the first redistribution layer, the second redistribution layer is electrically connected to the first redistribution layer;

One end of the bonding wire is electrically connected to the second redistribution layer, and the other end is electrically connected to the substrate.

Further, the chip packaging structure also includes:

a first dielectric layer, located on the side of the first chip layer away from the substrate, and the first dielectric layer at least covers the side of the first chip layer facing the first redistribution layer; the first dielectric layer There is a first opening on the layer, and the position of the first opening corresponds to the pad on the chip of the first chip layer; the first redistribution layer is connected to the first chip layer through the first opening The functional surface of the chip is electrically connected.

Further, the chip packaging structure also includes:

The second dielectric layer is located on the side of the first redistribution layer away from the substrate, and the second dielectric layer covers at least the side of the first redistribution layer away from the substrate; on the second dielectric layer A second opening is provided, the position of the second opening corresponds to the pad on the chip of the second chip layer, and the first redistribution layer is connected to the chip of the second chip layer through the second opening functional surface electrical connection.

Further, the chips in the first chip layer are in one-to-one correspondence with the chips in the second chip layer to form a plurality of chip groups; wherein, at least part of the two chip pads in the chip group are in the same position, The first opening and the second opening at the positions of the two chips with the same pad position are aligned and arranged.

Further, the chip packaging structure also includes:

The third dielectric layer is located on the side of the second chip layer away from the substrate, and the third dielectric layer at least covers the side of the second chip layer away from the substrate.

Further, the third dielectric layer covers the side of the second chip layer away from the substrate and the side of the second chip layer; wherein, the third dielectric layer is located on the side of the second chip layer in the third dielectric layer Conductive holes are provided, and the second redistribution layer is electrically connected to the first redistribution layer through the conductive holes.

Further, the peripheral sides of the first dielectric layer, the second dielectric layer and the third dielectric layer are arranged in alignment.

Further, the chip packaging structure also includes:

A solder resist layer and a first pad, the solder resist layer and the first pad are located on the side of the second redistribution layer facing away from the second chip layer, and the first pad and the The second redistribution layer is electrically connected, and one end of the bonding wire is electrically connected to the first pad.

Further, the first chip layer includes at least two chips, and the second chip layer includes at least two chips.

Further, the chips of the first chip layer are aligned on a plane parallel to the surface of the substrate, the chips of the second chip layer are aligned on a plane parallel to the substrate surface, the first chips The chips of the layer and the chips of the second chip layer are aligned in a direction perpendicular to the surface of the substrate.

Different from the situation in the prior art, the beneficial effects of the present application are: the chip packaging structure provided by the embodiments of the present application, by sequentially arranging the first chip layer, the first rewiring layer, the second chip layer and the second chip layer on one side of the substrate The redistribution layer, the first redistribution layer is electrically connected to the first chip layer, the second chip layer, and the second redistribution layer respectively, which can easily realize the vertical and vertical stacking of three-dimensional multi-chips, save the lateral space of the substrate, and avoid The chip shift problem occurs because the chip position alignment accuracy is not high. The first chip layer may include one or more chips, and the second chip layer may also include one or more chips, which can reduce the overall longitudinal dimension. By electrically connecting the bonding wires drawn from the second redistribution layer of the top layer to the substrate, the bonding wires can be saved and the cost can be reduced. The chip packaging structure has relatively low requirements on equipment and environment, and the material is cheap.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

Fig. 1 is the chip packaging structure adopting the dislocation stacking method in the prior art;

FIG. 2 is a chip package structure using a pad stacking method in the prior art;

FIG. 3 is a chip package structure using a FOW stacking method in the prior art;

Fig. 4 is the chip packaging structure adopting the FOD stacking method in the prior art;

FIG. 5 is a schematic structural diagram of a chip packaging structure provided in this embodiment;

FIG. 6 is a flowchart of steps of a chip packaging method provided in this embodiment;

FIG. 7 is a schematic structural diagram of an embodiment corresponding to step S12 in FIG. 6;

FIG. 8 is a schematic structural diagram of an embodiment corresponding to step S131 in FIG. 13 ;

FIG. 9 is a schematic structural diagram of an embodiment corresponding to step S14 in FIG. 6;

FIG. 10 is a schematic structural diagram of an embodiment corresponding to step S151 in FIG. 15;

11 is a schematic structural diagram of an embodiment corresponding to step S16 in FIG. 6;

FIG. 12 is a schematic structural diagram of an embodiment corresponding to steps S18 and S110 in FIG. 6 ;

Fig. 13 is a flow chart of steps of an embodiment between step S12 and step S14 in Fig. 6;

FIG. 14 is a flow chart of steps of an embodiment of step S14 in FIG. 6;

Fig. 15 is a flow chart of steps of an embodiment between step S14 and step S16 in Fig. 6;

FIG. 16 is a flow chart of steps of an embodiment of step S16 in FIG. 6;

Fig. 17 is a flow chart of steps of an embodiment between step S16 and step S18 in Fig. 6;

FIG. 18 is a flow chart of steps of an embodiment of step S18 in FIG. 6;

FIG. 19 is a flow chart of steps of an embodiment between steps S18 and S110 in FIG. 6 .

Description of reference numbers:

1. Substrate; 2. SMD adhesive; 3. The first chip layer; 4. The first re-wiring layer; 5. The second chip layer; 6. The second re-wiring layer; 7. Bonding wire; 8. The first Dielectric layer; 9, Second dielectric layer; 10, Third dielectric layer; 11, First opening; 12, Second opening; 13, Conductive hole; 14, Solder mask; 15, First pad; 20, Substrate ; 30, chip; 40, gasket; 50, bonding wire.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening another element may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or it may be intervening with the other element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for the purpose of illustration only and do not represent the only embodiment.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are for the purpose of describing specific embodiments only, and are not intended to limit the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

See Figure 5. Embodiments of the present application provide a chip package structure, including a substrate 1 , a first chip layer 3 , a first redistribution layer 4 , a second chip layer 5 , a second redistribution layer 6 and bonding wires 7 .

The first chip layer 3 is located on one side of the substrate 1 , and the first chip layer 3 includes one or more chips. The non-functional surfaces of the chips of the first chip layer 3 face the substrate 1 . The first redistribution layer 4 is located on the side of the first chip layer 3 facing away from the substrate 1 , and the first redistribution layer 4 is electrically connected to the functional surface of the chip of the first chip layer 3 . The second chip layer 5 is located on the side of the first redistribution layer 4 facing away from the first chip layer 3 . The second chip layer 5 includes one or more chips. The functional surfaces of the chips of the second chip layer 5 face the first redistribution layer 4 and are electrically connected to the first redistribution layer 4 . The second redistribution layer 6 is located on the side of the second chip layer 5 facing away from the first redistribution layer 4 , and the second redistribution layer 6 is electrically connected to the first redistribution layer 4 . One end of the bonding wire 7 is electrically connected to the second redistribution layer 6 , and the other end is electrically connected to the substrate 1 .

In the chip package structure provided by the embodiment of the present application, the first chip layer 3 , the first redistribution layer 4 , the second chip layer 5 and the second redistribution layer 6 are sequentially arranged on one side of the substrate 1 , and the first redistribution layer 4 It is electrically connected to the first chip layer 3, the second chip layer 5, and the second redistribution layer 6 respectively, which can easily realize the vertical vertical stacking of three-dimensional multi-chips, save the lateral space of the substrate 1, and at the same time can avoid the occurrence of misalignment of the chip positions. The chip shift problem caused by the low quasi-precision. The first chip layer 3 may include one or more chips, and the second chip layer 5 may also include one or more chips, which can reduce the overall longitudinal dimension. By electrically connecting the bonding wires 7 drawn out from the second redistribution layer 6 of the top layer to the substrate 1 , the bonding wires 7 can be saved and the cost can be reduced. The chip packaging structure has relatively low requirements on equipment and environment, and the material is cheap.

In the present embodiment, the chips of the first chip layer 3 may be mounted on the substrate 1 by means of dispensing patches, that is, a patch adhesive 2 is provided between the first chip layer 3 and the substrate 1 . When the first chip layer 3 includes a plurality of chips, theoretically, the chips can be infinitely close to each other.

In this embodiment, the chip package structure may further include a first dielectric layer 8 on the side of the first chip layer 3 away from the substrate 1 . The first dielectric layer 8 at least covers the side of the first chip layer 3 facing the first redistribution layer 4 . Preferably, the first dielectric layer 8 can also cover the side of the first chip layer 3 , and the peripheral side of the first dielectric layer 8 is connected to the substrate 1 . At this time, the first dielectric layer 8 connects the first chip layer 3 and the first chip The glue between the layer 3 and the substrate 1 is completely wrapped, which can protect the chips of the first chip layer 3 . The surface of the first dielectric layer 8 away from the first chip layer 3 is flat, which facilitates the subsequent formation of the first redistribution layer 4 . The first dielectric layer 8 is an insulating layer, and its material can be selected from polyimide (PI).

Specifically, the first dielectric layer 8 is provided with a first opening 11 , and the position of the first opening 11 corresponds to the pad on the chip of the first chip layer 3 . The shape of the first opening 11 may be consistent with the pad on the chip of the first chip layer 3 . The first opening 11 may be formed by laser drilling. The laser drilling can precisely locate the drilling position and depth of the first opening 11 . The first redistribution layer 4 is electrically connected to the functional surface of the chip of the first chip layer 3 through the first opening 11 . Among them, the first opening 11 can be electroless-plated and then electroplated with copper, that is, a first conductive member can be formed in the first opening 11, so that the first opening 11 can pass through the first conductive member and the chip of the first chip layer 3. functional surface electrical connection.

In this embodiment, while electroplating the first opening 11 , a first metal layer may be formed on the surface of the first dielectric layer 8 away from the first chip layer 3 , and the first conductive member is electrically connected to the first metal layer . The first metal layer is etched to form an RDL (Re-Distribution Layer), which constitutes the first redistribution layer 4 . Wherein, the first metal layer is preferably a metal copper layer.

In this embodiment, the chip package structure may further include a second dielectric layer 9 on the side of the first redistribution layer 4 away from the substrate 1 . The second dielectric layer 9 covers at least the side of the first redistribution layer 4 facing away from the substrate 1 . Preferably, the second dielectric layer 9 can also cover the side of the first redistribution layer 4, and the peripheral side of the second dielectric layer 9 is connected to the first dielectric layer 8. At this time, the second dielectric layer 9 connects the first redistribution layer 4 is completely wrapped and can protect the first redistribution layer 4. The surface of the second dielectric layer 9 away from the first redistribution layer 4 is flat, which facilitates the subsequent mounting of the second chip layer 5 . The second dielectric layer 9 is an insulating layer, and its material can be selected from polyimide (PI).

Specifically, the second dielectric layer 9 is provided with a second opening 12 , and the position of the second opening 12 corresponds to the pad on the chip of the second chip layer 5 . The shape of the second opening 12 may be consistent with the pad on the chip of the second chip layer 5 . The second opening 12 may be formed by laser drilling. The laser drilling can precisely locate the drilling position and depth of the second opening 12 . The first redistribution layer 4 is electrically connected to the functional surface of the chip of the second chip layer 5 through the second opening 12 . Wherein, the second opening 12 can be electroless-plated and then plugged with copper, that is, a second conductive member can be formed in the second opening 12, so that the second opening 12 can pass through the second conductive member and the chip of the second chip layer 5 functional surface electrical connection.

In this embodiment, conductive glue may be applied to the pads of the chips of the second chip layer 5 , and the pads of the chips of the second chip layer 5 may be aligned with the second openings 12 for installation, thereby forming the second chip layer 5 . The amount of the conductive glue can be accurately calculated according to the condition of the second opening 12 . After high temperature reflow, the second chip layer 5 can be electrically connected to the first redistribution layer 4 and the first chip layer 3 .

Specifically, the chips in the first chip layer 3 and the chips in the second chip layer 5 may be the same or different, which is not limited in the present application. In order to further reduce the cost, the first chip layer 3 includes at least two chips, and the second chip layer 5 includes at least two chips.

Preferably, on a plane parallel to the surface of the substrate 1 , that is, the horizontal plane in FIG. 5 , the chips of the first chip layer 3 are aligned and the chips of the second chip layer 5 are aligned. The surface of the substrate 1 here refers to the surface of the substrate 1 on which the first chip layer 3 is mounted. In the direction perpendicular to the surface of the substrate 1, that is, in the vertical direction in FIG. 5, the chips in the first chip layer 3 and the chips in the second chip layer 5 are aligned, and the chips in the first chip layer 3 and the chips in the The chips in the two chip layers 5 are in one-to-one correspondence to form a plurality of chip groups. When the chips in the first chip layer 3 and the chips in the second chip layer 5 are the same, the pads of the two chips in the chip group are in the same position, and the first opening at the position where the two chips in the chip group are located 11 and the second opening 12 are aligned.

In this embodiment, the chip package structure may further include a third dielectric layer 10 on the side of the second chip layer 5 away from the substrate 1 . The third dielectric layer 10 covers at least the side of the second chip layer 5 away from the substrate 1 . Preferably, the third dielectric layer 10 can also cover the side of the second chip layer 5 , and the peripheral side of the third dielectric layer 10 is connected to the second dielectric layer 9 . At this time, the third dielectric layer 10 completely covers the second chip layer 5 The package can protect the chips of the second chip layer 5 . The surface of the third dielectric layer 10 facing away from the second chip layer 5 is flat, which facilitates the subsequent formation of the second redistribution layer 6 . The third dielectric layer 10 is an insulating layer, and its material can be selected from polyimide (PI).

Specifically, a conductive hole 13 is provided in the third dielectric layer 10 on the side of the second chip layer 5 , and the second redistribution layer 6 is electrically connected to the first redistribution layer 4 through the conductive hole 13 . The conductive holes 13 can be formed by laser drilling. The laser drilling can precisely locate the position and depth of the conductive hole 13 . Among them, the conductive holes 13 can be electroless-plated and then plugged with copper to make them conductive.

In this embodiment, while electroplating the conductive holes 13 , a second metal layer may be formed on the surface of the third dielectric layer 10 away from the second chip layer 5 , and the conductive holes 13 are electrically connected to the second metal layer. The RDL can be formed by etching the second metal layer to form the second redistribution layer 6 . Wherein, the second metal layer is preferably a metal copper layer.

Preferably, the peripheral sides of the first dielectric layer 8 , the second dielectric layer 9 and the third dielectric layer 10 are aligned, so that the chip package structure is more stable.

In this embodiment, the chip package structure may further include a solder resist layer 14 and a first pad 15 on the side of the second redistribution layer 6 facing away from the second chip layer 5 . The first pad 15 is electrically connected to the second redistribution layer 6 , and one end of the bonding wire 7 is electrically connected to the first pad 15 .

It should be noted that the chip packaging structure in FIG. 5 is a double-layer multi-chip Fan-out packaging structure, and this embodiment does not make a unique limitation on the number of chip layers. That is to say, the chip packaging structure can be provided with multiple chip layers, and it is only necessary to continue to provide a third chip layer on the side of the second redistribution layer 6 away from the substrate 1, so that the chip of the third chip layer is electrically connected to the second redistribution layer 6. Then, a third rewiring layer is arranged on the side of the third chip layer away from the substrate 1, so that the third rewiring layer and the second rewiring layer 6 are electrically connected, and then stacked up in the same way to continue to form multi-layer chip layers and In the redistribution layer, the substrate 1 and the redistribution layer on the top layer are finally electrically connected by bonding wires 7 .

See Figure 6. Embodiments of the present application provide a chip packaging method, including the following steps:

Step S10: providing the substrate 1;

Step S12 : forming a first chip layer 3 on one side of the substrate 1 , the first chip layer 3 includes one or more chips, and the non-functional surfaces of the chips of the first chip layer 3 face the substrate 1 ;

Step S14: forming a first redistribution layer 4 on the side of the first chip layer 3 facing away from the substrate 1, and the first redistribution layer 4 is electrically connected to the functional surface of the chip of the first chip layer 3;

Step S16 : forming a second chip layer 5 on the side of the first redistribution layer 4 facing away from the first chip layer 3 , the second chip layer 5 includes one or more chips, and the functional surfaces of the chips of the second chip layer 5 face The first redistribution layer 4 is electrically connected to the first redistribution layer 4;

Step S18: forming a second redistribution layer 6 on the side of the second chip layer 5 facing away from the first redistribution layer 4, and the second redistribution layer 6 is electrically connected to the first redistribution layer 4;

Step S110 : the second redistribution layer 6 and the substrate 1 are electrically connected by the bonding wires 7 .

In the chip packaging method provided by the embodiment of the present application, the first chip layer 3 , the first redistribution layer 4 , the second chip layer 5 and the second redistribution layer 6 are sequentially arranged on one side of the substrate 1 , and the first redistribution layer 4 It is electrically connected to the first chip layer 3, the second chip layer 5, and the second redistribution layer 6 respectively, which can easily realize the vertical vertical stacking of three-dimensional multi-chips, save the lateral space of the substrate 1, and at the same time can avoid the occurrence of misalignment of the chip positions. The chip shift problem caused by the low quasi-precision. The first chip layer 3 may include one or more chips, and the second chip layer 5 may also include one or more chips, which can reduce the overall longitudinal dimension. By electrically connecting the bonding wires 7 drawn out from the second redistribution layer 6 of the top layer to the substrate 1 , the bonding wires 7 can be saved and the cost can be reduced. The chip packaging method has relatively low requirements on equipment, environment, etc., and the price of materials is cheap.

In step S12 , as shown in FIG. 7 , the chips of the first chip layer 3 can be mounted on the substrate 1 by dispensing a patch, that is, a patch adhesive 2 is provided between the first chip layer 3 and the substrate 1 . . When the first chip layer 3 includes a plurality of chips, theoretically, the chips can be infinitely close to each other.

As shown in FIG. 13, after step S12 and before step S14, the following steps may also be included:

Step S131 : forming a first dielectric layer 8 on the side of the first chip layer 3 away from the substrate 1 , and the first dielectric layer 8 covers at least the side of the first chip layer 3 facing the first redistribution layer 4 ;

Step S132 : a first opening 11 is formed on the first dielectric layer 8 , and the position of the first opening 11 corresponds to the pad on the chip of the first chip layer 3 .

In step S131 , as shown in FIG. 8 , the first dielectric layer 8 can also cover the side surface of the first chip layer 3 , and the peripheral side of the first dielectric layer 8 is connected to the substrate 1 . At this time, the first dielectric layer 8 completely wraps the first chip layer 3 and the glue between the first chip layer 3 and the substrate 1 , which can protect the chips of the first chip layer 3 . The surface of the first dielectric layer 8 away from the first chip layer 3 is kept flat to facilitate the subsequent formation of the first redistribution layer 4 . The first dielectric layer 8 is an insulating layer, and its material can be selected from polyimide (PI).

In step S132 , as shown in FIG. 9 , the shape of the first opening 11 may be consistent with the pad on the chip of the first chip layer 3 . The first opening 11 may be formed by laser drilling. The laser drilling can precisely locate the drilling position and depth of the first opening 11 .

In step S14, as shown in FIG. 14 and FIG. 9, the step of forming the first redistribution layer 4 may include:

Step S141 : forming a first conductive member in the first opening 11 to electrically connect the first conductive member to the functional surface of the chip of the first chip layer 3 ;

Step S142: forming a first metal layer on the surface of the first dielectric layer 8 away from the first chip layer 3, and the first conductive member is electrically connected to the first metal layer;

Step S143 : etching the first metal layer to form the first redistribution layer 4 .

In step S141 , the first conductive member is formed in the first opening 11 , which can be achieved by electroless plating on the first opening 11 and then copper electroplating, so that the first opening 11 can pass through the first conductive member and the first chip. The functional surfaces of the chips of layer 3 are electrically connected.

In step S142 , the formation of the first metal layer may be performed simultaneously with the electroplating of the first opening 11 . The first conductive member is electrically connected to the first metal layer. Wherein, the first metal layer is preferably a metal copper layer.

In step S143 , the first metal layer is etched to form an RDL (Re-Distribution Layer), which constitutes the first redistribution layer 4 . The first redistribution layer 4 is electrically connected to the functional surface of the chip of the first chip layer 3 through the first opening 11 .

As shown in FIG. 15 , after step S14 and before step S16, the following steps may also be included:

Step S151 : forming a second dielectric layer 9 on the side of the first redistribution layer 4 away from the substrate 1 , and the second dielectric layer 9 covers at least the side of the first redistribution layer 4 away from the substrate 1 ;

Step S152 : opening a second opening 12 on the second dielectric layer 9 , and the position of the second opening 12 corresponds to the pad on the chip of the second chip layer 5 ;

Step S153 : forming a second conductive member in the second opening 12 , and the second conductive member is electrically connected to the first redistribution layer 4 .

In step S151 , as shown in FIG. 10 , the second dielectric layer 9 can also cover the side surface of the first redistribution layer 4 , and the peripheral side of the second dielectric layer 9 is connected to the first dielectric layer 8 . The dielectric layer 9 completely wraps the first redistribution layer 4 and can protect the first redistribution layer 4 . The surface of the second dielectric layer 9 away from the first redistribution layer 4 is flattened, so as to facilitate the subsequent mounting of the second chip layer 5 . The second dielectric layer 9 is an insulating layer, and its material can be selected from polyimide (PI).

In step S152 , as shown in FIG. 11 , the shape of the second opening 12 may be consistent with the pad on the chip of the second chip layer 5 . The second opening 12 may be formed by laser drilling. The laser drilling can precisely locate the drilling position and depth of the second opening 12 .

In step S153, a second conductive member is formed in the second opening 12, which can be realized by electroless plating on the second opening 12 and then copper electroplating, so that the second opening 12 can pass through the second conductive member and the second chip The functional surfaces of the chips of layer 5 are electrically connected. The first redistribution layer 4 can be electrically connected to the functional surface of the chip of the second chip layer 5 through the second opening 12 .

In step S16, as shown in FIG. 16 and FIG. 11, the step of forming the second chip layer 5 may include:

Step S161: brushing conductive glue on the pads of the chips of the second chip layer 5;

Step S162 : align the pads of the chips of the second chip layer 5 with the second openings 12 to mount, and the second conductive members are electrically connected to the functional surfaces of the chips of the second chip layer 5 .

In step S161 , the amount of conductive glue can be accurately calculated according to the condition of the second opening 12 . After step S162 , after high temperature reflow, the second chip layer 5 can be electrically connected to the first redistribution layer 4 and the first chip layer 3 .

Specifically, the chips in the first chip layer 3 and the chips in the second chip layer 5 may be the same or different, which is not limited in the present application. In order to further reduce the cost, the first chip layer 3 includes at least two chips, and the second chip layer 5 includes at least two chips.

Preferably, on a plane parallel to the surface of the substrate 1 , that is, the horizontal plane in FIG. 11 , the chips of the first chip layer 3 are aligned and the chips of the second chip layer 5 are aligned. The surface of the substrate 1 here refers to the surface of the substrate 1 on which the first chip layer 3 is mounted. In the direction perpendicular to the surface of the substrate 1, that is, the vertical direction in FIG. 11, the chips of the first chip layer 3 and the chips of the second chip layer 5 are aligned, and the chips in the first chip layer 3 and the chips of the first chip layer 3 are aligned with The chips in the two chip layers 5 are in one-to-one correspondence to form a plurality of chip groups. When the chips in the first chip layer 3 and the chips in the second chip layer 5 are the same, the pads of the two chips in the chip group are in the same position, and the first opening at the position where the two chips in the chip group are located 11 and the second opening 12 are aligned.

As shown in FIG. 17 , after step S16 and before step S18, the following steps may also be included:

Step S171 : forming a third dielectric layer 10 on the side of the second chip layer 5 away from the substrate 1 , and the third dielectric layer 10 covers at least the side of the second chip layer 5 away from the substrate 1 .

In step S171, as shown in FIG. 12, the third dielectric layer 10 can also cover the side surface of the second chip layer 5, and the peripheral side of the third dielectric layer 10 is connected to the second dielectric layer 9. At this time, the third dielectric layer The layer 10 completely wraps the second chip layer 5 and can protect the chips of the second chip layer 5 . The surface of the third dielectric layer 10 facing away from the second chip layer 5 is flattened, so as to facilitate the subsequent formation of the second redistribution layer 6 . The third dielectric layer 10 is an insulating layer, and its material can be selected from polyimide (PI).

As shown in Figure 17, after step S171 and before step S18, it also includes:

Step S172 : a conductive hole 13 is provided in the third dielectric layer 10 on the side of the second chip layer 5 , and the conductive hole 13 is electrically connected to the first redistribution layer 4 .

In step S172, the conductive holes 13 may be formed by laser drilling. The laser drilling can precisely locate the position and depth of the conductive hole 13 . Among them, the conductive holes 13 can be electroless-plated and then plugged with copper to make them conductive.

In step S18, as shown in FIG. 18 and FIG. 12, the step of forming the second redistribution layer 6 may include:

Step S181 : forming a second metal layer on the surface of the third dielectric layer 10 away from the second chip layer 5 , and the conductive holes 13 are electrically connected to the second metal layer;

Step S182 : etching the second metal layer to form the second redistribution layer 6 .

In step S181 , the formation of the second metal layer may be performed simultaneously with the electroplating of the conductive holes 13 . Wherein, the second metal layer is preferably a metal copper layer.

In step S182 , the RDL can be formed by etching the second metal layer to form the second redistribution layer 6 . The second redistribution layer 6 is electrically connected to the first redistribution layer 4 through the conductive holes 13 .

Preferably, the peripheral sides of the first dielectric layer 8 , the second dielectric layer 9 and the third dielectric layer 10 are aligned, so that the chip package structure is more stable.

As shown in FIG. 19 and FIG. 12 , after step S18 and before step S110, the following steps may also be included:

Step S19 : forming a solder resist layer 14 and a first pad 15 on the side of the second redistribution layer 6 facing away from the second chip layer 5 , the first pad 15 is electrically connected to the second redistribution layer 6 , and the bonding wire One end of 7 is electrically connected to the first pad 15 .

It should be noted that the chip packaging structure in FIG. 5 is a double-layer multi-chip Fan-out packaging structure, and this embodiment does not make a unique limitation on the number of chip layers. That is to say, the chip packaging structure can be provided with multiple chip layers, and it is only necessary to continue to provide a third chip layer on the side of the second redistribution layer 6 away from the substrate 1, so that the chip of the third chip layer is electrically connected to the second redistribution layer 6. Then, a third rewiring layer is arranged on the side of the third chip layer away from the substrate 1, so that the third rewiring layer and the second rewiring layer 6 are electrically connected, and then stacked up in the same way to continue to form multi-layer chip layers and In the redistribution layer, the substrate 1 and the redistribution layer on the top layer are finally electrically connected by bonding wires 7 .

It should be noted that in the description of this specification, the terms "first", "second", etc. are only used for the purpose of description and to distinguish similar objects, and there is no sequence between the two, nor can they be understood as indicating or imply relative importance. Also, in the description of this specification, unless otherwise specified, "plurality" means two or more.

Use of the terms "comprising" or "comprising" to describe combinations of elements, ingredients, components or steps herein also contemplates embodiments consisting essentially of those elements, ingredients, components or steps. By use of the term "may" herein, it is intended to indicate that "may" include any described attributes that are optional.

A plurality of elements, components, components or steps can be provided by a single integrated element, component, component or step. Alternatively, a single integrated element, component, component or step may be divided into separate multiple elements, components, components or steps. The disclosure of "a" or "an" used to describe an element, ingredient, part or step is not intended to exclude other elements, ingredients, parts or steps.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. A chip package structure, comprising:

a substrate;

a first chip layer located on one side of the substrate, the first chip layer including one or more chips, a non-functional side of the chips of the first chip layer facing the substrate;

the first rewiring layer is positioned on one side, back to the substrate, of the first chip layer and is electrically connected with the functional surface of the chip of the first chip layer;

a second chip layer located on a side of the first redistribution layer opposite to the first chip layer, the second chip layer including one or more chips, functional surfaces of the chips of the second chip layer facing the first redistribution layer and electrically connected to the first redistribution layer;

a second redistribution layer on a side of the second chip layer opposite the first redistribution layer, the second redistribution layer electrically connected to the first redistribution layer;

and one end of the bonding wire is electrically connected with the second rewiring layer, and the other end of the bonding wire is electrically connected with the substrate.

2. The chip package structure according to claim 1, further comprising:

the first dielectric layer is positioned on one side, away from the substrate, of the first chip layer, and at least covers one side, facing the first rewiring layer, of the first chip layer; a first opening is formed in the first medium layer, and the position of the first opening corresponds to a bonding pad on a chip of the first chip layer; the first redistribution layer is electrically connected with the functional surface of the chip of the first chip layer through the first opening.

3. The chip package structure according to claim 2, further comprising:

the second dielectric layer is positioned on one side, away from the substrate, of the first rewiring layer, and at least covers one side, away from the substrate, of the first rewiring layer; and a second opening is arranged on the second medium layer, the position of the second opening corresponds to the bonding pad on the chip of the second chip layer, and the first rewiring layer is electrically connected with the functional surface of the chip of the second chip layer through the second opening.

4. The chip package structure according to claim 3,

the chips in the first chip layer and the chips in the second chip layer correspond to each other one by one to form a plurality of chip groups; the bonding pads of at least two chips in part of the chip set are in the same position, and the first opening and the second opening at the positions where the two chips in the same bonding pad position are located are arranged in an aligned manner.

5. The chip package structure according to claim 3, further comprising:

and the third dielectric layer is positioned on one side, away from the substrate, of the second chip layer, and at least covers one side, away from the substrate, of the second chip layer.

6. The chip package structure according to claim 5,

the third dielectric layer covers one side of the second chip layer, which is far away from the substrate, and the side face of the second chip layer; and the third dielectric layer positioned on the side surface of the second chip layer is internally provided with a conductive hole, and the second rewiring layer is electrically connected with the first rewiring layer through the conductive hole.

7. The chip package structure according to claim 5, wherein peripheral sides of the first dielectric layer, the second dielectric layer, and the third dielectric layer are aligned.

8. The chip package structure according to claim 1, further comprising:

the second rewiring layer is arranged on the second chip layer, the solder mask layer and the first bonding pad are located on one side, back to the second chip layer, of the second rewiring layer, the first bonding pad is electrically connected with the second rewiring layer, and one end of the bonding wire is electrically connected with the first bonding pad.

9. The chip package structure according to claim 1, wherein the first chip layer comprises at least two chips and the second chip layer comprises at least two chips.

10. The chip package structure according to claim 9, wherein the chips of the first chip layer are aligned in a plane parallel to the substrate surface, the chips of the second chip layer are aligned in a plane parallel to the substrate surface, and the chips of the first chip layer and the chips of the second chip layer are aligned in a direction perpendicular to the substrate surface.

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