CN114420661B - Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment - Google Patents

Abstract

The integrated circuit packaging structure comprises a first substrate, a ball grid array, an integrated circuit component and a first capacitor, wherein the first capacitor is connected with the first substrate through a bonding pad and is connected with at least two contact solder balls through interconnection wiring on the first substrate to realize electric connection with the integrated circuit component, so that the first capacitor can provide energy for a core power supply of the integrated circuit component when the core power supply fluctuates, the fluctuation of the core power supply is reduced or eliminated, and the performance of the integrated circuit packaging structure is optimized. In addition, the arrangement density of a plurality of contact solder balls included in the ball grid array in the first area of the first substrate is smaller than that in the second area, so that more space is provided for arranging the first capacitor in the first area, the arrangement quantity of the first capacitor is increased, and the first capacitor can better exert the voltage stabilizing function on the core power supply.

Description

Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment

technical field

This specification relates to the field of semiconductor technology, and more particularly, to an integrated circuit packaging structure, a packaging method, an integrated circuit system, and an electronic device.

Background technique

With the continuous development of semiconductor technology, the number of components accommodated on a single integrated circuit is increasing, which puts forward higher requirements for the packaging structure of the integrated circuit.

Among all kinds of integrated circuit packaging structures, the Ball Grid Array (BGA) packaging structure has the characteristics of smaller volume, better heat dissipation performance and electrical performance, etc. LSI) or very large scale integrated circuit (Very Large Scale Integration Circuit, VLSI) better adaptability.

However, with the further improvement of integrated circuit integration, it is necessary to optimize the performance of the integrated circuit packaging structure.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present specification aim to provide an integrated circuit packaging structure, a packaging method, an integrated circuit system, and an electronic device, so as to achieve the purpose of optimizing the performance of the integrated circuit packaging structure.

In a first aspect, an integrated circuit packaging structure is provided, including:

a first substrate including a first side and a second side opposite the first side, the first side including a first region and a second region surrounding the first region;

A ball grid array, the ball grid array includes a plurality of contact solder balls distributed on the first side, and the density of the contact solder balls distributed in the first area is smaller than that of the contact solder balls distributed in the second area Density of contact solder balls;

an integrated circuit component located on the second side;

a first capacitor, the first capacitor is disposed in the first region, and the first capacitor is connected to at least two of the contact solder balls to be electrically connected to the integrated circuit component.

The first capacitor is connected to at least two contact solder balls (specifically, the first capacitor is connected to the first substrate through the pad, and is connected to the at least two contact solder balls through the traces on the first substrate), so as to realize the connection with the first capacitor. The electrical connection of the integrated circuit components enables the first capacitor to provide energy for the core power supply when the core power supply of the integrated circuit component fluctuates, reduces or eliminates the fluctuation of the core power supply, and optimizes the performance of the integrated circuit packaging structure. In addition, the arrangement density of the plurality of contact solder balls included in the ball grid array in the first area of the first substrate is smaller than that in the second area, so that there is more space in the first area to arrange the first area. The capacitor increases the settable number of the first capacitor, so that the first capacitor can better exert the function of regulating the core power supply.

In a feasible implementation manner, the value of the ratio of the area of the first region to the sum of the areas of the first region and the second region ranges from 10% to 20%.

Through research, the inventor found that the ratio of the area of the first region to the sum of the areas of the first region and the second region is limited between 10% and 20%, and a certain area can be provided for setting the first capacitor, so as to satisfy the On the basis of improving the stability of the core power supply, the warpage of the substrate caused by the soldering stress of the contacting solder balls after the first substrate is packaged with other packaging substrates is avoided.

In a feasible implementation manner, the density of the contact solder balls distributed in the first region is zero.

Since the first area is not used for arranging contact solder balls, a larger space is provided for the first capacitor. First, the convenience of arranging the first capacitor is improved. Second, because there are no contact solder balls in the first region, the possibility that the first capacitor is in wrong contact with the adjacent contact solder balls during the setting process is reduced to a certain extent, and the fabrication yield of the integrated circuit packaging structure is improved. Third, since all the first areas are used to set the first capacitors, a larger number of first capacitors can be set in the first area of the same size, increasing the capacitance as the core power storage capacitor, and the larger the capacitance. The energy storage capacitor can provide a better voltage regulation function for the core power supply of the integrated circuit components and improve the system stability.

In a possible implementation, the integrated circuit component includes a core power supply;

The orthographic projection of the first region on the first side at least partially overlaps the orthographic projection of the core power supply on the first side.

In this way, the decoupling path between the first capacitor (especially the first capacitor in the region overlapping with the core power supply) and the core power supply disposed in the overlapping region is relatively short, which is beneficial to improve the first capacitor in the overlapping region. The capacitance filtering effect of the capacitor ensures that the first capacitor has a good voltage stabilization effect.

In a feasible implementation manner, the orthographic projection of the first region on the first side coincides with the orthographic projection of the core power supply on the first side.

In this way, the distance between the first capacitor arranged in the first area and the core power supply is relatively small, that is, the decoupling paths of the first capacitor arranged in the first area are relatively short, which is beneficial to improve the filtering of the first capacitor. Therefore, it is ensured that the first capacitor can play a good voltage stabilization effect.

In a feasible implementation manner, the number of the first capacitors is multiple, the multiple first capacitors are arranged in the first region in an array manner, and the first capacitors in the same row are arranged in an array manner. facing the same.

Usually, the first capacitor includes a capacitor body, a first pole and a second pole. Since the interconnection trace connecting the first pole cannot cross the interconnection trace connecting the second pole, so as to avoid short-circuiting the first capacitor, the thus-configured No. A capacitor enables the interconnection lines connected to the first pole to be arranged on one side of the first capacitor, and the interconnection lines connected to the second pole can be arranged on the other side of the first capacitor, which is beneficial to simplify the design of interconnection lines Difficulty, reducing the risk of short-circuiting the first capacitor.

In a feasible implementation manner, the orientation of the first capacitors in the same row is perpendicular to the row direction, and the first electrodes of the first capacitors in the same row are in contact with the solder balls in a row of the ball grid array. at least one of the contact solder ball connections.

The second poles of the first capacitors in the same row are connected to at least one contact solder ball in another row of the ball grid array.

Also, since the interconnecting traces connecting the first pole cannot cross the interconnecting traces connecting the second pole, so as to avoid short-circuiting the first capacitor, the contact solder balls connecting the first pole and the second pole are arranged in different rows. It is beneficial to reduce the risk of short circuit between the interconnection line connecting the first pole and the interconnection line connecting to the second pole, simplify the design difficulty of the interconnection line, and reduce the risk of short circuit of the first capacitor.

In a feasible implementation manner, the first substrate further includes: a recessed area located in the first region.

The plurality of capacitors are disposed in the recessed area.

Disposing the first capacitor in the recessed area helps to increase the space of the first capacitor in the longitudinal direction (the direction perpendicular to the first side and the second side of the first substrate), so that when the first capacitor is placed on the first substrate, The larger operating space is beneficial to increase the success rate of placing the first capacitor, thereby increasing the fabrication yield of the entire integrated circuit package structure.

In a feasible implementation manner, the height of the first capacitor is smaller than the height of the contact solder ball.

Since the ball grid array also needs to be connected to a printed circuit board (Printed Circuit Boards, PCB), the first capacitor also needs to have a low height, and the height of the first capacitor is smaller than the height of the contact solder balls to ensure the contact solder balls. Good electrical contact with other packaging substrates avoids the problem of abnormal electrical contact between the contact solder balls and other packaging substrates due to excessively high first capacitance.

In a second aspect, an integrated circuit packaging structure is provided, including:

A first substrate, the first substrate includes a package side and a circuit side opposite the package side, the circuit side is used for arranging integrated circuit components, the package side includes a decoupling area and a circuit side surrounding the decoupling area The welding area, the decoupling area is used to provide a space for the arrangement of the first capacitor, and the first capacitor is used to reduce or eliminate the fluctuation of the core power supply of the integrated circuit component.

A special decoupling area is provided on the package side of the first substrate to provide a corresponding setting space for the first capacitor electrically connected to the integrated circuit component, so that the first capacitor can eliminate or reduce the fluctuation of the core power supply of the integrated circuit component. Under the premise of reducing the difficulty of setting the first capacitor, the dedicated decoupling area is also conducive to placing a relatively large number of first capacitors, which is conducive to optimizing the ability of the first capacitor in the decoupling area to suppress fluctuations in the core power supply.

In a third aspect, an integrated circuit system is provided, including: the integrated circuit packaging structure according to any one of the above, wherein the integrated circuit packaging structure includes a ball grid array;

A printed circuit board including a third side and a fourth side, the third side including at least one coupling region, the coupling region being coupled to a ball grid array of the integrated circuit package structure.

A second capacitor, the second capacitor is disposed on the fourth side, the orthographic projection of the second capacitor on the fourth side and the orthographic projection of the contact balls of the ball grid array on the fourth side do not overlap each other.

When the core power supply fluctuates, similar to the first capacitor, the second capacitor can provide energy for the core power supply, reduce the fluctuation of the core power supply voltage, and improve the stability of the core power supply voltage.

In a feasible implementation manner, the package size of the first capacitor is smaller than the package size of the second capacitor, or the capacity of the first capacitor of the integrated circuit package structure is smaller than the capacity of the second capacitor.

When the package size of the first capacitor is smaller than the package size of the second capacitor, and the capacity of the first capacitor is smaller than the capacity of the second capacitor, the first capacitor can provide a better core power supply at a medium frequency (for example, 100MHz) or a high frequency The second capacitor can provide a better energy supplement for the core power supply at low frequencies. The first capacitor and the second capacitor complement each other to ensure that the core power supply operates in the full frequency range (especially at low and medium frequencies). segment) can run stably and improve system stability.

In a feasible implementation manner, the fourth side includes: a third area, and the orthographic projection of the third area on the first side is in the same position as the area where the first capacitor is arranged in the integrated circuit package structure. The orthographic projections of the first side of the first substrate of the integrated circuit package structure at least partially overlap.

The second capacitor is disposed in the third region.

Since the density of contact solder balls in the setting area of the first capacitor (for example, the first area) is small or not used for setting contact solder balls, the degree of freedom of setting the second capacitor in the overlapping area can be increased, without considering the relationship between the second capacitor and the contact solder ball. positional relationship between the balls.

In a feasible implementation manner, the number of the second capacitors is multiple, and the multiple second capacitors are arranged in an array.

In a row of the second capacitors, the direction of the second capacitors is parallel to the row direction, and the first pole of the second capacitors faces a predetermined side, and the predetermined side includes the middle of the outer edge of the third region. A vertical edge closest to the second capacitor.

The first poles of the second capacitors set in this way are all facing the "outside" (that is, toward the preset side), so that the first poles connected to the core power supply are oriented in the same direction, which is beneficial to avoid the connection between the first pole and the second pole. The lines are crossed, which simplifies the design of the lines on the fourth side, and the first poles all face the outside, which is beneficial to increase the layout space of the lines connected to the first poles, reduce the design difficulty, and improve the fabrication yield.

In a feasible implementation manner, the integrated circuit package structure further includes: a first power supply terminal, a second power supply terminal and a third capacitor.

The third side includes at least two of the coupling regions, the third capacitor, the first power supply terminal and the second power supply terminal are arranged between adjacent coupling regions, and the third capacitor is The first pole is connected to the first power supply terminal, and the second pole of the third capacitor is connected to the second power supply terminal.

The third capacitor is arranged on the third side of the printed circuit board, so that the third capacitor can provide energy for the system power supply when the system power supply signal fluctuates, especially for low frequency power supply signals (for example, power signals less than or equal to 30MHz) ), the third capacitor can play a better decoupling role and improve the stability of the system power supply.

In a fourth aspect, an integrated circuit packaging method is provided, including:

providing a first substrate including a first side and a second side opposite the first side, the first side including a first region and a second region surrounding the first region;

forming integrated circuit components on the second side;

A ball grid array is formed on the first side, the ball grid array includes a plurality of contact solder balls, and the density of the contact solder balls distributed in the first region is less than that of the contact solder balls distributed in the second region The density of solder balls;

A first capacitor is formed in the first region, and the first capacitor is connected to at least two of the contact solder balls for electrical connection with the integrated circuit component.

In a fifth aspect, an electronic device is provided, including the integrated circuit system according to any one of the above.

In a sixth aspect, a server chip is provided, including the integrated circuit system described in any one of the above.

The integrated circuit package structure provided by the embodiments of this specification includes a first substrate, a ball grid array, an integrated circuit component, and a first capacitor, wherein the first capacitor is connected to the first substrate through a pad, and at the same time passes through the traces on the first substrate Connect with at least two contact solder balls to realize the electrical connection between the first capacitor and the integrated circuit component, so that the first capacitor can provide energy for the core power supply when the core power supply of the integrated circuit component fluctuates, and reduce or eliminate the fluctuation of the core power supply , optimizes the performance of the integrated circuit package structure.

In addition, the arrangement density of the plurality of contact solder balls included in the ball grid array in the first area of the first substrate is smaller than that in the second area, so that there is more space in the first area to arrange the first area. The capacitor increases the settable number of the first capacitor, so that the first capacitor can better exert the function of regulating the core power supply.

Description of drawings

FIG. 1 is a schematic diagram of an integrated circuit packaging structure according to an embodiment of the present specification.

FIG. 2 is a top view of FIG. 1 .

Fig. 3 is a schematic diagram of a cross-sectional structure along the line AA' in Fig. 2 .

FIG. 4 is a schematic diagram of a first side of a first substrate according to an embodiment of the present specification.

FIG. 5 is a schematic diagram of a connection between a first capacitor and a contact solder ball according to an embodiment of the present specification.

FIG. 6 is a schematic diagram of a first side of another first substrate according to an embodiment of the present specification.

Fig. 7 is a schematic cross-sectional structure diagram along the line BB' in Fig. 6 .

FIG. 8 is a schematic diagram of a first side of still another first substrate according to an embodiment of the present specification.

Fig. 9 is a schematic cross-sectional structure diagram taken along the line CC' in Fig. 8 .

FIG. 10 is a schematic cross-sectional structural diagram of an integrated circuit package structure provided by an embodiment of the present specification.

FIG. 11 is an enlarged schematic diagram of a partial area of a first side of a first substrate according to an embodiment of the present specification.

FIG. 12 is a schematic cross-sectional structure diagram of an integrated circuit system according to an embodiment of the present specification.

FIG. 13 is a schematic cross-sectional structure diagram of another integrated circuit system according to an embodiment of the present specification.

FIG. 14 is an enlarged schematic diagram of a partial area of a fourth side of a printed circuit board according to an embodiment of the present specification.

FIG. 15 is a schematic cross-sectional structural diagram of an integrated circuit package structure provided by an embodiment of the present specification.

FIG. 16 is a schematic flowchart of an integrated circuit packaging method according to an embodiment of the present specification.

Description of reference numbers:

10- Integrated circuit packaging structure;

20 - Integrated circuit system;

100 - the first substrate;

101 - first side;

102 - second side;

1001 - the first area;

1002-Second area;

1001a - depression area;

110-contact solder ball;

110a - the first contact solder ball;

110b - the second contact solder ball;

120 - the first capacitor;

121 - the capacitor body of the first capacitor;

122 - the first pole of the first capacitor;

123 - the second pole of the first capacitor;

130 - Integrated circuit components;

131 - core power supply;

161 - insulating layer;

162 - interconnection trace;

163-pad;

140 - printed circuit board;

141 - third side;

142 - fourth side;

143 - coupling region;

144 - interconnect layer;

145 - the third area;

1451 - a vertical edge of the third area 145;

1452 - another vertical edge of the third area 145;

150 - the second capacitor;

151 - the first pole of the second capacitor;

152 - the capacitor body of the second capacitor;

153 - the second pole of the second capacitor;

171 - the first power terminal;

172 - the second power terminal;

173 - the third capacitor;

202-package side;

201 - circuit side;

2021-decoupling area;

2022 - Welded area.

Detailed ways

This specification describes exemplary embodiments with reference to cross-sectional and/or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this specification, but include deviations in shapes due to, for example, manufacturing. For example, a contact ball shown as a spherical surface will typically have elliptical features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Unless otherwise defined, the technical or scientific terms used in the embodiments of the present specification shall have the usual meanings understood by those with ordinary skill in the art to which the embodiments of the present specification belong. The words "first", "second" and similar words used in the embodiments of the present specification do not indicate any order, quantity or importance, but are only provided to avoid confusion of constituent elements.

Unless the context requires otherwise, throughout the specification, the term "comprising" is to be interpreted in an open, inclusive sense, ie, "including, but not limited to". In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "particular example," or "some examples" and the like are intended to indicate associations with the embodiments or examples A particular feature, structure, material or characteristic of is included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples. In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited by the contents of this specification.

Application overview

With the rapid development of integrated circuit technology, the demand of integrated circuit chips for the information transmission capacity of the integrated circuit packaging structure is getting higher and higher, and the number of solder joints is becoming more and more dense. The ball grid array packaging structure has small size and excellent heat dissipation performance. Due to the characteristics of the same size and electrical performance, the ball grid array package structure of the same size can accommodate more contact solder balls. These characteristics make the ball grid array package structure a more commonly used package form at present.

Modern LSI circuits or VLSI devices such as Application Specific Integrated Circuits (ASICs) and general purpose processors can operate at high frequency, high power specifications. The inventor's research has found that for integrated circuit applications such as servers, the chip size is large, and the load fluctuates greatly when the chip operates. When the current flowing to the integrated circuit components increases sharply, such as when a calculation-intensive process or a high-concurrency process starts. , the inductive effect generated in the circuit will disturb the core power supply voltage (Core Positive Voltage Supply, CVDD), and the resulting power supply ripple may cause the integrated circuit to not work properly. Therefore, it is necessary to improve the power supply stability of integrated circuit chips.

Therefore, the embodiments of this specification provide an integrated circuit packaging structure, so as to reduce or eliminate core power supply fluctuations, optimize the performance of the integrated circuit packaging structure, and improve the system stability of the integrated circuit by improving the integrated circuit packaging structure. The technical solutions in the embodiments of the present specification will be described below with reference to the accompanying drawings in the embodiments of the present specification. Based on the embodiments in this specification, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

Exemplary Package Structure

An exemplary embodiment of the present specification provides an integrated circuit package structure. Referring to FIG. 1 , FIG. 2 and FIG. 3 , FIG. 1 shows a schematic diagram of the integrated circuit package structure 10 , and FIG. 2 is a top view of FIG. A schematic diagram of the first side 101 of the substrate 100), FIG. 3 is a schematic cross-sectional structure diagram along the line AA' in FIG. 2, the integrated circuit package structure 10 includes:

A first substrate 100 comprising a first side 101 and a second side 102 opposite the first side 101, the first side 101 comprising a first region 1001 and surrounding the first region 1001 the second area 1002. The first substrate 100 may be a semiconductor material substrate such as silicon or gallium arsenide, and the integrated circuit component 130 may be formed based on the first substrate 100 using semiconductor processes such as doping, etching, and film formation. The second area 1002 may surround the first area 1001 completely as shown in FIG. 2, or may be partially surrounded (for example, the second area 1002 surrounds three sides or two sides of the first area 1001). The manual does not limit this.

A ball grid array, the ball grid array includes a plurality of contact solder balls 110 distributed on the first side, and the density of the contact solder balls 110 distributed in the first region 1001 is smaller than that distributed in the second Density of contact balls 110 in region 1002 . Contact solder balls 110 located in the same area generally follow the same standard spacing rule, such as a 1.27mm or 1.0mm pitch. Some of the contact balls 110 in the ball grid array are electrically connected to the core power supply of the integrated circuit component 130 , and some of the contact balls 110 in the ball grid array are electrically connected to the negative power supply input (eg, ground) of the integrated circuit component 130 . The integrated circuit components 130 are disposed on the second side 102 opposite the first side 101 of the first substrate 100 , and some contact solder balls 110 in the ball grid array connect input/output signals to the integrated circuit package structure 10 . Without limiting the present specification, the pattern formed by the contact solder balls 110 in the ball grid array may be square, rectangular, or circular (refer to FIG. 4 , which provides the first substrate 100 in an embodiment of the present specification with a pattern). schematic diagram of one side 101), diamond or any other Lattice Configuration. In some exemplary embodiments, the pattern formed by the contact balls 110 in the ball grid array may also be asymmetric, or have limited symmetry. The shape of the contact solder balls 110 may be spherical, and in this case, the contact solder balls 110 may also be referred to as contact balls. Certainly, in some exemplary embodiments of this specification, the shape of the contact solder ball 110 may also be an ellipsoid (refer to FIG. 10 ) or other shapes, which are not limited in this specification. The forming material of the contact solder balls 110 may include metal tin, and the forming process may include reflow soldering.

In this embodiment, the integrated circuit package structure 10 includes a first capacitor 120 , the first capacitor 120 is disposed in the first region 1001 , and the first capacitor 120 is connected to the first substrate 100 through the bonding pad 163 . The interconnection traces 162 on the upper part are connected, and then connected to the contact solder balls 110 through the interconnection traces 162 to be electrically connected to the integrated circuit component 130 . More specifically, referring to FIG. 5 , FIG. 5 shows the first capacitor 120 A schematic diagram of the connection with the contact solder ball 110, the first capacitor 120 includes a capacitor body 121, a first pole 122 and a second pole 123, the first pole 122 is connected to the first contact solder ball 110a electrically connected to the core power supply, the first pole 122 is connected to the core power supply. The diode 123 is connected to the second contact ball 110b electrically connected to the ground terminal. When there are multiple first capacitors 120, the connection relationship between the multiple first capacitors 120 connected in this way is in parallel, and according to physical knowledge, the sum of the total capacitances of the multiple first capacitors 120 connected in parallel is equal to each of the multiple first capacitors 120 connected in parallel. The sum of capacitance values of the first capacitor 120 . In addition, FIG. 5 also shows the insulating layer 161 located on the first side 101 , the insulating layer 161 is used to protect the interconnecting traces 162 and other components on the first side 101 from being corroded by water and oxygen. The first pole 122 and the second pole 123 are respectively connected to different interconnecting traces 162 through the pads 163, so as to realize the electrical connection with the first contact solder balls 110a and the second contact solder balls 110b.

The integrated circuit component 130 may be disposed on the first substrate 100 in a flip-chip manner. At this time, the signal contacts on the integrated circuit component 130 are electrically connected to metal traces on the first substrate 100 through metal bumps. The integrated circuit component 130 is the main load of the integrated circuit system. When the load current is constant or small, the core power supply can meet the requirement of the system to provide a stable voltage for the load. At this time, the voltage across the first capacitor 120 is consistent with the core power supply voltage. When the load current of the system changes greatly due to the drastic changes in the amount of calculation and concurrency, the large and rapid jump of the load current will cause obvious fluctuations in the core power supply voltage of the integrated circuit components. As an energy storage element, the capacitor 120 can provide energy for the core power supply, thereby reducing or reducing the voltage fluctuation of the core power supply and achieving the effect of voltage regulation. In addition, since the density of the contact solder balls 110 in the first region 1001 on the first side 101 of the first substrate 100 is relatively small, a larger space is provided for the first capacitor 120 , which on the one hand improves the performance of the first capacitor 120 . The convenience of setting in the first area 1001 is beneficial to reduce the difficulty of manufacturing the integrated circuit packaging structure 10 and improve the manufacturing yield. On the other hand, it increases the number of the first capacitors 120 that can be arranged in the first area 1001, which is not difficult to understand. The point is that a larger number of first capacitors 120 can provide the system with a larger capacity energy storage capacitor, and only a small voltage change, the larger capacity energy storage capacitor can provide a large enough current to meet the load. The requirement of transient current ensures that the change of the core power supply voltage is within the allowable range and improves the stability of the system.

The first capacitor 120 may be a ceramic capacitor (Ceramic Capacitor) device or a silicon capacitor or other capacitor having the characteristics of compact structure and low equivalent inductance (Equivalent Series Inductance, ESL). In addition, since the ball grid array also needs to be connected to other packaging substrates such as printed circuit boards (PCBs), the first capacitor 120 also needs to have a low height. The height h of 120 is smaller than the height H of the contact solder balls 110 to ensure good electrical contact between the contact solder balls 110 and other packaging substrates, and to avoid abnormal electrical contact between the contact solder balls 110 and other packaging substrates due to the high first capacitor 120 The problem. In some embodiments of this specification, the first capacitor 120 may be a capacitor with a package size of 0402 or 0201, the height of the first capacitor is generally less than 0.35 mm, and the capacitance is less than 2.2 μF. When a ceramic capacitor is selected for the first capacitor 120, due to the low impedance curve of the ceramic capacitor near the mid-frequency band (100MHz), the core voltage drop caused by the load fluctuation is small, so that the core power supply of the integrated circuit component 130 can be affected. IF noise has a good decoupling effect. In the embodiment shown in FIG. 5 , the height H of the contact solder ball 110 refers to the distance between the point where the contact solder ball 110 is farthest from the first side 101 and the surface of the first side 101 , correspondingly, the first capacitor 120 The height h refers to the distance between the point of the first capacitor 120 farthest from the first side 101 and the surface of the first side 101 . Certainly, in other exemplary embodiments of the present specification, the height H of the contact solder ball 110 may also refer to the distance between the point where the contact solder ball 110 is farthest from the interconnection trace 162 and the interconnection trace 162 . The first capacitance The height h of 120 may also refer to the distance between the farthest point of the first capacitor 120 from the interconnection trace 162 and the interconnection trace 162 . All in all, the height of the contact solder ball 110 may be the same as the reference point (plane) for comparison with the height of the first capacitor, which is not exhaustive in this specification.

In an exemplary embodiment of the present specification, referring to FIG. 6 in conjunction with FIG. 2 and FIG. 4 , FIG. 6 is a schematic diagram of the first side 101 of the first substrate 100 . The density of the contact solder balls 110 in the first area 1001 is zero, that is, the first area 1001 is not used for setting the contact solder balls 110 , or the distribution area of the ball grid array is the second area 1002 . In the present exemplary embodiment, since the first area 1001 is not used for arranging the contact solder balls 110 , a larger space is provided for the first capacitor 120 . In the first aspect, the convenience of setting the first capacitor 120 is improved. In the second aspect, also because there is no contact solder ball 110 in the first region 1001 , the possibility that the first capacitor 120 is in contact with the adjacent contact solder ball 110 during the setting process is reduced to a certain extent, and the integrated circuit package structure 10 is improved. production yield. In the third aspect, since the first area 1001 is all used to set the first capacitors 120, a larger number of first capacitors 120 can be installed in the first area 1001 of the same size, thereby increasing the capacity of the core power storage capacitor. , similar to the previous description, the energy storage capacitor with a larger capacity can provide a better voltage regulation function for the core power supply of the integrated circuit component 130 and improve the system stability. In FIG. 6 , the density of the contact solder balls 110 in the first area 1001 is greater than zero, so that the stress between the first area 1001 and the second area 1002 can be caused when the first substrate 100 is soldered to other packaging substrates poor, the possibility of warpage of the first substrate 100 is reduced, and the fabrication yield of the integrated circuit packaging structure is improved.

In an exemplary embodiment of this specification, the ratio of the area of the first region 1001 to the sum of the areas of the first region 1001 and the second region 1002 ranges from 10% to 20%, that is, 10%≤ MA/(MA+MB)≤20%, wherein MA represents the area of the first area 1001 , and MB represents the area of the second area 1002 . Through research, the inventor found that limiting the ratio of the area of the first region 1001 to the sum of the areas of the first region 1001 and the second region 1002 between 10% and 20% can meet the requirements of improving the stability of the core power supply 131 . Basically, the warpage of the substrate caused by the soldering stress of the contacting solder balls 110 after the first substrate 100 is packaged with other packaging substrates is avoided.

In an exemplary embodiment of the present specification, referring to FIG. 7 , FIG. 8 , and FIG. 9 together with reference to FIG. 3 , FIG. 8 is a schematic diagram of the first side 101 of the first substrate 100 of the integrated circuit package structure 10 , and FIG. 7 is FIG. 6 9 is a schematic cross-sectional structure along line BB' in FIG. 8, and FIG. 9 is a schematic cross-sectional structure along line CC' in FIG. 8, the orthographic projection of the first region 1001 on the first side 101 and the core power supply 131 on the The orthographic projections of the first side 101 at least partially overlap. In the embodiment shown in FIG. 9 , the orthographic projection of the first region 1001 on the first side 101 partially overlaps with the orthographic projection of the core power supply 131 on the first side, and the other part does not overlap, so that the overlapped The decoupling path between the first capacitor 120 and the core power supply 131 in the area is relatively short, which is beneficial to improve the capacitive filtering effect of the first capacitor 120 in the overlapping area and ensure that the first capacitor 120 has a good voltage stabilization effect.

In the exemplary embodiment shown in FIG. 3 and FIG. 7 , the orthographic projection of the first region 1001 on the first side 101 coincides with the orthographic projection of the core power supply 131 on the first side, so that the The distance between the first capacitor 120 and the core power supply 131 in the first area 1001 is relatively small, that is, the decoupling paths of the first capacitor 120 disposed in the first area 1001 are relatively short, which is beneficial to improve the first The filtering effect of the capacitor 120 ensures that the first capacitor 120 has a good voltage stabilization effect.

Certainly, in some exemplary embodiments of this specification, the orthographic projection of the first region 1001 on the first side 101 and the orthographic projection of the core power supply 131 on the first side may not overlap. The first region 1001 designed in this way can meet some special packaging requirements, which is beneficial to improve the applicability of the integrated circuit packaging structure 10 .

In an exemplary embodiment of this specification, referring to FIG. 10, FIG. 10 is a schematic cross-sectional structure diagram of an integrated circuit package structure 10, the first substrate further includes: a recessed area 1001a located in the first area 1001, so The first capacitor 120 is disposed in the recessed region 1001a.

Disposing the first capacitor 120 in the recessed area 1001 a helps to increase the space of the first capacitor 120 in the longitudinal direction (the direction perpendicular to the first side 101 and the second side 102 of the first substrate 100 ), so that the space on the first substrate 100 is increased. When the first capacitor 120 is placed on the top, the operation space is larger, which is beneficial to increase the success rate of placing the first capacitor 120 , thereby increasing the fabrication yield of the entire integrated circuit package structure 10 . In addition, due to the existence of the recessed area 1001a, the space in which the first capacitor 120 can be placed in the longitudinal direction becomes larger. On the premise that the height of the first capacitor 120 is less than the height of the contact solder ball 110, a higher height can be selected. The first capacitor 120 can thus provide a greater degree of freedom for the size selection of the first capacitor 120 .

In an exemplary embodiment of the present specification, the area of the recessed area 1001a may be equal to the area of the first area 1001 , that is, the orthographic projection of the recessed area 1001a on the first side 101 may be the same as that of the first area 1001 on the first side 101 The orthographic projections of , are overlapped (as shown in FIG. 10 ), so as to provide as much accommodating space as possible for the first capacitor 120 . Of course, in other exemplary embodiments of this specification, the area of the recessed region 1001a may also be smaller than the area of the first region 1001 , that is, the orthographic projection of the recessed region 1001a on the first side 101 is on the first region 1001 on the first In the orthographic projection on the side 101, the recessed region 1001a thus arranged can provide a larger fault tolerance rate for the formation of the recessed region 1001a, and avoid the formation process of the recessed region 1001a (such as an etching process or a thinning process, etc.) to the first region. Areas other than 1001 cause adverse effects. The specification does not limit the specific size of the recessed region 1001a, which depends on the actual situation.

In an exemplary embodiment of the present specification, referring to FIG. 11 , FIG. 11 shows an enlarged schematic diagram of a partial area of the first side 101 of the first substrate 100 , the number of the first capacitors 120 is multiple, and the number of the multiple The first capacitors 120 are arranged in the first region 1001 in an array manner, and the first capacitors 120 in the same row are oriented in the same direction.

In this embodiment, the orientation of the first capacitor 120 refers to the orientation of the first pole 122 (for example, the positive pole) or the second pole 123 (for example, the negative pole) in the first capacitor 120 relative to the capacitor body 121 . In FIG. 11 , from The first poles 122 of the first capacitors 120 in the first row counted from top to bottom are all oriented toward the upper side of the paper (ie, the direction indicated by arrow DR1 ) relative to the capacitor body 121 , and the second poles 123 are relative to the capacitor body 121 . The orientation of 121 is towards the bottom of the paper. The orientation of the first capacitors 120 in different rows may be the same or different (for example, the orientation of the first capacitors 120 in the second row is different from the orientation of the first capacitors 120 in the first row). Since the interconnection trace 162 connected to the first pole 122 cannot cross the interconnection trace 162 connected to the second pole 123 to avoid short-circuiting the first capacitor 120 , the first capacitor 120 is set so that the interconnection connected to the first pole 122 The traces 162 can all be arranged on one side of the first capacitor, and the interconnecting traces 162 connected to the second pole 123 can be all arranged on the other side of the first capacitor, which is beneficial to simplify the design difficulty of the interconnecting traces 162 and reduce the need for the first capacitor. Risk of short circuit of a capacitor 120.

In an exemplary embodiment of the present specification, still referring to FIG. 11 , the orientation of the first capacitors 120 in the same row is perpendicular to the row direction, and the first poles 122 of the first capacitors 120 in the same row At least one contact solder ball 110 in a row of contact solder balls 110 in the ball grid array is connected.

The second electrodes 123 of the first capacitors 120 in the same row are connected to at least one contact solder ball 110 in another row of the contact solder balls 110 in the ball grid array.

It is not difficult to understand that the row direction is the extension direction of the “row” in the array, and the column direction is the extension direction of the “column” in the array. Referring to FIG. 11 , the direction of the arrow DR1 in FIG. The row direction is vertical. The orientation of the first capacitors 120 in the same row is perpendicular to the row direction, and the contact solder balls 110 connected to the first poles 122 and the second poles 123 of the first capacitors 120 in the same row are distributed in different rows, It is beneficial to reduce the possibility of cross contact with the first pole 122 and the second pole 123 when they are connected to the contact solder balls 110, and improve the production yield of the product.

In FIG. 11 , the first electrodes 122 of the first capacitors 120 are respectively connected to a contact solder ball 110 , and the second electrodes 123 of the plurality of first capacitors 120 are connected to the same contact solder ball 110 . In other exemplary embodiments, the first poles 122 of a plurality of first capacitors 120 may also be connected to the same contact solder ball 110, or the second poles 123 of each first capacitor 120 may be connected to different contact solder balls 110 respectively. This is not limited.

Exemplary Integrated Circuit System

The embodiments of this specification also provide an integrated circuit system. Referring to FIG. 12 and FIG. 13 , the integrated circuit system includes: the integrated circuit packaging structure 10 described in any of the above-mentioned embodiments, and a printed circuit board 140 . The printed circuit board 140 includes a third side 141 and a fourth side 142, the third side 141 includes at least one coupling region 143, the coupling region 143 is coupled with the ball grid array of the first substrate 100, the second Capacitor 150 , the second capacitor 150 is disposed on the fourth side 142 , the orthographic projection of the second capacitor 150 on the fourth side 142 and the positive projection of the contact solder ball 110 on the fourth side 142 The projections do not overlap each other.

The coupling area 143 on the printed circuit board 140 is used to set the first substrate 100 integrated with the integrated circuit components 130 , and the printed circuit board 140 is electrically connected to the integrated circuit components through the ball grid array on the first substrate 100 , different integrated circuit components 130 may have different functions. For example, in FIG. 13 , two integrated circuit components 130 may respectively have data and/or instruction storage functions and computing functions. In actual work, one of the integrated circuit components 130 Corresponding operations and the like may be performed by invoking data and/or instructions stored in another integrated circuit component 130 . This specification does not limit the specific number of the coupling regions 143 on the printed circuit board 140, nor does it limit the specific functions of the integrated circuit components 130 on the first substrate 100 that are coupled and connected on the coupling region 143, depending on the actual situation. Depends.

In this embodiment, the second capacitor 150 disposed on the fourth side 142 of the printed circuit board 140 is connected to the integrated circuit through the interconnection layer 144 inside the printed circuit board 140 and at least part of the contact solder balls 110 in the ball grid array. Electrical connection of component 130 . Since the second capacitor 150 is disposed on the fourth side 142 of the printed circuit board 140 , and this side is not blocked by other components, a larger package and larger capacity of the second capacitor 150 can be provided to provide the core power supply of the integrated circuit component 130 The voltage fluctuation has a voltage regulation effect and improves the system stability.

In an exemplary embodiment of this specification, the package size of the first capacitor 120 is smaller than the package size of the second capacitor 150 , or the capacity of the first capacitor 120 is smaller than the capacity of the second capacitor 150 .

As mentioned above, the first capacitor 120 may be a capacitor with a package size of 0402 or 0201, the height of the first capacitor is usually less than 0.35mm, and the capacitance is less than 2.2μF. The second capacitor 150 may be a capacitor with a package size of 0805 and above, and the value range of the capacitance of the second capacitor 150 may include 22 μF to 100 μF. According to the principle of capacitive decoupling, when the core power supply of the integrated circuit component 130 operates in a low frequency band, such as several tens of kHz, since the inductive reactance generated by the low frequency signal on the inductor can be ignored, in the low frequency band, the first capacitor 120 and the second capacitor The equivalent inductance (ESL) of the 150 can be approximately zero. When the load needs a large current instantaneously, the first capacitor 120 and the second capacitor 150 can supply power to the load in time to reduce or eliminate fluctuations in the core power supply. Since the frequency is low at this time, the discharge time is also relatively long (the inverse of the frequency), so the large-capacity second capacitor 150 can be discharged for a long time at this time, which can have a good voltage regulation effect on the core power supply.

When the core power supply operates at medium and high frequency, when the load changes, the equivalent inductance formed on the first capacitor 120 and the second capacitor 150 cannot be ignored. At this time, the first capacitor 120 with small package, small capacity and low ESL can better The function of quickly supplying current to the load is exerted, so at this time, the first capacitor 120 can supply energy for the core power supply faster, so as to ensure the normal operation of the integrated circuit components and improve the system stability.

That is to say, in general, when the package size of the first capacitor 120 is smaller than that of the second capacitor 150, and the capacity of the first capacitor 120 is smaller than the capacity of the second capacitor 150, the first capacitor 120 can operate at a medium frequency (eg, 100MHz) or high frequency provides a better energy supplement for the core power supply, while the second capacitor 150 can provide a better energy supplement for the core power supply at low frequencies. The first capacitor 120 and the second capacitor 150 complement each other to ensure that the core The power supply can operate stably in the full frequency range (especially in the low frequency and medium frequency range), which improves the system stability.

In an exemplary embodiment of the present specification, still referring to FIG. 12 , the fourth side includes: a third area 145 , and the orthographic projection of the third area 145 on the first side 101 is related to the first capacitance The orthographic projections of the setting area of , at least partially overlap, and the second capacitor 150 is arranged in the third area 145 .

In this embodiment, the first region 1001 is used as an example for the setting area of the first capacitor. In other embodiments of this specification, when the integrated circuit package structure is the package structure shown in FIG. 15 , the setting area of the first capacitor may also be a decoupling area, which is not limited in this specification.

The third area 145 is used to set the second capacitor 150 when the orthographic projection of the third area 145 on the first side 101 and the orthographic projection of the first area 1001 on the first side 101 at least partially overlap , since the density of the contact solder balls 110 in the first region 1001 is relatively small or is not used for arranging the contact solder balls 110 , the freedom of setting the second capacitor 150 in the overlapping region can be increased, without considering the difference between the second capacitor 150 and the contact solder balls 110 positional relationship between.

When the orthographic projection of the third region 145 on the first side 101 completely coincides with the orthographic projection of the first region 1001 on the first side 101 , the freedom of setting the second capacitor 150 increases, and when the first When the area 1001 overlaps with the core power supply of the integrated circuit component, the decoupling path between the second capacitor 150 and the core power supply is relatively short, which is beneficial to improve the decoupling effect of the second capacitor 150, reduce the fluctuation of the core power supply, and improve the system stability.

In an exemplary embodiment of the present specification, referring to FIG. 14 , FIG. 14 is an enlarged schematic diagram of a partial area of the fourth side 142 of the printed circuit board 140 , the number of the second capacitors 150 is multiple, and the multiple is The second capacitors 150 are arranged in an array. In a row of the second capacitors 150 , the direction of the second capacitors 150 is parallel to the row direction, and the first poles 151 of the second capacitors 150 face a predetermined side. Setting, the preset side includes a vertical side closest to the second capacitor 150 among the sides enclosing the third region 145 .

In FIG. 14 , similar to the first capacitor 120 , the second capacitor 150 includes a capacitor body 152 and a second pole 153 of the second capacitor 150 in addition to the first pole 151 of the second capacitor 150 . As mentioned above, the row direction refers to the extension direction of the "row" in the ball grid array, such as the direction shown by the arrow DR2 in FIG. 14 . The first poles 151 of the two capacitors 150 are disposed toward the predetermined side. The outer edge of the third area 145 refers to the side that surrounds the third area 145 , that is, the side that surrounds the third area 145 . Taking FIG. 14 as an example, for the second capacitor 150 in the left column , the vertical side 1451 of the third area 145 is the preset side of the second capacitor 150 in the row. For the second capacitor 150 in the right column, the vertical side 1452 of the third area 145 is the second capacitor 150 in the row. The preset side of the capacitor 150 . The first poles 151 of the second capacitor 150 thus arranged are all oriented to the "outside" (ie, toward the preset side), so that the first poles 151 connected to the core power supply are oriented in the same direction, which is beneficial to simplify the routing on the fourth side 142 . Line design, and the first poles 151 are all facing the outside, which is beneficial to increase the layout space of the lines connected to the first poles 151 , reduce the design difficulty, and improve the manufacturing yield.

It should be noted that, since the package size of the second capacitor 150 is relatively large, in FIG. 12 , FIG. 13 and FIG. 14 , the second capacitors 150 in one of the third regions 145 are arranged in two columns. It is beneficial to simplify the arrangement of the second capacitor 150 and the design of the wiring connected to the second capacitor 150 . However, in other exemplary embodiments of this specification, the second capacitors 150 in the third region 145 may also be arranged in three or more columns according to actual conditions, which is not limited in this specification.

In an exemplary embodiment of the present specification, still referring to FIG. 13 , the integrated circuit system 20 further includes: a first power supply terminal 171 , a second power supply terminal 172 and a third capacitor 173 .

The third side 141 includes at least two of the coupling regions, the third capacitor 173 , the first power supply terminal 171 and the second power supply terminal 172 are disposed between adjacent coupling regions, the The first pole of the third capacitor 173 is connected to the first power terminal 171 , and the second pole of the third capacitor 173 is connected to the second power terminal 172 .

In this embodiment, the first power supply terminal 171 and the second power supply terminal 172 may be the positive terminal and the negative terminal of the system power supply, respectively. The system power supply is the power supply that provides the working voltage for the integrated circuit components carried on the printed circuit board 140 . The third capacitor 173 disposed on the third side 141 of the printed circuit board 140 can perform a good decoupling function for low-frequency power signals (eg, power signals less than or equal to 30 MHz), and improve the stability of the system power supply.

Exemplary Package Structure

One or more embodiments of the present specification also provide an integrated circuit package structure 10. As shown in FIG. 15, the integrated circuit package structure 10 includes a first substrate 100, and the first substrate 100 includes a package side 202 and a The circuit side 201 opposite the package side 202, the circuit side 201 is used for arranging the integrated circuit component 130, the package side 202 includes a decoupling area 2021 and a soldering area 2022 surrounding the decoupling area 2021, the The decoupling region 2021 is used to provide a space for the arrangement of the first capacitor 120 , and the first capacitor 120 is used to reduce or eliminate the power supply fluctuation of the core power supply 131 of the integrated circuit component 130 .

The package side 202 of the first substrate 100 refers to the side that is packaged with other package substrates, and the circuit side 201 of the first substrate 100 refers to the side for arranging the integrated circuit components 130 . It is not difficult to understand that, in order to realize the soldering between the package side 202 and other package substrates, the package side 202 is usually used for disposing a ball grid array including a plurality of contact solder balls 110 , and these contact solder balls 110 are mainly arranged in the soldering area. 2022 , and the decoupling region 2021 is mainly for providing space for the first capacitor 120 to be placed.

In order to provide more space for the first capacitor 120 as much as possible, in an embodiment of this specification, the decoupling region 2021 is not used to set the contact solder balls 110 .

In order to reduce the risk of warpage of the first substrate 100 caused by the provision of the decoupling region 2021, in one embodiment of the present specification, the decoupling region 2021 is used to provide a small number of contact solder balls 110, that is, the decoupling region The density of contact solder balls 110 in 2021 is less than the density of contact solder balls 110 in bonding area 2022 .

That is, in general, the decoupling region 2021 is mainly used for placing the first capacitor 120 . In other words, the area where the first capacitor 120 is placed in the decoupling region 2021 is larger than the area where the contact solder balls 110 are placed.

In this embodiment, a special decoupling area 2021 is provided for the first capacitor 120 in the package side 202 to provide a larger placement space for the first capacitor 120, so that the first capacitor 120 can eliminate or reduce the integrated circuit. Under the premise that the core power supply 131 of the component 130 fluctuates, the difficulty of setting the first capacitor 120 is reduced, and the special decoupling area 2021 is also conducive to placing a relatively large number of first capacitors 120, which is conducive to optimizing the decoupling area 2021. The ability of the first capacitor 120 to suppress fluctuations of the core power supply 131 .

Exemplary packaging method

FIG. 16 is a schematic flowchart of an integrated circuit packaging method provided by an exemplary embodiment of the present specification, and the method includes:

S101: Provide a first substrate, the first substrate includes a first side and a second side opposite the first side, the first side includes a first area and a second area surrounding the first area.

S102: Form an integrated circuit component on the second side, where the integrated circuit component includes a core power supply.

S103: Form a ball grid array on the first side, the ball grid array includes a plurality of contact solder balls, and the density of the contact solder balls distributed in the first area is smaller than that of the contact solder balls distributed in the second area the density of the contact balls.

In step S103, when forming the ball grid array, the contact solder balls may be prepared in the first region and the second region without distinction according to the conventional ball grid array forming process, and then some or all of the contacts in the second region are removed. solder balls, so that the density of the contact solder balls distributed in the first region is smaller than the density of the contact solder balls distributed in the second region. Of course, different ball grid array forming processes can also be used in the first area and the second area, so that the density of the contact solder balls distributed in the first area is lower than that in the second area at the beginning. Density of contact balls in the area. This specification does not limit the specific formation process of the ball grid array, which depends on the actual situation.

S104: Form a first capacitor in the first region, where the first capacitor is connected to at least two of the contact solder balls so as to be electrically connected to the integrated circuit component.

It should be understood that, although the steps in the flowchart of FIG. 16 are sequentially displayed in accordance with the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated in this specification, the execution of these steps is not strictly limited in order, and these steps can be executed in other sequences. Moreover, at least a part of the steps in FIG. 16 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The execution of these sub-steps or stages The sequence is also not necessarily sequential, but may be performed alternately or alternately with other steps or sub-steps of other steps or at least a portion of a phase.

For the specific structures and beneficial effects of the package structure formed by the above-mentioned packaging method, reference may be made to the relevant description of the "exemplary package structure" above, which will not be repeated in this specification.

Exemplary Electronics

One or more exemplary embodiments of the present specification also provide an electronic device including the integrated circuit system as described in any of the above embodiments.

Exemplary Chip

One or more exemplary embodiments of this specification also provide a server chip, where the server chip includes the integrated circuit system described in any of the foregoing embodiments.

The server chip usually has the characteristics of large size, high computational complexity and high concurrency. Using the integrated circuit system described in any of the above-mentioned embodiments, the integrated circuit system is provided through the first side of the first substrate in the integrated circuit system. A capacitor can provide energy for the core power supply of the server chip when the server chip performs high concurrency or high computational workload operations, reduce or reduce the fluctuation of the core power supply, and ensure the normal operation of the server chip. The server chip may include one of a memory and a processor, or an integrated chip that integrates multiple structures such as a memory and a processor. This specification does not limit the specific type and form of the server chip. It depends on the actual situation.

The basic principles of this specification have been described above with reference to specific embodiments. However, it should be pointed out that the advantages, advantages, effects, etc. mentioned in this specification are only examples rather than limitations, and these advantages, advantages, effects, etc. should not be considered to be A must-have for each embodiment of this specification. In addition, the specific details disclosed above are only for the role of example and the role of facilitating understanding, rather than limiting, and the above-mentioned details do not limit the specification to be implemented by using the above-mentioned specific details.

Claims (15)

1. An integrated circuit package structure, comprising:

a first substrate including a first side and a second side opposite the first side, the first side including a first area and a second area surrounding the first area;

the ball grid array comprises a plurality of contact solder balls distributed on the first side, the density of the contact solder balls distributed in the first area is less than that of the contact solder balls distributed in the second area, and the number of the contact solder balls distributed in the second area is multiple;

an integrated circuit component on the second side, the integrated circuit component including a core power supply, an orthographic projection of the first region on the first side at least partially overlapping an orthographic projection of the core power supply on the first side;

a plurality of first capacitors disposed in the first region, the first capacitors being connected to at least two of the contact solder balls to electrically connect with the integrated circuit component.

2. The integrated circuit package structure of claim 1, wherein the density of the contact solder balls distributed in the first area is zero.

3. The integrated circuit package structure of claim 1, wherein a height of the first capacitor is less than a height of the contact solder ball.

4. The integrated circuit package structure of claim 1, wherein an orthographic projection of the first area on the first side coincides with an orthographic projection of the core power supply on the first side.

5. The integrated circuit package structure of any one of claims 1-3, wherein the first capacitors are plural in number, and are arranged in the first region in an array, and the first capacitors in a same row are oriented in a same direction.

6. The integrated circuit package structure of claim 5, wherein the first capacitors in the same row are oriented perpendicular to the row direction, and the first poles of the first capacitors in the same row are connected to at least one contact ball in a row of contact balls in the ball grid array;

the second pole of the first capacitance in the same row is connected to at least one contact ball in another row of contact balls in the ball grid array.

7. The integrated circuit package structure of any one of claims 1-3, wherein the first substrate further comprises: a recessed region in the first region;

the first capacitor is disposed in the recess.

8. An integrated circuit package structure, comprising:

the integrated circuit component comprises a core power supply, and an orthographic projection of the decoupling area on the circuit side and an orthographic projection of the core power supply on the circuit side at least partially overlap with the orthographic projection of the decoupling area on the circuit side.

9. An integrated circuit system, comprising:

an integrated circuit package structure as recited in any of claims 1-8, the integrated circuit package structure comprising a ball grid array;

a printed circuit board comprising a third side and a fourth side, the third side comprising at least one coupling region that couples with a ball grid array of the integrated circuit package structure;

and the second capacitor is arranged on the fourth side, and the orthographic projection of the second capacitor on the fourth side and the orthographic projection of the contact solder balls of the ball grid array on the fourth side do not overlap.

10. The integrated circuit system of claim 9, wherein a package size of the first capacitor of the integrated circuit package structure is smaller than a package size of the second capacitor; or the like, or, alternatively,

the capacitance of the first capacitor is smaller than that of the second capacitor.

11. The integrated circuit system of any of claims 9-10, wherein the fourth side comprises: a third region, wherein an orthographic projection of the third region on the first side is at least partially overlapped with an orthographic projection of a setting region of the first capacitor in the integrated circuit packaging structure on the first side of the first substrate of the integrated circuit packaging structure;

the second capacitor is disposed in the third region.

12. The integrated circuit system according to claim 11, wherein the second capacitors are plural in number, and the plural second capacitors are arranged in an array;

in one column of the second capacitors, the orientation of the second capacitors is parallel to the row direction, the first poles of the second capacitors face a preset edge, and the preset edge includes a vertical edge closest to the second capacitors in the third region outer edge.

13. The integrated circuit system of any of claims 9-10, further comprising: a first power supply terminal, a second power supply terminal, and a third capacitor;

the third side includes at least two of the coupling regions, the third capacitor, the first power terminal, and the second power terminal are disposed between adjacent coupling regions, a first pole of the third capacitor is connected to the first power terminal, and a second pole of the third capacitor is connected to the second power terminal.

14. An integrated circuit packaging method, comprising:

providing a first substrate comprising a first side and a second side opposite the first side, the first side comprising a first area and a second area surrounding the first area;

forming an integrated circuit component on the second side, the integrated circuit component including a core power supply, an orthographic projection of the first region on the first side at least partially overlapping an orthographic projection of the core power supply on the first side;

forming a ball grid array on the first side, wherein the ball grid array comprises a plurality of contact solder balls, the density of the contact solder balls distributed in the first area is less than that of the contact solder balls distributed in the second area, and the number of the contact solder balls distributed in the second area is multiple;

a plurality of first capacitors are formed in the first area, the first capacitors being connected to at least two of the contact solder balls for electrical connection to the integrated circuit component.

15. An electronic device, comprising: the integrated circuit system of any of claims 9-13.

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