CN114420711B

CN114420711B - Display substrate, preparation method thereof and display device

Info

Publication number: CN114420711B
Application number: CN202210126465.6A
Authority: CN
Inventors: 张有为; 程一鸣
Original assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Current assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Priority date: 2022-02-10
Filing date: 2022-02-10
Publication date: 2025-07-29
Anticipated expiration: 2042-02-10
Also published as: CN114420711A

Abstract

The display substrate comprises a substrate, a pixel definition layer and a binding region, wherein the substrate comprises a display region and the binding region is at least positioned at one side of the display region, the pixel definition layer is positioned at one side of the substrate and positioned at the display region and the binding region, and the shortest distance between the surface of the pixel definition layer positioned at one side of the binding region, which is far away from the substrate, and the substrate is smaller than the shortest distance between the surface of the pixel definition layer positioned at one side of the display region, which is far away from the substrate, and the substrate. According to the scheme provided by the embodiment, the thickness of the pixel definition layer positioned in the binding region is reduced, the step difference between the pixel definition layer and the binding pad is reduced, and the yield of subsequent IC binding can be improved.

Description

Display substrate, preparation method thereof and display device

Technical Field

Embodiments of the present disclosure relate to, but are not limited to, display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background

In the self-luminous display technology, whether an Organic LIGHT EMITTING Diode (OLED) or a Quantum dot LIGHT EMITTING Diode (QLED) display technology is adopted, no matter whether a printing process or an evaporation process is adopted, a hole design is required to be manufactured in a pixel, so that the later-stage OLED/QLED evaporation or printing related luminescent materials can conveniently enter the hole, and the technology is commonly called a pixel definition Layer (Pixel Definiton Layer or a Bank Layer, abbreviated as PDL) in the industry. The thickness of the Bank is required in vapor deposition or printing design.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display device, and the binding yield is improved.

In one aspect, an embodiment of the present disclosure provides a display substrate, including:

the substrate comprises a display area and a binding area at least positioned at one side of the display area;

the pixel definition layer is positioned on one side of the substrate and is positioned in the display area and the binding area, wherein the shortest distance between the surface of the pixel definition layer positioned on one side of the binding area, which is far away from the substrate, and the substrate is smaller than the shortest distance between the surface of the pixel definition layer positioned on one side of the display area, which is far away from the substrate, and the substrate.

In another aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, including:

Forming a pixel definition layer provided with a pixel opening on one side of a substrate, wherein the substrate comprises a display area and a binding area at least positioned on one side of the display area, the pixel definition layer is arranged on the display area and the binding area, and the pixel opening is arranged on the display area;

Coating photoresist on one side of the pixel definition layer far away from the substrate, performing halftone mask exposure, development and ashing treatment to ensure that the bottom of the pixel opening is free of photoresist after development, and at least partially covering the side wall of the pixel opening with photoresist after ashing treatment, wherein the exposure degree of the photoresist covering the pixel definition layer positioned in the display area is different from that of the photoresist covering the pixel definition layer positioned in the binding area, so that the shortest distance between the surface of the pixel definition layer positioned in the binding area far away from the substrate and the substrate is smaller than that between the surface of the pixel definition layer positioned in the display area far away from the substrate and the substrate after ashing treatment;

And stripping the photoresist.

In yet another aspect, an embodiment of the present disclosure provides a display device including the above display substrate.

The embodiment of the disclosure comprises a display substrate, a preparation method thereof and a display device, wherein the display substrate comprises a substrate, a pixel definition layer and a pixel definition layer, the substrate comprises a display area and a binding area at least positioned at one side of the display area, the pixel definition layer is positioned at one side of the substrate and positioned at the display area and the binding area, and the shortest distance between the surface of the pixel definition layer positioned at one side of the binding area far away from the substrate and the substrate is smaller than the shortest distance between the surface of the pixel definition layer positioned at one side of the display area far away from the substrate and the substrate. According to the scheme provided by the embodiment, the thickness of the pixel definition layer positioned in the binding region is reduced, the step difference between the pixel definition layer and the binding pad is reduced, and the yield of subsequent IC binding can be improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, and not constitute a limitation of the technical aspects.

FIG. 1 is a schematic plan view of a display substrate according to an exemplary embodiment;

FIG. 2 is a cross-sectional view of the display substrate AA shown in FIG. 1;

FIG. 3 is a schematic illustration of an exemplary embodiment after forming a gate electrode and a first electrode;

FIG. 4 is a schematic illustration of an exemplary embodiment after forming an active layer;

FIG. 5 is a schematic diagram of an exemplary embodiment of a source electrode, drain electrode and second electrode formed;

fig. 6 is a schematic diagram of a second insulating layer formed according to an exemplary embodiment;

FIG. 7 is a schematic diagram of a planar layer formed according to an exemplary embodiment;

FIG. 8 is a schematic illustration of an exemplary embodiment after forming an anode and a third electrode;

FIG. 9 is a schematic diagram of a pixel definition layer formed according to an exemplary embodiment;

FIG. 10 is a schematic illustration of an ashing process according to one exemplary embodiment;

FIG. 11 is a schematic view of a display substrate according to another exemplary embodiment;

FIG. 12 is a schematic view of a display substrate according to yet another exemplary embodiment;

FIG. 13 is a schematic view of a display substrate according to yet another exemplary embodiment;

Fig. 14 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments of the present disclosure and features in the embodiments may be arbitrarily combined with each other without collision.

The steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

In the drawings, the size of each constituent element, the thickness of a layer, or a region may be exaggerated for clarity. Accordingly, embodiments of the present disclosure are not necessarily limited to this size, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or the numerical values shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the disclosure, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, they may be fixedly connected or detachably connected or integrally connected, they may be mechanically connected or electrically connected, they may be directly connected or indirectly connected through an intermediate member, or they may be in communication with the inside of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode, and the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this disclosure, "film" and "layer" may be interchanged. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

At present, the main flow of the OLED luminescent material is carried out by adopting an evaporation process, the printing technology of a luminescent layer is regarded as the development of OLED & QLED directions, and aiming at the flowing property of ink, the printing technology at present also has a plurality of difficulties, wherein the roughness of a pixel defining layer is one of the difficulties, and one direction for improving the roughness of the pixel defining layer is to ensure that no glue residue exists in an opening of the pixel defining layer.

In the OLED manufacturing process, oxygen Plasma (O ₂ Plasma) is used for ashing the organic material, the film thickness of a part of PDL layer is lost, the material surface property in the PDL hole is not required to be high in the evaporation process, but in the QLED luminescent material ink printing process, the hydrophobicity of the material surface is required to be high in the ink, and the hydrophobic layer on the PDL layer surface is ashed in a traditional glue residue removing mode, so that the hydrophobicity is reduced, and the subsequent ink-jet effect is influenced. In an exemplary embodiment, the photoresist is used for protecting the pixel defining layer of the side wall of the pixel opening before the ashing treatment, so that the hydrophobicity of the side wall is prevented from being damaged during the ashing treatment, the ink jet effect is improved, the residual glue in the pixel opening can be removed through the ashing treatment, and the roughness of the pixel opening is improved.

In addition, since there is no flat layer in the Bonding (Bonding) region outside the display region, when the PDL layer target film thickness is 2.0um, the PDL layer thickness of the Bonding region is about 2.9um due to the fluidity of the glue, and the large level difference may cause the Bonding integrated circuit (Bonding IC) of the later stage to fail. In an exemplary embodiment, the yield of integrated circuit (INTEGRATED CIRCUIT, IC) bonding may be improved by reducing the thickness of the PDL layer of the bonding region.

Fig. 1 is a schematic plan view of a display substrate according to an exemplary embodiment. Fig. 2 is a cross-sectional view of the display substrate AA shown in fig. 1. As shown in fig. 1 and 2, the display substrate includes a base 1, and the base 1 includes a display area 100 and a bonding area 200 at least on one side of the display area 100. The display area 100 includes a plurality of subpixels 110 distributed in an array, and the bonding area 200 includes a plurality of bonding pads 210. At least one of the plurality of sub-pixels 110 includes a thin film transistor, a planarization layer, and a light emitting element sequentially disposed on the substrate 1. The flat layer is positioned on one side of the thin film transistor far away from the substrate so as to cover the thin film transistor; the light-emitting element is positioned on one side of the flat layer away from the substrate, and the light-emitting element comprises an anode. The sub-pixels 110 are connected to the bonding pads 210 through the data lines 300, and are connected to an external driving circuit by the bonding pads 210, and only a part of the sub-pixels are connected to the bonding pads 210 through the data lines 300, and the rest of the sub-pixels are similar as shown in fig. 1.

As shown in fig. 2, the display substrate provided in this embodiment includes a substrate 1, where the substrate 1 includes a display area 100 and a binding area 200 at least located at one side of the display area 100. On a plane perpendicular to a base 1 of the display substrate, the display substrate includes a base 1, a gate electrode 2 and a first electrode 3 provided on the base 1, a first insulating layer 4 provided on a side of the gate electrode 2 and the first electrode 3 away from the base 1, an active layer 5 provided on a side of the first insulating layer 4 away from the base 1, a source-drain electrode layer provided on a side of the active layer 5 away from the base 1, the source-drain electrode layer may include a source electrode 6 and a drain electrode 7 and a second electrode 8, a second insulating layer 9 provided on a side of the source-drain electrode layer away from the base 1, a flat layer 10 provided on a side of the second insulating layer 9 away from the base 1, an anode 11 and a third electrode 12 provided on a side of the flat layer 10 away from the base 1, and a pixel defining layer 13 provided on a side of the anode 11 and the third electrode 12 away from the base. The planarization layer 10 includes a first planarization layer via P1, the anode 11 is electrically connected to the drain electrode 7 through the first planarization layer via P1, the second electrode 8 is electrically connected to the first electrode 3 through the first via K1, and the third electrode 12 is electrically connected to the second electrode 8 through the second via K2.

Wherein the gate electrode 2, the source electrode 6, the drain electrode 7, the planarization layer 10, and the anode 11 may be disposed in the display area 100, the first electrode 3, the second electrode 8, and the third electrode 12 may be disposed in the bonding area 200, and the first insulating layer 4, the second insulating layer 9, and the pixel defining layer 13 may be disposed in the display area 100 and the bonding area 200. The gate electrode 2, the active layer 5, the source electrode 6, and the drain electrode 7 constitute the thin film transistor. In another exemplary embodiment, the anode 11 may be electrically connected to the source electrode 6 through the first planarization layer via P1.

In an exemplary embodiment, a shortest distance d1 between a surface of the pixel defining layer 13 located at the binding area 200 away from the substrate 1 and the substrate 1 is smaller than a shortest distance d2 between a surface of the pixel defining layer 13 located at the display area 100 away from the substrate 1 and the substrate 1. According to the scheme provided by the embodiment, the thickness of the pixel definition layer 13 positioned in the binding region is reduced, the step difference between the pixel definition layer 13 and the third electrode 12 is reduced, and the yield of subsequent IC binding can be improved. In the present disclosure, the pixel defining layer 13 located in the display area 100 means that the pixel defining layer 13 located in the display area 100 is orthographically projected on a plane parallel to the substrate 1. The pixel definition layer 13 located in the binding area 200 means that the pixel definition layer 13 located in the binding area 200 is orthographically projected on a plane parallel to the substrate 1.

In an exemplary embodiment, 1.5≤d2/d1≤1.9. For example only, d2/d1 may be other values.

The technical scheme of this embodiment is further described below through the preparation process of the display substrate of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping, etc., and is a well-known preparation process in the related art. The "photolithography process" in this embodiment includes coating a film layer, mask exposure and development, and is a well-known preparation process in the related art. The deposition may be performed by known processes such as sputtering, vapor deposition, chemical vapor deposition, etc., the coating may be performed by known coating processes, and the etching may be performed by known methods, which are not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process or a photolithography process throughout the fabrication process. If the "film" is also subjected to a patterning process or a photolithography process during the entire fabrication process, it is referred to as a "film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern". The phrase "a and B are co-layer disposed" in this disclosure means that a and B are formed simultaneously by the same patterning process.

(1) A flexible material is coated on a glass carrier plate, and cured to form a film, thereby forming a substrate 1. The substrate 1 includes a display area 100 and a binding area 200. In the disclosed embodiment, the substrate 1 may be a flexible substrate. The flexible material can be polyimide PI, polyethylene terephthalate PET or a polymer soft film subjected to surface treatment. In the exemplary embodiment, the substrate 1 may have a single-layer structure or a multi-layer stacked structure. The substrate of the laminated structure may include a flexible material/inorganic material/flexible material, a flexible material/inorganic material/amorphous silicon/flexible material/inorganic material, etc., and the inorganic material may be a Barrier (Barrier) film such as silicon nitride (SiNx) or silicon oxide (SiOx) etc., for improving the water-oxygen resistance of the substrate. Taking a PI/Barrier/PI/Barrier laminated structure as an example, the preparation process can comprise the steps of coating a layer of polyimide on a glass carrier plate, depositing a layer of Barrier film after curing to form a film, coating a layer of polyimide on the Barrier film, and depositing a layer of Barrier film after curing to form the flexible substrate with the laminated structure.

(2) A first metal thin film is deposited on the substrate 1, and patterned by a patterning process to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in the display region 100 and the first electrode 3 is formed in the bonding region 200, as shown in fig. 3.

(3) Sequentially depositing a first insulating film and an active layer film, patterning the first insulating film through a patterning process to form a first insulating layer 4 pattern provided with a first via hole K1, patterning the active layer film to form an active layer 5 pattern, forming an active layer 5 in a display area 100, wherein the first via hole K1 exposes the first electrode 3, and the first insulating layer 4 covers the display area 100 and the bonding area 200, as shown in fig. 4.

(4) A second metal film is deposited, the second metal film is patterned by a patterning process to form a source electrode 6, a drain electrode 7 and a second electrode 8, the second electrode 8 is electrically connected with the first electrode 3 through the first via hole K1, the source electrode 6 and the drain electrode 7 are formed in the display area 100, the second electrode 8 is formed in the binding area 200, and the source electrode 6 and the drain electrode 7 are at least partially arranged on the surface of the active layer 5 to realize electrical connection with the active layer 5, as shown in fig. 5.

(5) Depositing a second insulating film covering the display area 100 and the bonding area 200 as shown in fig. 6;

(6) The flat film is coated, patterns of a flat layer (PLN) 10 and a second insulating layer 9 are formed, a first flat layer via hole P1 is formed on the flat layer 10, the first flat layer via hole P1 is formed in the display area 100, the flat film and the second insulating film in the first flat layer via hole P1 are etched away to expose the surface of the drain electrode 7, a second via hole K2 is formed on the second insulating layer 9, the second via hole K2 exposes the second electrode 8, and as shown in FIG. 7, the flat layer 10 is formed in the display area 100, and the bonding area 200 is free of the flat layer 10. In an exemplary embodiment, the flat film may employ an organic material such as polyimide, etc.;

In an exemplary embodiment, the orthographic projection of the second electrode 8 is located outside the orthographic projection of the second insulating layer 9 in a plane parallel to the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the second electrode 8 may be partially located outside the orthographic projection of the second insulating layer 9 on the plane parallel to the substrate 1, for example, the orthographic projection of the second via K2 may be located inside the orthographic projection of the second electrode 8.

(7) A transparent conductive film is deposited on the substrate on which the foregoing pattern is formed, the transparent conductive film is patterned by a patterning process, an anode 11 and a third electrode 12 are formed on the planarization layer 10, the anode 11 is formed on the display area 100, the third electrode 12 is formed on the bonding area 200, the anode 11 is connected to the drain electrode 7 through a first planarization layer via P1 opened on the planarization layer 10, and the third electrode 12 is connected to the second electrode 8 through a second via K2, as shown in fig. 8. Among them, the transparent conductive film may be indium tin oxide ITO, indium zinc oxide IZO, or the like. In an exemplary embodiment, the anode 11 may be an ITO/Ag/ITO, IZO/Ag/IZO multilayer structure, and a transparent conductive film, an Ag film, and a transparent conductive film may be sequentially deposited and then patterned to form the anode 11.

In an exemplary embodiment, there is an overlap between the front projection of the second via K2 on the substrate 1 and the front projection of the first via K1 on the substrate 1.

(8) A pixel defining film is coated on the substrate on which the foregoing pattern is formed, and a Pixel Defining Layer (PDL) 13 is patterned by a mask, exposure, and development process, wherein the pixel defining layer 13 is provided with a pixel opening formed in the display area 100 and a binding opening formed in the binding area 200, the pixel defining film in the pixel opening is developed to expose the surface of the anode 11, and the binding opening exposes the third electrode 12, as shown in fig. 9. After this process, there is glue residue 14 in the pixel openings and the binding openings.

In an exemplary embodiment, the orthographic projection of the bottom of the bonding opening may be located within the orthographic projection of the third electrode 12 on a plane parallel to the substrate 1. In the solution provided in this embodiment, the sidewall of the third electrode 12 is covered by the pixel defining layer 13, so as to avoid the sidewall of the third electrode 12 from being damaged in a subsequent process, for example, when the third electrode 12 includes Ag, oxidation of Ag during the subsequent ashing process using oxygen can be avoided.

In addition, the third electrode 12 may be used to protect the second electrode 8, so as to prevent the second electrode 8 from being oxidized in the subsequent ashing process.

The pixel defining layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

(9) The method comprises the steps of coating photoresist on a substrate 1 with the patterns, performing halftone Mask (HTM) exposure, development and ashing treatment, wherein when the halftone Mask is subjected to exposure, various exposure degrees exist, so that after development, the bottom of a pixel opening (the surface of the anode 11, which is far away from the substrate 1 side) and the bottom of a binding opening (the surface of the third electrode 12, which is far away from the substrate 1 side) are free of photoresist, the thickness of the photoresist covering the pixel defining layer 13 of the display area 100 is greater than the thickness of the photoresist covering the pixel defining layer 13 of the binding area 200 (the pixel defining layer 13 of the binding area 200 may be covered with the photoresist after development, or may not be covered with the photoresist) and the side wall of the pixel opening is at least partially covered with the photoresist after ashing treatment, and so that after ashing treatment, the thickness of the pixel defining layer of the binding area 200 is reduced (i.e. after ashing treatment, the thickness of the binding area 200 is smaller than the thickness of the pixel defining layer 1, which is far away from the substrate 1 side of the binding area 200, and the pixel defining layer 1, and the thickness of the pixel defining layer 1, which is far away from the substrate 1 side of the substrate 1, after ashing treatment). The glue residues in the pixel openings and the binding openings are removed.

According to the scheme provided by the embodiment, as the side wall of the pixel opening is protected by the photoresist, the hydrophobic layer on the surface of the pixel definition layer of the side wall is not ashed when ashing treatment is carried out, so that the subsequent ink-jet effect is not affected. In addition, the adhesive residue can be removed, and the pixel roughness is improved. In addition, the thickness of the pixel definition layer of the bonding region 200 can be reduced, and the yield of the subsequent IC bonding can be improved.

In an exemplary embodiment, the pixel defining layer 13 of the display area 100 before ashing may include an opening portion 131 constituting a sidewall of the pixel opening and a flat portion 132 except for the opening portion 131, and the method may further include that a thickness of the flat portion 132 after ashing at least partially coincides with a thickness before ashing in a direction perpendicular to the substrate. That is, after the ashing process, the flat portion 132 is covered with photoresist except for the sidewall (opening portion 131) of the pixel opening, and the flat portion 132 is protected so that the pixel defining layer of the display area 100 is not etched away in the ashing process. As shown in fig. 10, after the ashing process, the surface of the pixel defining layer of the display area 100 is covered with the photoresist 15, so as to avoid the pixel defining layer of the display area 100 from being etched during the ashing process. In an exemplary embodiment, only the sidewalls of the pixel openings in the display area 100 may be covered with photoresist after the ashing process, and the flat portions 132 may not be covered with photoresist, at which time the thickness of the flat portions 132 in a direction perpendicular to the substrate may be reduced during the ashing process. According to the scheme provided by the embodiment, the side wall of the pixel opening area is protected by the photoresist, and the hydrophobic layer on the surface of the side wall cannot be ashed, so that the subsequent ink-jet effect cannot be influenced.

In an exemplary embodiment, when the halftone mask exposure is performed, the area 101 where the bottom of the pixel opening is located and the area 201 where the bottom of the bonding opening is located are completely exposed, the display area 100 is not exposed except for the area 101 where the bottom of the pixel opening is located, and the area 201 where the bottom of the bonding opening is located is partially exposed except for the bonding area 200, so that after development, the areas 101 and 102 are free of photoresist, the thickness of photoresist covered by the area except for the area 101 of the display area 100 is greater than the thickness of photoresist covered by the area except for the area 201 of the bonding area 200, so that in the subsequent ashing process, the thickness of the pixel definition layer of the bonding area 200 is reduced, and the thickness of at least part of the pixel definition layer of the display area 100 is unchanged.

In an exemplary embodiment, as shown in fig. 10, the thickness d3 of the pixel defining layer 13 located in the bonding region 200 along the direction perpendicular to the substrate 1 may be 0.8um to 1um. d3 is the value range, the step difference between the pixel defining layer 13 and the third electrode 12 is smaller, so that the yield of the subsequent integrated circuit (INTEGRATED CIRCUIT, IC) binding can be improved. The embodiments of the present disclosure are not limited thereto and the thickness d3 may be other values.

In an exemplary embodiment, as shown in fig. 10, the thickness d4 of the pixel defining layer 13 in the display area 100 along the direction perpendicular to the substrate 1 is, for example, 2um to 3um.

In an exemplary embodiment, the ashing process may be performed using oxygen plasma, but the embodiments of the present disclosure are not limited thereto, and the ashing process may be performed using other gases.

(10) The photoresist 15 is stripped.

Wet stripping may be used to remove the photoresist 15 using an organic or inorganic solvent.

In an exemplary embodiment, the first insulating film and the second insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like, and may have a single-layer structure or a multi-layer composite structure. The first metal thin film and the second metal thin film may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (MTD), or the like, or an alloy material of the above metals such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or the like, and may be a single-layer structure, or a multi-layer composite structure such as Mo/Cu/Mo, or the like. The active layer film may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, or the like.

In a subsequent process, an organic light emitting layer, a cathode, an encapsulation layer, and the like may be sequentially formed in the display area 100, completing the preparation of the display substrate of this embodiment.

The organic light emitting layer may include a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer stacked, the cathode may be made of one of metal materials such as magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), lithium (Li), or an alloy of the above metals, and the encapsulation layer may be made of a stacked structure of inorganic material/organic material/inorganic material.

The structure shown in this embodiment and the process of preparing it are merely exemplary. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the active layer may be disposed on a side of the gate electrode near the substrate, i.e., the display region 100 may include an active layer, a gate electrode, a source electrode, a drain electrode, and the like, which are sequentially disposed.

Fig. 11 is a schematic view of a display substrate according to another exemplary embodiment. As shown in fig. 11, the display substrate provided in this embodiment includes a base 1, the base 1 includes a display region 100 and a bonding region 200 at least on the side of the display region 100, the display substrate includes, along a plane perpendicular to the base 1, a gate electrode 2 and a first electrode 3 disposed on the side of the base 1 away from the base, a first insulating layer 4 disposed on the side of the gate electrode 2 and the first electrode 3 away from the base 1, an active layer 5 disposed on the side of the first insulating layer 4 away from the base 1, a source-drain electrode layer disposed on the side of the active layer 5 away from the base 1, the source-drain electrode layer including a source electrode 6, a drain electrode 7 and a second electrode 8, a flat layer 10 disposed on the side of the second insulating layer 9 away from the base 1, an anode 11 and a third electrode 12 disposed on the side of the flat layer 10 away from the base 1, and a pixel defining layer 13 disposed on the side of the anode 11 and the third electrode 12 away from the base 1. The anode 11 is electrically connected to the drain electrode 7 through a first flat layer via P1, the second electrode 8 is electrically connected to the first electrode 3 through a first via K1, and the third electrode 12 is electrically connected to the second electrode 8 through a second via K2. The shortest distance d1 between the surface of the pixel defining layer 13 on the side away from the substrate 1 and the substrate 1 in the binding area 200 is smaller than the shortest distance d2 between the surface of the pixel defining layer 13 on the side away from the substrate 1 and the substrate 1 in the display area 100.

Wherein, on a plane parallel to the substrate 1, there is an overlap of the orthographic projection of the second electrode 8 with the orthographic projection of the second insulating layer 9, i.e. a portion of the second electrode 8 is exposed by the second via K2. In the former embodiment, the orthographic projection of the second electrode 8 is located outside the orthographic projection of the second insulating layer 9 on a plane parallel to the substrate 1, and the second electrode 8 is entirely exposed by the second via K2.

Fig. 12 is a schematic view of a display substrate according to another exemplary embodiment. As shown in fig. 12, the display substrate provided in this embodiment includes a substrate 1, the substrate 1 includes a display region 100 and a bonding region 200 at least on one side of the display region 100, the display substrate includes, along a plane perpendicular to the substrate 1, a gate electrode 2 and a first electrode 3 disposed on the substrate 1, a first insulating layer 4 disposed on one side of the gate electrode 2 and the first electrode 3 away from the substrate 1, an active layer 5 disposed on one side of the first insulating layer 4 away from the substrate 1, a source-drain electrode layer disposed on one side of the active layer 5 away from the substrate 1, which may include a source electrode 6 and a drain electrode 7 and a second electrode 8, a second insulating layer 9 disposed on one side of the source-drain electrode layer away from the substrate 1, a flat layer 10 disposed on one side of the second insulating layer 9 away from the substrate 1, an anode 11 and a third electrode 12 disposed on one side of the flat layer 10 away from the substrate 1, and a pixel defining layer 13 disposed on one side of the anode 11 and the third electrode 12 away from the substrate 1. The anode 11 is electrically connected to the drain electrode 7 through a first flat layer via P1, the third electrode 12 is electrically connected to the second electrode 8 through a third via K3, and the third electrode 12 is electrically connected to the first electrode 3 through a fourth via K4. The first electrode 3 is disposed in the bonding area 200, the second electrode 8 and the third electrode 12 are at least partially disposed in the bonding area 200, and the second electrode 8 and the third electrode 12 may be partially disposed in the display area 100. The shortest distance d1 between the surface of the pixel defining layer 13 on the side away from the substrate 1 and the substrate 1 in the binding area 200 is smaller than the shortest distance d2 between the surface of the pixel defining layer 13 on the side away from the substrate 1 and the substrate 1 in the display area 100.

According to the scheme provided by the embodiment, the third via hole K3 and the fourth via hole K4 can be formed through one patterning process, and compared with the previous embodiment, the first via hole K1 and the second via hole K2 are required to be formed through two patterning processes respectively, so that one patterning process can be reduced, the process is simplified, and the cost is reduced.

The preparation process of the display substrate shown in fig. 12 is briefly described below, and some details may be referred to the foregoing embodiments, which are not repeated.

The preparation process of the display substrate provided in this embodiment includes:

(1) A flexible material is coated on a glass carrier plate, cured to form a film, and a substrate 1 is formed, wherein the substrate 1 comprises a display area 100 and a binding area 200.

(2) A first metal thin film is deposited on the substrate 1, and patterned by a patterning process to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in the display region 100 and the first electrode 3 is formed in the bonding region 200.

(3) The first insulating film and the active layer film are sequentially deposited, the active layer film is patterned through a patterning process to form patterns of the first insulating layer 4 and the active layer 5, the active layer 5 is formed in the display area 100, and the first insulating layer 4 covers the display area 100 and the bonding area 200.

(4) A second metal film is deposited, the second metal film is patterned through a patterning process to form a source electrode 6, a drain electrode 7 and a second electrode 8, the source electrode 6 and the drain electrode 7 are formed in the display area 100, the second electrode 8 is at least partially formed in the binding area 200, and the source electrode 6 and the drain electrode 7 are at least partially arranged on the surface of the active layer 5 to realize electrical connection with the active layer 5.

In an exemplary embodiment, the second electrode 8 is located on a side of the first electrode 3 near the display area 100.

(5) Depositing a second insulating film covering the display area 100 and the bonding area 200 as shown in fig. 5;

(6) The flat film is coated, patterns of a flat layer (PLN) 10 and a second insulating layer 9 are formed, a first flat layer via hole P1 is formed on the flat layer 10, the first flat layer via hole P1 is formed in the display area 100, the flat film and the second insulating film in the first flat layer via hole P1 are etched away to expose the surface of the drain electrode 7, a third via hole K3 and a fourth via hole K4 are formed on the second insulating layer 9, the third via hole K3 exposes the second electrode 8, the fourth via hole K4 exposes the first electrode 3, the flat layer 10 is formed in the display area 100, and the bonding area 200 is free of the flat layer 10.

(7) A transparent conductive film is deposited on the substrate on which the foregoing pattern is formed, the transparent conductive film is patterned by a patterning process, an anode 11 and a third electrode 12 are formed on the planarization layer 10, the anode 11 is formed in the display area 100, the third electrode 12 is at least partially formed in the bonding area 200, the anode 11 is electrically connected to the drain electrode 7 through a first planarization layer via P1 opened on the planarization layer 10, the third electrode 12 is electrically connected to the second electrode 8 through a third via K3, and is electrically connected to the first electrode 3 through a fourth via K4.

(8) A pixel defining film is coated on the substrate on which the foregoing pattern is formed, and a Pixel Defining Layer (PDL) 13 is patterned by a mask, exposure, and development process, wherein the pixel defining layer 13 is provided with a pixel opening formed in the display area 100 and a binding opening formed in the binding area 200, the pixel defining film in the pixel opening is developed to expose the surface of the anode 11, and the binding opening exposes the third electrode 12, as shown in fig. 8. After this process, there is glue residue 14 in the pixel openings and the binding openings.

(9) The substrate 1 with the pattern is coated with photoresist, and a halftone mask exposure, development and ashing treatment are performed, where, when the halftone mask exposure is performed, there are multiple exposure degrees, so that after development, the bottom of the pixel opening (the surface of the anode 11 far from the substrate 1 side) and the bottom of the binding opening (the surface of the third electrode 12 far from the substrate 1 side) are free of photoresist, the thickness of the photoresist covering the pixel defining layer 13 of the display area 100 is greater than the thickness of the photoresist covering the pixel defining layer 13 of the binding area 200 (the photoresist may be covered on the pixel defining layer 13 of the binding area 200 after development, or may not be covered), and the sidewall of the pixel opening is at least partially covered with photoresist after ashing treatment, and so that after ashing treatment, the thickness of the pixel defining layer of the binding area 200 is reduced (i.e. after ashing treatment, the thickness of the pixel defining layer of the binding area 200 is smaller than the thickness of the pixel defining layer of the binding area 200 before ashing treatment is smaller than the thickness of the pixel defining layer of the binding area 200 on the side of the pixel defining layer 1 far from the substrate 1d 1 and the substrate 1 is located on the side of the substrate 1 far from the substrate 1). The glue residues in the pixel openings and the binding openings are removed.

(10) The photoresist 15 is stripped.

Fig. 13 is a schematic view of a display substrate according to another exemplary embodiment. The display substrate provided in this embodiment may include a substrate 1, where the substrate 1 includes a display area 100 and a binding area 200 at least located at one side of the display area 100, and the display area 100 may include a plurality of sub-pixels, and at least one sub-pixel includes a thin film transistor, a flat layer, and a light emitting element sequentially disposed on the substrate. The flat layer is positioned on one side of the thin film transistor far away from the substrate so as to cover the thin film transistor; the light-emitting element is positioned on one side of the flat layer away from the substrate, and the light-emitting element comprises an anode. The thin film transistor includes an active layer on the substrate, a gate electrode on a side of the active layer away from the substrate, and source and drain electrodes on a side of the gate electrode away from the substrate, and one of the source and drain electrodes is electrically connected to an anode of the light emitting element through the first planarization layer via hole. As shown in fig. 13, the display substrate provided in this embodiment may include a substrate 1, an active layer 5 disposed on the substrate 1, a fourth insulating layer 16 disposed on a side of the active layer 5 away from the substrate 1, a gate electrode 2 and a first electrode 3 disposed on a side of the fourth insulating layer 16 away from the substrate 1, a first insulating layer 4 disposed on a side of the gate electrode 2 and the first electrode 3 away from the substrate 1, a source-drain electrode layer disposed on a side of the first insulating layer 4 away from the substrate 1, and may include a source electrode 6, a drain electrode 7, and a second electrode 8, a second insulating layer 9 disposed on a side of the source-drain electrode layer away from the substrate 1, a flat layer 10 disposed on a side of the second insulating layer 9 away from the substrate 1, an anode 11 and a third electrode 12 disposed on a side of the flat layer 10 away from the substrate 1, and a pixel defining layer 13 disposed on a side of the anode 11 and the third electrode 12 away from the substrate. The planarization layer 10 includes a first planarization layer via P1, the anode 11 is electrically connected to the drain electrode 7 through the first planarization layer via P1, the second electrode 8 is electrically connected to the first electrode 3 through the first via K1, the third electrode 12 is electrically connected to the second electrode 8 through the second via K2, and the source electrode 6 and the drain electrode 7 are electrically connected to the active layer 5. The shortest distance d1 between the surface of the pixel defining layer 13 on the side away from the substrate 1 and the substrate 1 in the binding area 200 is smaller than the shortest distance d2 between the surface of the pixel defining layer 13 on the side away from the substrate 1 and the substrate 1 in the display area 100. In this embodiment, the thin film transistor includes an active layer 5, a gate electrode 2, a source electrode 6, and a drain electrode 7, which are sequentially disposed on a substrate 1. The preparation of the display substrate according to this embodiment, after the formation of the active layer 5 and the fourth insulating layer 16, may refer to the foregoing embodiments for subsequent preparation, and will not be described again.

Fig. 14 is a flowchart of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure. As shown in fig. 14, a method for manufacturing a display substrate according to an embodiment of the present disclosure may include:

step 1401, forming a pixel defining layer provided with a pixel opening on a substrate;

step 1402, coating photoresist on one side of the pixel definition layer far away from the substrate, performing mask exposure, development and ashing treatment, so that the bottom of the pixel opening after development is free of photoresist, and at least partially covering the side wall of the pixel opening after ashing treatment with photoresist;

Step 1403, stripping the photoresist.

According to the preparation method of the display substrate, the side wall of the pixel opening is protected by using the photoresist, so that the surface of the side wall of the pixel opening is prevented from being damaged in the ashing treatment, the subsequent ink-jet printing effect is improved, in addition, the residual photoresist in the pixel opening can be removed, and the pixel roughness is improved.

In an exemplary embodiment, the substrate includes a display area and a binding area at least located at one side of the display area, the pixel defining layer is disposed in the display area and the binding area, and the pixel opening is disposed in the display area;

the mask exposure is a halftone mask exposure, wherein the exposure degree of the photoresist covering the pixel definition layer located in the display area is different from the exposure degree of the photoresist covering the pixel definition layer located in the binding area, so that the shortest distance between the surface of the pixel definition layer located in the binding area, which is far away from the substrate, and the substrate is smaller than the shortest distance between the surface of the pixel definition layer located in the display area, which is far away from the substrate, and the substrate after the ashing treatment.

In an exemplary embodiment, the pixel defining layer located in the display region before ashing includes an opening portion constituting a sidewall of the pixel opening and a flat portion other than the opening portion, and the method further includes that a thickness of the flat portion at least partially in a direction perpendicular to the substrate after ashing is identical to a thickness before ashing.

In an exemplary embodiment, the forming a pixel defining layer provided with a pixel opening on a substrate includes:

Forming a pixel definition layer provided with the pixel opening and a binding opening on the substrate, wherein the binding opening is arranged in the binding area;

the method further includes, after developing, leaving the bottom of the tie opening photoresist free.

In an exemplary embodiment, before forming the pixel defining layer provided with the pixel opening on the substrate, the method further includes:

forming a first electrode on the substrate, the first electrode being formed at the bonding region;

Forming a first insulating layer provided with a first via hole on one side of the first electrode far away from the substrate, wherein the first via hole exposes the first electrode;

Forming a second electrode on one side of the first insulating layer far away from the substrate, wherein the second electrode is electrically connected with the first electrode through the first via hole, and the second electrode is formed in the binding region;

forming a second insulating layer on one side of the second electrode away from the substrate;

Forming a flat layer on one side of the second insulating layer far away from the substrate, and forming a second via hole exposing the second electrode;

and forming a third electrode on one side of the flat layer far away from the substrate, wherein the third electrode is formed in the binding region, the third electrode is electrically connected with the second electrode through the second via hole, and the binding opening exposes the third electrode.

Forming a first insulating layer on one side of the first electrode away from the substrate;

forming a second electrode on one side of the first insulating layer far away from the substrate, wherein the second electrode is at least partially formed in the binding region;

Forming a flat layer on one side of the second insulating layer away from the substrate, and forming a third via hole exposing the second electrode and a fourth via hole exposing the first electrode;

And forming a third electrode on one side of the flat layer far away from the substrate, wherein the third electrode is at least partially formed in the binding region, the third electrode is electrically connected with the second electrode through the third via hole, the third electrode is electrically connected with the first electrode through the fourth via hole, and the binding opening exposes the third electrode.

forming a gate electrode between the substrate and the first insulating layer, the gate electrode being formed in the display region, the gate electrode and the first electrode being formed by the same patterning process;

Forming a source electrode and a drain electrode between the first insulating layer and the second insulating layer, wherein the source electrode and the drain electrode are formed in the display area, and the source electrode, the drain electrode and the second electrode are formed through the same composition process;

and forming an anode on one side of the flat layer away from the substrate, wherein the anode is formed in the display area, the pixel opening exposes the anode, and the anode and the third electrode are formed through the same patterning process.

The embodiment of the disclosure provides a display substrate, which is prepared by using the preparation method of the display substrate in any embodiment. According to the display substrate provided by the embodiment, the pixel definition layer on the side wall of the pixel opening is protected, so that the damage to the hydrophobicity of the surface of the pixel definition layer on the side wall of the pixel opening during ashing treatment is avoided, the ink-jet printing effect is improved, glue residues can be removed, and the roughness of the pixel is improved.

In an exemplary embodiment, the display substrate includes a display area and a binding area at least located at one side of the display area, the pixel defining layer is disposed in the display area and the binding area, and a shortest distance between a surface of the pixel defining layer located at one side of the binding area, which is far from the substrate, and the substrate is smaller than a shortest distance between a surface of the pixel defining layer located at one side of the display area, which is far from the substrate, and the substrate. According to the display substrate provided by the embodiment, the thickness of the pixel definition layer positioned in the binding area is smaller than that of the pixel definition layer positioned in the display area, so that the step difference between the pixel definition layer and the electrode in the binding opening can be reduced, and the binding yield is improved.

In an exemplary embodiment, the thickness of the pixel defining layer at the bonding region along a direction perpendicular to the substrate is 0.8 micrometers to 1 micrometer.

In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode, and a third electrode sequentially disposed on the substrate, the first electrode, the second electrode, and the third electrode are disposed in the binding region, the second electrode is electrically connected to the first electrode through a first via hole, and the third electrode is electrically connected to the second electrode through a second via hole.

In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode, and a third electrode sequentially disposed on the substrate, the first electrode is disposed in the binding region, the second electrode and the third electrode are at least partially disposed in the binding region, the third electrode is electrically connected to the second electrode through a third via, and the third electrode is electrically connected to the first electrode through a fourth via.

In an exemplary embodiment, the pixel defining layer further includes a bonding opening exposing the third electrode, and an orthographic projection of a bottom of the bonding opening may be located within an orthographic projection of the third electrode on a plane parallel to the substrate.

The embodiment of the disclosure also provides a display device, which comprises the display substrate of the embodiment. The display device can be any product or component with display function such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims

1. A display substrate, comprising:

The pixel definition layer is positioned on one side of the substrate and is positioned in the display area and the binding area, wherein the shortest distance between the surface of the pixel definition layer positioned on one side of the binding area, which is far away from the substrate, and the substrate is smaller than the shortest distance between the surface of the pixel definition layer positioned on one side of the display area, which is far away from the substrate, and the substrate;

The thickness of the pixel defining layer in the binding region along the direction perpendicular to the substrate is 0.8 micrometers to 1 micrometer;

The display substrate further comprises a first electrode, a second electrode and a third electrode which are sequentially arranged on the substrate, wherein the first electrode, the second electrode and the third electrode are arranged in the binding area, the second electrode is electrically connected with the first electrode through a first via hole, the third electrode is electrically connected with the second electrode through a second via hole, or the first electrode is arranged in the binding area, the second electrode and the third electrode are at least partially arranged in the binding area, the third electrode is electrically connected with the second electrode through a third via hole, and the third electrode is electrically connected with the first electrode through a fourth via hole.

2. The display substrate according to claim 1, wherein a shortest distance between a surface of the pixel defining layer located at the binding region on a side away from the substrate and the substrate is d1, and a shortest distance between a surface of the pixel defining layer located at the display region on a side away from the substrate and the substrate is d2, and d2/d1 is 1.5≤d2≤1.9.

3. The display substrate of claim 1, wherein the pixel defining layer further comprises a bonding opening exposing the third electrode, an orthographic projection of a bottom of the bonding opening being located within an orthographic projection of the third electrode in a plane parallel to the base.

4. The display substrate according to claim 1, further comprising a plurality of sub-pixels in the display region, at least one of the plurality of sub-pixels comprising a thin film transistor, a planarization layer, and a light emitting element;

The flat layer is positioned on one side of the thin film transistor far away from the substrate so as to cover the thin film transistor;

the light-emitting element is positioned on one side of the flat layer far away from the substrate, and comprises an anode;

The planarization layer comprises a first planarization layer via;

The thin film transistor comprises a gate electrode positioned on the substrate, an active layer positioned on one side of the gate electrode away from the substrate, and a source electrode and a drain electrode positioned on one side of the active layer away from the substrate, wherein one of the source electrode and the drain electrode is electrically connected with an anode of the light emitting element through the first flat layer via hole;

The third electrode is arranged on the same layer as the anode.

5. The display substrate according to claim 4, wherein the first electrode is provided in the same layer as the gate electrode;

The second electrode is arranged on the same layer as the source electrode or the drain electrode.

6. The display substrate according to claim 1, further comprising a plurality of sub-pixels in the display region, at least one of the plurality of sub-pixels comprising a thin film transistor, a planarization layer, and a light emitting element;

the light-emitting element is positioned on one side of the flat layer away from the substrate, and comprises an anode;

The planarization layer comprises a first planarization layer via;

The thin film transistor comprises an active layer positioned on the substrate, a gate electrode positioned on one side of the active layer far away from the substrate, and a source electrode and a drain electrode positioned on one side of the gate electrode far away from the substrate, wherein one of the source electrode and the drain electrode is electrically connected with an anode of the light emitting element through the first flat layer via hole;

the third electrode is arranged on the same layer as the anode, the first electrode is arranged on the same layer as the gate electrode, and the second electrode is arranged on the same layer as the source electrode or the drain electrode.

7. A display device comprising the display substrate according to any one of claims 1 to 6.

8. A method for manufacturing a display substrate, comprising:

And stripping the photoresist.

9. The method for manufacturing a display substrate according to claim 8, wherein the pixel defining layer located in the display region before ashing includes an opening portion constituting a sidewall of the pixel opening and a flat portion other than the opening portion, and the method further includes that a thickness of the flat portion after ashing at least partially in a direction perpendicular to the base is identical to a thickness before ashing.

10. The method of manufacturing a display substrate according to claim 8, wherein forming a pixel defining layer provided with a pixel opening on the base includes:

11. The method of manufacturing a display substrate according to claim 10, further comprising, before forming the pixel defining layer provided with the pixel opening on the base:

12. The method of manufacturing a display substrate according to claim 10, further comprising, before forming the pixel defining layer provided with the pixel opening on the base:

Forming a second electrode on one side of the first insulating layer away from the substrate, wherein the second electrode is at least partially formed in the binding region;