CN114448203B - Control circuit and corresponding method - Google Patents

Abstract

Embodiments of the present disclosure relate to control circuits and corresponding methods. A circuit receives an input signal having a first level and a second level. The logic circuit includes a finite state machine circuit, an edge detection circuit, and a timer circuit. The finite state machine circuit is configured to set an operating mode of the circuit. The edge detection circuit is configured to detect a transition between the first level and the second level. The timer circuit is configured to determine whether the first level or the second level is maintained for a period of time, the period starting from the transition detected by the edge detection circuit. The finite state machine circuit is configured to change the operating mode based on the timer circuit determining that the first level or the second level has been maintained for a period of time.

Description

Control circuit and corresponding method

Cross Reference to Related Applications

The present application claims priority from italian application No. 102020000026530 filed on month 11 and 6 of 2020, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to control logic for electronic circuits and, in particular embodiments, to dynamically managing two different modes of operation for a device and an external clock via a single pin.

Background

Some types of electronic devices may support two different modes of operation. Synchronization with a clock signal generated by an external master clock may be desirable for one or both of these modes.

For example, a switching DC-DC converter may function in a low consumption mode (e.g., burst switching) and a low noise mode (e.g., constant switching). The synchronization signal may be provided by an external clock signal applied to pins in the device for the latter mode, which may identify the signal frequency.

In packages with a limited number of pins, any of the possible modes of operation may be selected by a different "part number" defined for each mode, or a "pin shorting" function may be provided that sets the mode of operation at device start-up so that the same pin may be used for other functions in steady state.

Furthermore, if the selected mode provides possible synchronization with the external clock (e.g., which may be the case for a low noise mode), the clock may be supplied via a dedicated pin.

This may result in a limitation of the possible application areas of the device, since dynamic transition from one mode to another (as may be desired) is not supported.

It is desirable to provide greater flexibility in these cases where a single pin of a device is configured to facilitate dynamic (e.g., on-the-fly) transitions between different modes of operation, as well as schemes that manage external synchronous clocks via the same pin.

Disclosure of Invention

In accordance with one or more embodiments, a circuit and method are provided herein.

As discussed, the flexibility of those devices with different modes of operation that are suitable for selection from the outside may be disadvantageous in applications where it is desired to change the mode of operation in operation. As mentioned, this problem is not properly addressed via pin shorting or by a static selection between two different modes of operation that assign different part numbers to each of the two modes.

At least in principle, dynamic mode changes can be implemented by programming of internal registers, which would involve continuous accessibility of standard programming interfaces.

One or more embodiments may develop a single pin of a device with a reduced area increase to facilitate possible dynamic management of two different modes of operation while also providing an external synchronous clock via the same pin.

In one or more embodiments, the use of a single pin provides the advantage of avoiding the use of multiple pins for devices configured to dynamically switch between two different modes of operation, one of which involves an external clock for synchronization. In this embodiment, no additional pins will be used for modes of operation that do not involve an external clock.

In one or more embodiments, the mode of operation may be determined by a temporal evaluation of the level presented, for example, on the input pins (e.g., single). This configuration may be used for mode selection and for applying an external clock.

In one or more embodiments, an external control level is associated with each mode, wherein the logic circuit is configured to check for a change in level of the signal by detecting a falling edge associated with the change in level, for example. In these embodiments, a low level is associated with a first MODE of operation (MODE 1) and a high level is associated with a second MODE of operation (MODE 2). For example, if the level signal is driven low at start-up, the device "knows" that the current configuration is in MODE1 and implements the relevant configuration in the device. If a level change occurs that may involve a configuration change, the logic circuit may process information about the evaluation duration. The (lower) time threshold may be selected for each particular application. If the signal on the (single) pin previously discussed remains constant at a level above the threshold for a duration, then the change in configuration is verified.

The presence of a clock signal on the pin may be detected as a continuous level change.

One or more embodiments may include a Finite State Machine (FSM) circuit that handles the change between two modes of operation and external clocks and enable and control signals. An edge detector may be provided to detect a rising or falling edge of the signal at the input pin corresponding to the level change. A level filter may be provided to evaluate the level change signal, for example to check whether this has been maintained for longer than a time threshold before modifying the mode or state of operation.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 and 2 are diagrams of embodiment mode of operation transitions;

FIG. 3 is a block diagram of an embodiment;

FIG. 4 is a flow chart of the operation of an embodiment;

FIG. 5 is a diagram of an embodiment operating mode transition that remains active;

FIG. 6 is a diagram of an embodiment operating mode transition that remains inactive;

FIG. 7 is a diagram of an embodiment external clock verification, and

Fig. 8 is a diagram of an embodiment of clock removal.

Detailed Description

The present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments are merely illustrative of specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments may be combined to form further embodiments unless otherwise specified.

Variations or modifications described in one of the embodiments may also be used in other embodiments. Further, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

References to "an embodiment" or "one embodiment" in the framework of the description of the invention are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one or the same embodiment.

Furthermore, the particular structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Headings/references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

One or more embodiments may be applicable to, for example, circuits such as L7983 synchronous buck switching regulator devices, as currently available from the legal semiconductor group company.

This circuit can be seen as an example of a circuit that enables (at least) two different modes of operation, namely a Low Consumption Mode (LCM) and a Low Noise Mode (LNM), taking advantage of the possibility to manage both modes e.g. by a single pin and taking advantage of the switching action of the low noise mode to synchronize with an external clock. Reference to this circuit is by way of example only and does not limit the embodiments.

One or more embodiments facilitate selection between different modes of operation through a single pin of a device (e.g., through dynamic management of transitions from one mode to another). Further, one or more embodiments provide logic circuitry that is capable of checking whether an external synchronous clock signal is present on the pin.

As discussed, certain devices that fix the operating mode at startup (e.g., via pulling up to VCC or down to GND on the select pin) do not take into account the possibility of dynamically changing the operating mode as desired by various applications.

For example, in some devices, the configuration is fixed via trim bits, which may limit flexibility. Further, if synchronization with an external clock is considered for one of the modes of operation, a pin for providing the clock may be kept floating when the device is configured in a mode or application where synchronization is not desired.

One or more embodiments may relate to a time assessment mechanism for signal values at input pins of a device configuration, thereby providing greater flexibility of device use.

Fig. 1 and 2 refer by way of example to the possible transitions between two MODEs of operation (i.e. MODE1 and MODE 2). Fig. 1 is an example of conversion from MODE1 to MODE 2. Fig. 2 is an example of conversion from MODE2 to MODE 1. It will be further appreciated that one or more embodiments are very "transparent" to the nature of these two modes of operation.

The example shown refers to a pin 10 in an electronic circuit (not visible as a whole in fig. 1 and 2). Pin 10 may be configured to receive a signal MODSEL_CLKEXT for selecting between two MODEs of operation (i.e., MODE1 and MODE 2).

Throughout this specification, for simplicity and ease of understanding, pin 10 will also be referred to as the MODSEL_CLKEXT pin.

In the illustrated example, this MODSEL_CLKEXT pin can also be used to provide a device associated with (e.g., external) the synchronized clock CLKEXT, as desired in either (or both) of the two aforementioned modes of operation.

For example, an operating MODE (MODE 1 or MODE 2) may be selected on the MODSEL_CLKEXT pin by holding the pin at a constant level (e.g., high or low) for a time Tmin, where each level is associated with one of the MODEs. The time Tmin for maintaining the signal level may be set to vary (possibly by its setting) depending on the application for which the device is intended to be used.

For example, in FIG. 1, when MODE1 is enabled, the rising edge of the signal at MODSEL_ CLKTEXT pin can be "filtered" within Tmin to detect a stable high level before the internal MODE signal is set to MODE 2.

Further, in FIG. 2, when MODE2 is enabled, the falling edge of the signal at the MODSEL_ CLKTEXT pin can be "filtered" within Tmin to detect a stable low level before the internal MODE signal is set to MODE 1.

Those skilled in the art will readily appreciate that specific references to rising/falling edges and high/low levels are merely exemplary, as the same type of operation may be obtained in which the roles of rising/falling edges and/or high/low levels are reversed.

In one or more embodiments, time Tmin may be used to determine the current operating MODE (i.e., MODE1 or MODE 2) and facilitate dynamic transitions between the two MODEs when a change in operating MODE is desired.

One or more embodiments can relate to detection logic that continuously detects rising and falling edges of a signal at a MODSEL_CLKEXT input pin, which has the ability to detect level changes and determine an operating mode based on the following mechanism.

For example, if, at device start-up, the high or low level of the signal at MODSEL_CLKEXT remains stable for a minimum time T at least equal to Tmin, then the device is configured in the corresponding operating mode.

Furthermore, if the (falling or rising) edge of the signal is subsequently detected such that the level changes (e.g., from high to low or vice versa) and the new level is maintained for a time T at least equal to Tmin, then the logic interprets this level change as expected to produce a change in the operating mode of the device.

Furthermore, if a pulse train is detected at the pin (e.g. a continuous level change or switching), a check of the external synchronization clock may be made-a continuous transition between spikes or modes of operation affecting the signal value.

For example, if the signal level at the MODSEL_CLKEXT pin is detected to switch as an indication of a stable level at a time period T that is shorter than time Tmin, then the time between consecutive rising edges of the signal can be analyzed (e.g., based on information received from a circuit block that can filter an external clock).

Further, if at least N rising edges of the signal are detected for a period of time less than or equal to the lower threshold Tckmin, then it is assumed that a CLKEXT clock signal having a frequency greater than or equal to 1/Tckmin is present at the pin.

Time Tckmin may be selected as the longest period considered by the external clock (i.e., its maximum value) -an indication of the lowest (i.e., smallest) frequency within the frequency range considered by the external clock. The summary of the selection mechanism discussed above is reproduced in table I below.

TABLE I-Signal level based operation mode selection

Those skilled in the art will again appreciate that specific references to low/high levels and MODE1/MODE2 are merely exemplary, as the roles of levels and MODEs implementing the same type of operation may be reversed.

In an embodiment, a circuit such as an integrated device is considered to have (at least) two different MODEs of operation (e.g., MODE1 and MODE 2) that can be selected depending on two different levels of a signal applied to an input pin (MODSEL_CLKEXT), where the same pin can also provide an external clock for synchronization.

In this embodiment, a change in operation of the operating MODE of the device switch, e.g., to MODE2 (see fig. 1) when MODE1 is enabled or to MODE1 (see fig. 2) when MODE2 is enabled, is facilitated from an external drive pin via, e.g., a microprocessor or other logic circuit.

For example, in the illustrated example, the operating mode can be considered a default mode to enable at device start-up, which can be selected in response to a low level signal ("0") at the MODSEL_CLKEXT input pin.

The control logic processes the corresponding signal of the value "0" and indicates the value MODE1 of the internal MODE signal.

MODE MODE2 may be selected in response to a high level present at the input pin MODSEL_CLKEXT corresponding to a value of "1" of the internal MODE signal.

Fig. 3 is a block diagram example of an embodiment circuit 100 in accordance with an embodiment of the present invention described including control logic and some support blocks.

As illustrated in fig. 3, circuit 100 includes logic 120 built around Finite State Machine (FSM) circuit 12, which is configured to manage transitions between two MODEs of operation (i.e., MODE1, MODE 2) and selection of an external clock in accordance with signals from the various blocks and support circles in the logic.

For example, as illustrated in fig. 3, circuit 12A may be configured to generate MODE signals (mode=mode 1 or MODE 2) in accordance with signals old_mode, new_mode, and update_mode of finite state machine circuit 12, as discussed below.

As similarly discussed below, the finite state machine circuitry 12 may also be configured to generate signals CLK_EXT_GOOD and CLK_EXT_FILT that are related to the selection of an external clock, as discussed below.

As illustrated in fig. 3, the logic circuit 120 includes an edge detection circuit 14, the edge detection circuit 14 being sensitive to the signal modsel_clkext at pin 10. The edge detection circuit 14 is configured to detect a rising or falling edge of the input signal received at that pin, which corresponds to a level change of the signal MODSEL_CLKEXT and generates a corresponding signal mode_ CLKEXT _edge that is applied to the finite state machine circuit 12.

As illustrated in fig. 3, logic circuit 120 also includes timer circuit 16. The timer circuit 16 may include a counter configured to evaluate (i.e., enabled by the signal mode_cnt_en from the finite state machine circuit 12) whether the change in level of the signal MODSEL_CLKEXT at pin 10 is maintained for a minimum time (Tmin) before a new mode of operation is verified. Since the count signal mode _ cnt (see also fig. 4 and 5) reaches the upper threshold (Thmin) which is in accordance with the time Tmin previously discussed, it may be involved in generating an overflow signal that is applied to the active state machine circuit 12.

As illustrated in FIG. 3, logic circuit 120 also receives information from check circuit 18 and counter circuit 20 to verify the presence of an external clock signal that may be applied to pin 10 as a MODSEL_CLKEXT signal.

As illustrated in fig. 3, the checking circuit 18 includes a counter configured to evaluate whether the frequency of the incoming pulse train received at pin 10 corresponds to (i.e., meets) the minimum (i.e., smallest frequency) frequency permitted by the external clock by generating a corresponding signal (i.e., designated tclk_good in the drawing) applied to the finite state machine circuit 12.

As illustrated in FIG. 3, the counter circuit 20 includes another counter configured to count N number of rising edges of an incoming burst received as MODSEL_CLKEXT, which facilitates determining the presence of an external clock by generating a corresponding signal (i.e., designation NPulse _OK in the drawing) that is applied to the finite state machine circuit 12.

As illustrated in fig. 3, the circuit 100 also includes a clock circuit 22 (of any type known to those skilled in the art), the clock circuit 22 generating an internal clock signal clk_int that is supplied to the control logic 120, as discussed below in connection with fig. 5 and 6.

Even though illustrated as separate elements for ease of explanation, clock circuit 22 may be included in circuit 140 in fig. 3.

As illustrated in fig. 3, logic circuit 120 is configured to pass signal patterns, clk_ext_good, and clk_ext to another circuit 140 in circuit 100. These circuit stages may comprise, for example, one or more analog blocks and an oscillator.

One or more embodiments are very "transparent" to the nature of circuit 140, which also motivates the embodiment to be very transparent to the nature of the MODE (i.e., MODE1, MODE 2).

FIG. 4 is a flow chart of an exemplary embodiment of a possible operation of control logic as previously discussed.

Step 1000 corresponds to a start (start mode).

At step 1002, the device is configured to operate in a default MODE selected from MODE1 and MODE2, depending on the current value (e.g., low or high) of the signal MODSEL_CLKEXT (i.e., mode=MODSEL_CLKEXT).

At step 1004, the occurrence of a rising/falling edge in the signal MODSEL_CLKEXT as indicated by the signal MODSEL _ CLKEXT _edge from the edge detection circuit 14 is checked. If the check yields a negative result (no = no edge detected), then return to step 1002.

At step 1006, if the check at step 1004 yields a positive result (i.e., yes = detected edge), then the signal mode_new is made equal to MODSEL_CLKEXT.

At step 1008, the duration of the level transition caused by the edge is measured by setting mode_cnt_en= "1", increasing the count cnt=cnt+1, and setting the mode to the current mode, i.e., mode=mode_curr.

At step 1010, the current (cumulative) count value is checked against overflow with a threshold value corresponding to Tmin. At each increment, the value is compared to a threshold value and an overflow signal is generated in response to the count reaching a count value.

At step 1012, if the check at step 1010 yields a negative result (i.e., no = no exceeding the threshold duration), then another check is performed as to whether modsel _ clkext _edge from the edge detection circuit 14 indicates a (further) edge. If the check at step 1012 yields a negative result (i.e., no = no further edge detected), then return to step 1008.

At step 1014, if the check at step 1010 is positive (i.e., yes = occurrence of a count overflow, indicating that the level change of MODSEL_CLKEXT continues to exceed Tmin), then mode_cnt_en= "0" and update_mode = mode_new.

At step 1016, the operation mode is set to a new mode (caused by the change) mode = update_mode.

At step 1018, when the counter has exceeded the threshold, in response to the result of the check at step 1012 being positive (i.e., being =another edge detected), CNT is set to "0" indicating a spike in the input signal as expected.

At step 1020, it is checked whether CLK_EXT_GOOD from the checking circuit 18 indicates that the frequency of the received incoming pulse train coincides with the lowest (minimum) frequency allowed by the external clock. If the check at step 1020 is negative (i.e., confirms a spike in the input signal), then return to step 1006.

At step 1022, in response to the check at step 1020 being positive (i.e., the frequency of the received incoming burst is consistent with the minimum frequency allowed by the external clock), then step 1016 is passed as previously discussed.

At step 1024, regardless of the path followed to step 1016 (e.g., from step 1014 or step 1022), another check is performed as to whether CLK_EXT_GOOD from the checking circuitry 18 indicates that the frequency of the received incoming burst is consistent with the minimum frequency permitted by the external clock. If the result of the check at step 1024 is positive, then return to step 1016.

At step 1026, in response to the check at step 1024 being negative (i.e., no), another check is performed as to whether modsel _ clkext _edge from the edge detection circuit 14 indicates a (further) edge. If the result of the check at step 1026 is negative (i.e., no=no further edge detected), then return to step 1016. If the test at step 1026 is positive (i.e., yes = another edge detected), then return to step 1006.

It should be noted that the check of clk_ext_good at step 1016-1024 will be negative in response to the count overflow corresponding to the mode change from step 1014, and the current mode will be maintained until a new signal edge occurs.

Further, in response to identifying that the external clock arrived at step 1016 from step 1022—the check of CLK_EXT_GOOD at step 1024 will be positive and the mode corresponding to the presence of the external clock will be maintained until the check becomes negative.

Furthermore, the signal CLK_EXT_GOOD generated by finite state machine circuit 12 depends on the signal TCLK_GOOD (e.g., the distance between two consecutive rising edges corresponding to the minimum expected frequency) and Npulse _OK (e.g., the count of at least N >1 rising edges on the MODSEL_CLKEXT pin) from checking circuit 18 and counter circuit 20, respectively, where these blocks are enabled on the rising edges of the signal at the MODSEL_CLKEXT pin.

As previously discussed, the operations may be further illustrated by reference to fig. 5 and 6. These figures depict the common time scale t (abscissa scale), the possible timing behavior (from top to bottom) of the internal clock signal clk_int from the clock circuit 22 (fig. 3), the signal modsel_clkext received at pin 10, the signal new_mode from the finite state machine circuit 12, the signal mode_ CLKEXT _edge from the edge detection circuit 14, the enable signal mode_cnt_en provided by the finite state machine circuit 12 to the timer circuit 16, the level filtered signal mode_cnt, the overflow signal provided by the timer circuit 16 to the finite state machine circuit 12 in response to the signal mode_cnt reaching the upper threshold th _min (which varies as a function of the threshold time Tmin), and the MODE signal switched (e.g., from MODE1 to MODE 2).

Briefly, when the signal on the MODSEL_CLKEXT pin (i.e., pin 10) undergoes a level transition (e.g., from low to high in FIG. 5), the edge detection circuit 14 detects a change (which is a signal edge) and generates a corresponding mode_ CLKEXT _edge pulse.

The pulse is processed in finite state machine circuit 12, which thus performs various actions, as previously discussed in connection with the flowchart of fig. 4, generating a MODE cnt en signal, enabling timer circuit 16, the MODE signal being maintained at a current level (e.g., low level=mode1) until a new level is verified (e.g., high level=mode2), and storing a change in the new level via an internal signal new_mode (e.g., high level=mode2).

The timer circuit 16, enabled by the mode_cnt_en signal from the finite state machine circuit 12, increments the mode_cnt counter at each cycle of the internal clock clk_int until the threshold count value th _min is reached.

As discussed, this threshold may be defined as a minimum time value Tmin established upon verification of the operating mode of the device.

When the mode _ cnt counter reaches a threshold value (e.g., there is no further change in the detected signal level), timer circuit 16 generates an overflow signal (e.g., flag) that resets the count.

In response to detecting the overflow flag, finite state machine circuit 12 updates the internal MODE signal to a logical value previously stored on "new_mode" (e.g., high level=mode 2), which is evaluated as stable by timer circuit 16 for time Tmin.

The device operating MODE is then updated to a new operating MODE (e.g., MODE 2).

Similarly, if a subsequent falling edge is detected on the input pin (i.e., MODSEL_CLKEXT at pin 10), and the signal level remains low for a time greater than Tmin after this edge, finite state machine circuit 12 will again change operating MODE (e.g., to MODE 1).

If the signal presented on the input pin changes level again and then returns to the previous level before the counter (signal mode cnt) reaches the threshold th _min, the logic circuit 120 will not change the value of the mode signal, treating the change as a spike in the input signal.

This possible mode of operation is illustrated in fig. 6.

As noted, FIG. 5 is an example of a MODE transition that causes a change from MODE1 to MODE2 in response to a rising edge in the signal MODSEL_CLKEXT, which results in an overflow signal being asserted.

By contrast, the right hand side of FIG. 6 is an example of an "invalid" MODE transition in which MODE1 is maintained (without regard to the falling edge in signal MODSEL_CLKEXT) as a result of the count signal mode_cnt not reaching the threshold corresponding to Th _min.

If a burst is present on the MODSEL_CLKEXT pin (i.e., pin 10), then the logic circuit 120 can investigate whether this corresponds to an external clock or is caused by a continuous change in the operating mode.

This type of operation is illustrated in fig. 7 (external clock verification) and fig. 8 (external clock removal).

These figures again depict the common time scale t (abscissa scale), the possible timing behavior (from top to bottom) of the signal MODSEL_CLKEXT received at pin 10, the signal CLK_EXT_GOOD from finite state machine circuit 12, the signal CLK_EXT_FILT from finite state machine circuit 12, and the MODE signal switching (e.g., from MODE1 to MODE2 in FIG. 7, and from MODE2 to MODE1 in FIG. 8).

As illustrated herein, the counter circuit 20 detects each rising edge of the signal on the MODSEL_CLKEXT pin (i.e., pin 10) and generates the Npulse _OK signal in response to having counted N number of rising edges.

At the same time, filtering of the frequency of the clock signal received at the MODSEL_CLKEXT pin (i.e., pin 10) is performed in the check circuit 18. The check circuit 18 is enabled at each rising edge of the signal on the MODSEL_CLKEXT pin and is configured to evaluate the distance between two consecutive rising edges and to undergo a reset when the distance between edges exceeds the value of the minimum expected frequency of the (expected) external clock signal.

If the detected edges are separated by a time Tck that is shorter than Tckmin, then the check circuit 18 generates a tclk_good signal. Accordingly, the logic circuit 120 will generate the internal signal CLK_EXT_GOOD to verify the presence of the external clock CLK_EXT on pin 10 (MODSEL_CLKEXT). The clock will thus have a period defined by the switching time Tck of the burst.

The MODE signal will be adapted to MODE2, which in the example shown provides a supply of/synchronization with an external clock.

For example, if MODE1 is enabled before receiving the burst, then the MODE is changed from MODE1 to MODE2. On the other hand, if MODE2 is the enabled MODE prior to the burst, MODE2 will be verified. In both cases, logic circuit 120 will pass the external clock to circuit 140 (see FIG. 3) through the CLK_EXT_FILT output of finite state machine circuit 12.

That is, as illustrated in FIG. 7, if at least N rising edges are detected that are separated by a distance Tck (asserted CLK_EXT_GOOD) that is less than Tckmin, then the logic circuit 120 filters the value on pin MODSEL_CLKEXT (pin 10) to check for a valid external clock and verify the clock. Once verified, the clock is forwarded to circuit 140 (asserted CLK_EXT_FILT) within finite state machine circuit 12 and the internal signal MODE is set to MODE2 or verified at MODE 2.

If, conversely (see FIG. 8), the verify signal CLK_EXT_GOOD is reset during the time Tck when no rising edge is detected, and the logic circuit 120 causes a counter in the timer circuit 16 to check whether the signal level on the MODSEL_CLKEXT pin remains stable at time T > Tmin.

If the signal on the MODSEL_CLKEXT pin remains stable (e.g., high) up to the threshold set by Tmin, then the internal MODE signal remains at MODE 2. On the other hand, if it is smoothly low for Tmin, the internal signal will switch to MODE1.

Logic circuit 120 thus continuously monitors the change in signal on the input pin (MODSEL_CLKEXT-pin 10) to facilitate dynamic transitions between operating MODEs (MODE 1 through MODE2 and vice versa) provided by the device and management of possible external clocks.

That is, as illustrated in FIG. 8, the logic circuit 120 continuously checks the reset signal CLK_EXT_GOOD if the distance between two consecutive rising edges is shorter (lower) than Tck, and if the distance is longer (higher) than Tck. Logic circuit 120 begins counting T > Tmin to detect whether a stable level (high or low) is present on the input pin and change the internal mode signal accordingly.

The example illustrated herein is where the pointer considers the external synchronous clock for only one of the two MODEs (here, the MODE indicated as MODE 2).

Those skilled in the art will additionally appreciate that the present invention will also apply mutatis mutandis to the more general case of externally synchronized clocks recognized by both MODE1 and MODE 2.

In this case, the user may set a first desired mode with a first action, keep the signal level stable at time T > Tmin, and then provide a synchronized clock as described.

As repeated above, it will be readily appreciated by those skilled in the art that specific references to certain signal edges, rising and falling edges, respectively, and certain signal levels, high and low, respectively, are merely exemplary, as the same type of operation may be obtained, e.g., wherein the roles of rising/falling edges and/or high/low levels are reversed.

The circuit (e.g., 100) as illustrated herein may include a logic circuit (e.g., 120) coupled to an input node (e.g., 10) configured to receive an input signal (e.g., MODSEL_CLKEXT) exhibiting a transition between a first level and a second level. The logic circuit may include a state machine (e.g., 12) coupled to the input node. The state machine is configured to set the circuit (e.g., 100-including stage 140) to either one of a first MODE of operation (e.g., MODE 1) and a second MODE of operation (e.g., MODE 2) in response to an input signal (e.g., via a signal MODE) having a first level or a second level, respectively.

Further, an edge detector block (e.g., 14) is coupled to the input node. The edge detector block is configured to detect transitions (e.g., rising and falling edges) between a first level and a second level in the input signal and to send a corresponding transition signal (e.g., mode_ clkext _edge) to the state machine (12).

Further, a timer block (e.g., 16) is coupled (e.g., to be enabled via signal mode_cnt_en) to the state machine and is configured to check whether the first level or the second level in the input signal is maintained beyond a threshold period (e.g., tmin) from a transition detected by the edge detector block.

The state machine is configured to change the operating mode of the circuit from one of the first operating mode and the second operating mode to the other operating mode in response to a check in the timer block that the first level or the second level in the input signal has been maintained within a threshold period from a transition detected by the edge detector block.

The circuitry as illustrated herein may include processing circuitry (e.g., inspection circuitry 18 and counter circuitry 20) coupled to the input nodes, as well as a state machine. The processing circuit is configured to apply a signal received at the input node as a verification clock signal to the circuit in response to the input signal exhibiting N number of transitions from one of the first level and the second level to the other level and a frequency of transitions between the first level and the second level exceeding a lower threshold.

One or more embodiments may thus utilize edges that occur within Tmin and on a lower (e.g., minimum) limit on the frequency of the edges in order to assert that a true clock is applied to the pins.

If the pin level changes, where the frequency is below a threshold value of the frequency of the external signal identified as the clock signal (which threshold frequency may be selected and set to vary depending on the intended application or use), the signal considered as a clock will be erroneous because the signal will only correspond to the user in selecting one mode instead of another.

In one or more embodiments, to evaluate the presence of an external clock, the time TCKmin that elapses between two consecutive rising edges of the signal is checked as less than time Tmin, during which the signal remains stable after a change in level that causes a change in mode.

Furthermore, even in the presence of an "acceptable" frequency value, checking for the presence of N number of transitions from one of the first level and the second level to the other level may provide a safety limit that asserts the presence of a clock signal via a masking effect over a (e.g., minimum) desired number of clock cycles N (where n=1 represents a limiting case of such masking effect).

The circuit as illustrated herein may be configured to apply the signal received at the input node as a verification clock signal to the circuit for only one of the first and second MODEs of operation (e.g., only for MODE2 and not for MODE 1).

That is, the clock signal may (but need not) be passed to circuitry for only one of the two MODEs, which in turn means that the clock signal identified at MODSEL_CLKEXT does not imply a change between MODE1 and MODE 2.

In the circuit as illustrated, the state machine may thus be configured to apply a signal received at the input node as a verification clock signal to the circuit in combination with setting the circuit to or maintaining the circuit in the only one of the first and second modes of operation.

That is, the state machine can be configured to change the operating mode of the circuit only if one of the two levels at MODSEL_CLKEXT is maintained beyond a threshold period Tmin from the transition detected by the edge detection circuit 14.

For example, if the signal at MODSEL_CLKEXT remains high up to the threshold indicated by Tmin, then the internal MODE signal is maintained at MODE 2. If, conversely, the signal at MODSEL_CLKEXT is stable low within Tmin, then the internal MODE signal switches to MODE1, as illustrated in FIG. 8.

That is, the state machine may be configured to change the operating MODE of the circuit from one of the first operating MODE and the second operating MODE to the other operating MODE (e.g., from MODE1 to MODE 2) only in response to a check that a first level (e.g., low) in the input signal has been maintained within a threshold period from the start of the transition detected by the edge detector block in a timer block (e.g., 16).

Conversely, the state machine may be configured to maintain the operating MODE of the circuit at one of the first operating MODE and the second operating MODE (e.g., maintain MODE 2) in response to a check in the timer block indicating that the second level (e.g., high) in the input signal has been maintained within the threshold period from the start of the transition detected by the edge detector block.

As illustrated herein, a method of operating a circuit (e.g., 100) having an output node (e.g., 10) configured to receive an input signal (e.g., modsel_clkext) exhibiting transitions (e.g., rising/falling edges) between a first level and a second level may include setting the circuit to either of a first MODE of operation (e.g., MODE 1) and a second MODE of operation (e.g., MODE 2) in response to the input signal having a first level or a second level, respectively (e.g., via a signal MODE).

The method may further include detecting (e.g., at edge detection circuit 14) a transition between a first level and a second level in the input signal, checking (e.g., at timer circuit 16) whether the first level or the second level in the input signal is maintained beyond a threshold period (e.g., tmin) from the transition detected (by edge detection circuit 14).

The method may further include changing the operating mode of the circuit from one of the first operating mode and the second operating mode to the other operating mode in response to the first level or the second level in the input signal being maintained beyond a threshold period from a transition detected by the edge detector block.

The method as illustrated herein may include applying a signal received at the input node as a verification clock signal to the circuit in response to the input signal exhibiting N number of transitions from one of the first level and the second level to the other level and a frequency of transitions between the first level and the second level exceeding a lower threshold.

Although the specification has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. Like elements are denoted by like reference numerals throughout the various figures. Furthermore, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from the disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Accordingly, the specification and drawings are to be regarded only as illustrative of the present disclosure as defined in the appended claims, and are contemplated to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.

Claims (20)

1.A circuit, comprising:

An input node configured to receive an input signal having a first level value and a second level value, an

Logic circuitry coupled to the input node and configured to receive the input signal, the logic circuitry comprising:

A finite state machine circuit configured to configure an operation mode of the circuit to a first operation mode or a second operation mode based on the input signal being at the first level value or the second level value, respectively,

An edge detection circuit configured to detect a transition between the first level value and the second level value and to pass a corresponding transition signal to the finite state machine circuit based on the transition, and

A timer circuit configured to determine whether the first level value or the second level value has been maintained for more than a threshold period of time, the threshold period of time beginning with a transition detected by the edge detection circuit, and wherein the finite state machine circuit is configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time.

2. The circuit of claim 1, further comprising processing circuitry, wherein the finite state machine circuitry is configured to correlate the input signal to a verification clock signal based on determining, by the processing circuitry, that the input signal includes a number N of transitions between the first level value and the second level value, and determining, by the processing circuitry, that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

3. The circuit of claim 2, wherein the finite state machine circuit is configured to:

correlating the input signal to a verification clock signal, an

The operating mode of the circuit is set to only one of the first operating mode or the second operating mode, or the circuit is maintained at only one of the first operating mode or the second operating mode.

4. The circuit of claim 2, wherein the circuit is configured to correlate the input signal as a verification clock signal for only one of the first or second modes of operation.

5. The circuit of claim 4, wherein the finite state machine circuit is configured to:

correlating the input signal to a verification clock signal, an

The operation mode is set to only one of the first operation mode or the second operation mode, or is maintained at only one of the first operation mode or the second operation mode.

6. The circuit of claim 1, wherein the finite state machine circuit being configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained beyond the threshold period comprises changing the operating mode of the circuit based on the timer circuit determining that the first level value has been maintained beyond the threshold period, and

The operating mode of the circuit is maintained based on the timer circuit determining that the second level value has been maintained beyond the threshold period.

7. The circuit of claim 1, further comprising:

a counter circuit configured to determine that the input signal includes a number N of transitions between the first level value and the second level value, and

A checking circuit configured to determine that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

8. A method of operating a circuit, the method comprising:

causing the input node to be configured to receive an input signal having a first level value and a second level value;

setting an operation mode of the circuit to a first operation mode or a second operation mode based on the input signal being at the first level value or the second level value, respectively;

Detecting a transition between the first level value and the second level value;

Determining whether the first level value or the second level value is maintained for more than a threshold period of time, and

The operating mode is changed based on determining that the first level value or the second level value has been maintained beyond the threshold period.

9. The method of claim 8, further comprising associating the input signal as a verification clock signal based on determining that the input signal includes a number N of transitions between the first level value and the second level value and determining that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

10. The method of claim 9, further comprising setting the operating mode to only one of the first operating mode or the second operating mode, or maintaining the operating mode at only one of the first operating mode or the second operating mode.

11. The method of claim 9, further comprising correlating the input signal as a verification clock signal for only one of the first or second modes of operation.

12. The method of claim 11, further comprising:

Determining a time difference between two consecutive rising edges of said input signal, and

The verification clock signal is reset to be associated with the input signal based on determining that the time difference is greater than a threshold.

13. The method of claim 11, further comprising setting the operating mode to only one of the first operating mode or the second operating mode, or maintaining the operating mode at only one of the first operating mode or the second operating mode.

14. The method of claim 8, changing the operating mode based on determining that the first level value or the second level value has been maintained beyond the threshold period comprises:

changing the operating mode based on determining that the first level value has been maintained beyond the threshold period of time, and

The operating mode is maintained based on determining that the second level value has been maintained beyond the threshold period.

15. A system, comprising:

a clock circuit configured to generate a signal having a first level value and a second level value, and

A circuit coupled to the clock circuit and configured to receive the signal at an input of the circuit, the circuit comprising logic configured to receive the signal, the logic comprising:

A finite state machine circuit configured to configure an operating mode of the circuit to a first operating mode or a second operating mode based on the signal being at the first level value or the second level value, respectively,

An edge detection circuit configured to detect a transition between the first level value and the second level value and to pass a corresponding transition signal to the finite state machine circuit based on the transition, and

A timer circuit configured to determine whether the first level value or the second level value has been maintained for more than a threshold period of time, the threshold period of time beginning with a transition detected by the edge detection circuit, and wherein the finite state machine circuit is configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time.

16. The system of claim 15, wherein the logic circuit further comprises processing circuitry, wherein the finite state machine circuitry is configured to correlate the signal to a verification clock signal based on determining, by the processing circuitry, that the signal includes a number N of transitions between the first level value and the second level value, and determining, by the processing circuitry, that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

17. The system of claim 16, wherein the finite state machine circuitry is configured to:

correlating the signals as verify clock signals, an

The operating mode of the circuit is set to only one of the first operating mode or the second operating mode, or the circuit is maintained at only one of the first operating mode or the second operating mode.

18. The system of claim 16, wherein the circuitry is configured to correlate the signal as a verification clock signal for only one of the first or second modes of operation.

19. The system of claim 15, wherein the finite state machine circuit being configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained beyond the threshold period comprises changing the operating mode of the circuit based on the timer circuit determining that the first level value has been maintained beyond the threshold period, and

The operating mode of the circuit is maintained based on the timer circuit determining that the second level value has been maintained beyond the threshold period.

20. The system of claim 15, wherein the logic circuit further comprises:

a counter circuit configured to determine that the signal includes a number N of transitions between the first level value and the second level value, and

A checking circuit configured to determine that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.