CN114448369A - Amplifying circuits, related chips and electronic devices - Google Patents

Abstract

The application discloses an amplifying circuit, a related chip and an electronic device. The amplifying circuit comprises a current balancing unit, a biasing unit, an output unit, a P-type transistor differential amplifying unit, an N-type transistor replica differential input unit, a P-type transistor replica differential input unit and an N-type transistor differential amplifying unit, wherein the P-type transistor differential amplifying unit, the N-type transistor replica differential input unit and the N-type transistor differential amplifying unit respectively receive a first input voltage signal and a second input voltage signal. The current balancing unit balances currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit. The bias unit outputs a first bias current to the P-type transistor differential amplifier unit and the N-type transistor replica differential input unit together, and provides a second bias current to the P-type transistor replica differential input unit and the N-type transistor differential amplifier unit together. The output unit generates output end current according to a plurality of current signals generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit.

Description

Amplifying circuits, related chips and electronic devices

technical field

The present application relates to an amplifier circuit, in particular to an amplifier circuit with stable output terminal current.

Background technique

Because the clock signal generated by the phase-locked loop has the advantages of low noise and high stability, it is widely used in various chips, and gradually develops in the direction of low power consumption and high integration. In the charge pump phase-locked loop, the performance of the charge pump plays an important role in suppressing the reference spur of the phase-locked loop. In the prior art, in order to reduce the current mismatch caused by the charging and discharging of the parasitic capacitance and the voltage jitter at the output end of the charge pump in the charge pump, an amplifier is often used for feedback to clamp the output end of the charge pump. , thereby enhancing the current matching accuracy of the charge pump.

Since the charge pump requires small quiescent current and fast switching speed, there are also higher requirements for the amplifier used to provide feedback, such as the amplifier needs to have a larger common-mode input range, higher drive capability, lower characteristics such as power consumption and large bandwidth to suppress the impact of the amplifier on the operating point of the charge pump. That is to say, how to provide an appropriate amplifier to reduce the influence on the operating point of the charge pump has become a problem to be solved.

SUMMARY OF THE INVENTION

One of the objectives of the present application is to disclose an amplifier circuit, a related chip and an electronic device to solve the above problems.

An embodiment of the present application provides an amplifying circuit. The amplifying circuit includes a P-type transistor differential amplifying unit, an N-type transistor replica differential input unit, a P-type transistor replica differential input unit, an N-type transistor differential amplifying unit, a current balance unit, a bias unit and an output unit. The P-type transistor differential amplifying unit is used for receiving a first input voltage signal and a second input voltage signal. The N-type transistor replicates the differential input unit for receiving the first input voltage signal and the second input voltage signal. The P-type transistor replicates the differential input unit for receiving the first input voltage signal and the second input voltage signal. The N-type transistor differential amplifying unit is used for receiving the first input voltage signal and the second input voltage signal. The current balancing unit is used for balancing the currents generated by the P-type transistor differential amplifying unit and the N-type transistor differential amplifying unit. The bias unit is used for jointly providing a first bias current to the P-type transistor differential amplifying unit and the N-type transistor replica differential input unit, and replicating the P-type transistor differential input unit and the N-type transistor The transistor differential amplifying units jointly provide a second bias current. The output unit is used for generating an output current according to a plurality of current signals generated by the P-type transistor differential amplifying unit and the N-type transistor differential amplifying unit.

The current value of the first bias current is the same as the current value of the second bias current. When the common-mode voltages of the first input voltage signal and the second input voltage signal change, the current change corresponding to the P-type transistor differential amplifying unit and the P-type transistor replica differential input unit is the same as the corresponding current change. The current variation corresponding to the N-type transistor replica differential input unit and the N-type transistor differential amplifying unit has the same variation amount and opposite variation direction, so that the output current generated by the output unit remains stable.

Another embodiment of the present application provides a chip including an amplification circuit and a power supply circuit, the power supply circuit is connected to the amplification circuit, and the power supply circuit supplies power to the amplification circuit, for example, provides a stable power supply voltage VDD for the amplification circuit.

Another embodiment of the present application provides an electronic device, including the chip and a housing, where the chip is disposed inside the housing.

The amplifying circuit, related chip and electronic device provided by the embodiments of the present application can utilize complementary single-stage input common-source amplifier groups to provide gain, and balance the common-source through a current branch circuit and a current balancing unit connected in parallel with the common-source amplifiers The current of the amplifier group, so the output current can be kept stable, thereby reducing the impact on the operating point of the charge pump.

Description of drawings

FIG. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the present application.

FIG. 2 is a circuit diagram of the amplifier circuit of FIG. 1 .

FIG. 3 is a schematic diagram of the current of the amplifier circuit of FIG. 1 when the common mode voltage of the first input voltage signal and the second input voltage signal is half of the power supply voltage.

FIG. 4 is a schematic diagram of the current of the amplifier circuit of FIG. 1 when the common mode voltage of the first input voltage signal and the second input voltage signal is the power supply voltage.

FIG. 5 is a schematic diagram of an amplifying circuit according to another embodiment of the present application.

FIG. 6 is a circuit diagram of a P-type transistor differential amplifying unit according to an embodiment of the present application.

FIG. 7 is a circuit diagram of an N-type transistor replica differential input unit according to an embodiment of the present application.

Detailed ways

The following disclosure provides various implementations, or illustrations, that can be used to implement various features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. As can be appreciated, these descriptions are exemplary only, and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments in which the first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Notwithstanding that the numerical ranges and parameters setting forth the broader scope of the application are approximations, the numerical values set forth in the specific examples have been reported as precisely as possible. Any numerical value, however, inherently contains the standard deviation resulting from individual testing methods. As used herein, "about" generally means within plus or minus 10%, 5%, 1%, or 0.5% of the actual value of a particular value or range. Alternatively, the word "about" means that the actual value lies within an acceptable standard error of the mean, as considered by one of ordinary skill in the art to which this application pertains. It should be understood that all ranges, quantities, numerical values and percentages used herein (for example, to describe material amounts, time durations, temperatures, operating conditions, quantity ratios and other similar) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the accompanying claims are approximate numerical values and may be changed as required. At a minimum, these numerical parameters should be construed to mean the number of significant digits indicated and the numerical values obtained by applying ordinary rounding. Numerical ranges are expressed herein as from one endpoint to the other or between the endpoints; unless otherwise indicated, the numerical ranges recited herein are inclusive of the endpoints.

FIG. 1 is a schematic diagram of an amplifying circuit 100 according to an embodiment of the present application. The amplifier circuit 100 includes a bias unit 110 , a P-type transistor differential amplifying unit 120 , an N-type transistor replica differential input unit 130 , a P-type transistor replica differential input unit 140 , an N-type transistor differential amplifying unit 150 , a current balance unit 160 and an output unit 170. In this embodiment, the amplifying circuit 100 can be designed as a chip, and can be arranged in an electronic device according to system requirements.

In some embodiments, in order to enable the amplifier to provide smaller current consumption and larger bandwidth, a single-stage common-source amplifier is used. However, the output current of the single-stage common-source amplifier is easily affected by the load, for example, when the load is relatively heavy When it is large, it may cause the single-stage common source amplifier to turn off and not work properly. To solve this problem, in this embodiment, the amplifying circuit 100 can use a single-stage input-stage common-source amplifier to provide gain, and add a current branch by duplicating a pair of tubes, so that the amplifying circuit 100 can provide a relatively stable output current. For example, in the present embodiment, the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 are complementary input stage common-source amplifiers, and the P-type transistor replicates the differential input unit 140 and the N-type transistor replicates the differential input The unit 130 is a current branch circuit connected in parallel with the input stage common source amplifier, and the P-type transistor replica differential input unit 140 can use transistors of the same type and the same aspect ratio as the P-type transistor differential amplifying unit 120, and N-type transistors The replica differential input unit 130 can use transistors of the same type and the same aspect ratio as the N-type transistor differential amplifying unit 150 , so the N-type transistor replica differential input unit 130 can generate a current corresponding to and complementary to the P-type transistor differential amplifying unit 120 While the P-type transistor replicates the differential input unit 140 to generate a corresponding and complementary current change to the N-type transistor differential amplifying unit 150 . In this way, the amplifying circuit 100 can have the advantages of less current consumption and wider frequency band. Furthermore, since the current branch provided by the P-type transistor replica differential input unit 140 and the N-type transistor replica differential input unit 130 can compensate the current generated by the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 , and Therefore, the output current of the amplifying circuit 100 can be maintained in a relatively stable state without affecting the working state of the input pair transistors, such as the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 .

In this embodiment, the P-type transistor differential amplifying unit 120 , the N-type transistor replica differential input unit 130 , the P-type transistor replica differential input unit 140 , and the N-type transistor differential amplifying unit 150 can each receive the first input voltage signal VP and the second The two input voltage signals VN can respectively conduct the first input voltage signal VP and the second input voltage signal VN into an amplified current. In addition, the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 not only have the input pair of transistors, but also have the load pair of transistors required to provide gain. However, since the main function of the N-type transistor replica differential input unit 130 and the P-type transistor replica differential input unit 140 is to replicate the branch current, only the input pair transistors can be included, and the load pair transistors can be omitted. The specific circuit structures of the P-type transistor differential amplifying unit 120 , the N-type transistor replica differential input unit 130 , the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifying unit 150 will be described in detail in the following paragraphs.

The bias unit 110 may provide bias currents required by the P-type transistor differential amplifying unit 120 , the N-type transistor replica differential input unit 130 , the P-type transistor replica differential input unit 140 , and the N-type transistor differential amplifying unit 150 . For example, the bias unit 110 can provide a first bias current IB1 and a second bias current IB2, wherein the first bias current IB1 flows into the P-type transistor differential amplifying unit 120 and the N-type transistor replica differential input unit 130 The second bias current IB2 is the total current flowing from the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifying unit 150 . In this embodiment, the current value of the first bias current IB1 and the current value of the second bias current IB2 may have the same current value.

The current balancing unit 160 can balance the currents generated by the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 , and the output unit 170 can generate a stable output current according to the current signal synthesized by the current balancing unit 160 . When the output voltage is provided through the output terminal OUT of the amplifying circuit 100 , it is not easy for the amplifying circuit 100 to be turned off due to excessive load current.

As mentioned above, in the present embodiment, the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 are complementary common-source amplifier groups, and the N-type transistor duplicates the differential input unit 130 and the P-type transistor duplicates the differential input unit 140 is a current branch circuit connected in parallel with the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 respectively. In this case, when the common-mode voltages of the first input voltage signal VP and the second input voltage signal VN change, the current changes corresponding to the P-type transistor differential amplifying unit 120 and the P-type transistor replica differential input unit 140 will change. The current variation corresponding to the N-type transistor replica differential input unit 130 and the N-type transistor differential amplifying unit 150 has the same variation amount and opposite variation direction, and the current balancing unit 160 can further balance the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150. The current generated by the N-type transistor differential amplifying unit 150 enables the output current generated by the output unit 170 to remain stable without changing with the change of the common mode voltage. In addition, since the amplifying circuit 100 may not use an additional feedback circuit, the required area is small, the bandwidth is large, and the power consumption is also low. In some embodiments, the amplifier circuit 100 can be used in a phase locked loop to provide feedback required by the charge pump.

FIG. 2 is a circuit diagram of the amplifier circuit 100 . In FIG. 2 , the bias unit 110 may include a first current mirror 112 , a second current mirror 114 and a third current mirror 116 . The first current mirror 112 can generate the first replica current IP1 according to the received reference current IB0. The second current mirror 114 may include a plurality of P-type transistors, and may generate the first bias current IB1 according to the first replica current IP1. The third current mirror 116 may include a plurality of N-type transistors, and may generate a second bias current IB2 according to the first replica current IP1.

For example, the first current mirror 112 may include a first N-type transistor MN1 and a second N-type transistor MN2, and the second current mirror may include a first P-type transistor MP1, a second P-type transistor MP2 and a third P-type transistor MP3, and the third current mirror 116 may include a third N-type transistor MN3 and a fourth N-type transistor MN4.

The first N-type transistor MN1 has a first terminal, a second terminal and a control terminal, the first terminal of the first N-type transistor MN1 can receive the reference current IB0, and the second terminal of the first N-type transistor MN1 is coupled to the ground voltage GND , and the control terminal of the first N-type transistor MN1 is coupled to the first terminal of the first N-type transistor MN1. In this embodiment, the reference current IB0 can be provided by the current source CS1. The second N-type transistor MN2 has a first terminal, a second terminal and a control terminal, the second terminal of the second N-type transistor MN2 is coupled to the ground voltage GND, and the control terminal of the second N-type transistor MN2 is coupled to the first terminal The control terminal of the N-type transistor MN1.

The first P-type transistor MP1 has a first terminal, a second terminal and a control terminal. The first terminal of the first P-type transistor MP1 is coupled to the power supply voltage VDD, and the second terminal of the first P-type transistor MP1 is coupled to the second terminal. The first terminal of the N-type transistor MN2 and the control terminal of the first P-type transistor MP1 are coupled to the second terminal of the first P-type transistor MP1. The second P-type transistor MP2 has a first terminal, a second terminal and a control terminal, the first terminal of the second P-type transistor MP2 is coupled to the power supply voltage VDD, and the control terminal of the second P-type transistor MP2 is coupled to the first terminal The control terminal of the P-type transistor MP1. The third N-type transistor MN3 has a first terminal, a second terminal and a control terminal. The first terminal of the third N-type transistor MN3 is coupled to the second terminal of the second P-type transistor MP2. The second terminal is coupled to the ground voltage GND, and the control terminal of the third N-type transistor MN3 is coupled to the first terminal of the third N-type transistor MN3.

In this embodiment, in the first current mirror 112 , the second N-type transistor MN2 can replicate the reference current IB0 received by the first N-type transistor MN1 to generate the first replicated current IP1 , while in the second current mirror 114 , the second P-type transistor MP2 can copy the current IP1 flowing through the first P-type transistor MP1, and since the third N-type transistor MN3 and the second P-type transistor MP2 are connected in series, the third N-type transistor MN3 and the second The P-type transistor MP2 will flow the same current, eg, the same current as the current IP1, and can be used to provide the bias voltages VB1 and VB2 required by the third P-type transistor MP3 and the fourth N-type transistor MN4, respectively. As shown in FIG. 2 , the third P-type transistor MP3 has a first terminal, a second terminal and a control terminal, the first terminal of the third P-type transistor MP3 is coupled to the power supply voltage VDD, and the second terminal of the third P-type transistor MP3 The terminal can provide the first bias current IB1, and the control terminal of the third P-type transistor MP3 is coupled to the control terminal of the second P-type transistor MP2 to receive the bias voltage VB1. That is to say, in the second current mirror 114, the control terminals of the third P-type transistor MP3 and the second P-type transistor MP2 can receive the same voltage, so the third P-type transistor MP3 and the second P-type transistor MP2 are the same The current flowing through the first P-type transistor MP1 can be replicated to generate the first bias current IB1.

The fourth N-type transistor MN4 has a first terminal, a second terminal and a control terminal, the first terminal of the fourth N-type transistor MN4 can provide the second bias current IB2, and the second terminal of the fourth N-type transistor MN4 is coupled to The ground voltage GND, and the control terminal of the fourth N-type transistor MN4 is coupled to the control terminal of the third N-type transistor MN3 to receive the bias voltage VB2. That is to say, in the third current mirror 116, the control terminals of the fourth N-type transistor MN4 and the third N-type transistor MN3 can receive the same voltage, so the fourth N-type transistor MN4 can replicate the flow through the third N-type transistor MN4. The current of the transistor MN3 thus generates the second bias current IB2.

In addition, the P-type transistor differential amplifying unit 120 may include a fourth P-type transistor MP4, a fifth P-type transistor MP5, a sixth N-type transistor MN6 and a seventh N-type transistor MN7, wherein the fourth P-type transistor MP and the fifth P-type transistor MP5 The N-type transistor MP5 can receive the first input voltage signal VP and the second input voltage signal VN respectively, and according to the first input voltage signal VP and the second input voltage signal VN, generate a transduction amplification current to the sixth N-type transistor MN6 and the seventh N-type transistor MN6 N-type transistor MN7.

As shown in FIG. 2 , the fourth P-type transistor MP4 has a first terminal, a second terminal and a control terminal. The first terminal of the fourth P-type transistor MP4 is coupled to the second terminal of the third P-type transistor MP3. The control terminal of the fourth P-type transistor MP4 can receive the first input voltage signal VP. The fifth P-type transistor MP5 has a first terminal, a second terminal and a control terminal. The first terminal of the fifth P-type transistor MP5 is coupled to the second terminal of the third P-type transistor MP3. The fifth P-type transistor MP5 controls the The terminal can receive the second input voltage signal VN. The sixth N-type transistor MN6 has a first terminal, a second terminal and a control terminal. The first terminal of the sixth N-type transistor MN6 is coupled to the second terminal of the fourth P-type transistor MP4. The sixth N-type transistor MN6 has a first terminal. The two terminals are coupled to the ground voltage GND, and the control terminal of the sixth N-type transistor MN6 is coupled to the first terminal of the sixth N-type transistor MN6. The seventh N-type transistor MN7 has a first terminal, a second terminal and a control terminal. The first terminal of the seventh N-type transistor MN7 is coupled to the second terminal of the fifth P-type transistor MP5. The seventh N-type transistor MN7 has a first terminal. The two terminals are coupled to the ground voltage GND, and the control terminal of the seventh N-type transistor MN7 is coupled to the first terminal of the seventh N-type transistor MN7.

In this embodiment, the P-type transistor differential amplifying unit 120 and the N-type transistor replica differential input unit 130 have input pair transistors of complementary types, so when the common mode voltage of the first input voltage signal VP and the second input voltage signal VN is generated When changing, the current change generated by the P-type transistor differential amplifying unit 120 and the current change generated by the N-type transistor replicating the differential input unit 130 have the opposite direction of change. For example, when the current generated by the P-type transistor differential amplifier unit 120 increases, the current generated by the N-type transistor replica differential input unit 130 decreases, and vice versa. Furthermore, since the P-type transistor differential amplifying unit 120 and the N-type transistor replica differential input unit 130 can be biased by the first bias current IB1 together, even if the P-type transistor differential amplifying unit 120 and the N-type transistor replicating the differential input unit 130 The respective generated currents may vary due to changes in the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN, but both the P-type transistor differential amplifying unit 120 and the N-type transistor replicate the differential input unit 130. The sum of the currents remains the same.

As shown in FIG. 2 , the N-type transistor replica differential input unit 130 may include a tenth N-type transistor MN10 and an eleventh N-type transistor MN11 . The tenth N-type transistor MN10 has a first terminal, a second terminal and a control terminal, the first terminal of the tenth N-type transistor MN10 is coupled to the second terminal of the third P-type transistor MP3, and the tenth N-type transistor MN10 has a first terminal. The control terminal can receive the first input voltage signal VP. The eleventh N-type transistor MN11 has a first terminal, a second terminal and a control terminal, the first terminal of the eleventh N-type transistor MN11 is coupled to the second terminal of the third P-type transistor MP3, and the eleventh N-type transistor The second terminal of the MN11 is coupled to the second terminal of the tenth N-type transistor MN10, and the control terminal of the eleventh P-type transistor MN11 can receive the second input voltage signal VN.

In this embodiment, the third current mirror 116 of the bias unit 110 may further include a fifth N-type transistor MN5 to provide the bias current IB3 to the N-type transistor replicating the differential input unit 130 , so that the N-type transistor replicating the differential input unit 130 Correspondingly generate and output the bias current IB3. The fifth N-type transistor MN5 has a first terminal, a second terminal and a control terminal. The first terminal of the fifth N-type transistor MN5 is coupled to the second terminal of the eighth N-type transistor MN8 to provide a bias current IB3. The second terminal of the N-type transistor MN5 is coupled to the ground voltage GND, and the control terminal of the fifth N-type transistor MN5 is coupled to the control terminal of the third N-type transistor MN3 to receive the bias voltage VB2.

In addition, in this embodiment, the bias unit 110 can provide the second bias current IB2 to the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifying unit 150 through the fourth N-type transistor MN4, so that the P-type transistor replicates The total output current of the differential input unit 140 and the N-type transistor differential amplifying unit 150 is the second bias current IB2.

As shown in FIG. 2 , the P-type transistor replica differential input unit 140 includes a sixth P-type transistor MP6 and a seventh P-type transistor MP7 . The sixth P-type transistor MP6 has a first terminal, a second terminal and a control terminal, the second terminal of the sixth P-type transistor MP6 is coupled to the first terminal of the fourth N-type transistor MN4, and the sixth P-type transistor MP6 has a The control terminal can receive the first input voltage signal VP. The seventh P-type transistor MP7 has a first terminal, a second terminal and a control terminal. The first terminal of the seventh P-type transistor MP7 is coupled to the first terminal of the sixth P-type transistor MP6. The seventh P-type transistor MP7 has a first terminal. The two terminals are coupled to the first terminal of the fourth N-type transistor MN4, and the control terminal of the seventh P-type transistor MN7 can receive the second input voltage signal VN.

In addition, in this embodiment, the second current mirror 114 of the bias unit 110 may further include an eighth P-type transistor MP8 for providing the bias current IB4 required by the P-type transistor to replicate the differential input unit 140 . The eighth P-type transistor MP8 has a first terminal, a second terminal and a control terminal. The first terminal of the eighth P-type transistor MP8 is coupled to the power supply voltage VPP, and the second terminal of the eighth P-type transistor MP8 is coupled to the sixth terminal. The first terminal of the P-type transistor MP6 provides the bias current IB4, and the control terminal of the eighth P-type transistor MP8 is coupled to the control terminal of the second P-type transistor MP2 to receive the bias voltage VB1.

The N-type transistor differential amplifying unit 150 may include a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eighth N-type transistor MN8, and a ninth N-type transistor MN9. The ninth P-type transistor MP9 has a first terminal, a second terminal and a control terminal, the first terminal of the ninth P-type transistor MP9 is coupled to the power supply voltage VPP, and the control terminal of the ninth P-type transistor MP9 is coupled to the ninth P-type transistor MP9 The second terminal of the P-type transistor MP9. The tenth P-type transistor MP10 has a first terminal, a second terminal and a control terminal, the first terminal of the tenth P-type transistor MP10 is coupled to the power supply voltage VPP, and the control terminal of the tenth P-type transistor MP10 is coupled to the tenth P-type transistor MP10 The second terminal of the P-type transistor MP10. The eighth N-type transistor MN8 has a first terminal, a second terminal and a control terminal. The first terminal of the eighth N-type transistor MN8 is coupled to the second terminal of the ninth P-type transistor MP9. The eighth N-type transistor MN8 has a first terminal. The two terminals are coupled to the first terminal of the fourth N-type transistor MN4, and the control terminal of the eighth N-type transistor MN8 can receive the first input voltage signal VP. The ninth N-type transistor MN9 has a first terminal, a second terminal and a control terminal. The first terminal of the ninth N-type transistor MN9 is coupled to the second terminal of the tenth P-type transistor MP10. The ninth N-type transistor MN9 has a first terminal. The two terminals are coupled to the first terminal of the fourth N-type transistor MN4, and the control terminal of the ninth N-type transistor MN9 can receive the second input voltage signal VN.

The current balance unit 160 includes an eleventh P-type transistor MP11 and a twelfth N-type transistor MN12. The eleventh P-type transistor MP11 has a first terminal, a second terminal and a control terminal. The first terminal of the eleventh P-type transistor MP11 is coupled to the power supply voltage VPP, and the second terminal of the eleventh P-type transistor MP11 is coupled to is connected to the first terminal of the seventh N-type transistor MN7, and the control terminal of the eleventh P-type transistor MP11 is coupled to the control terminal of the tenth P-type transistor MP10. The twelfth N-type transistor MN12 has a first terminal, a second terminal and a control terminal. The first terminal of the twelfth N-type transistor MN12 is coupled to the second terminal of the ninth P-type transistor MP9. The twelfth N-type transistor MN12 has a first terminal. The second terminal of the transistor MN12 is coupled to the ground voltage GND, and the control terminal of the twelfth N-type transistor MN12 is coupled to the control terminal of the sixth N-type transistor MN6. In this embodiment, the eleventh P-type transistor MP11 can replicate the current generated by the tenth P-type transistor MP10 to the seventh N-type transistor MN7, and the twelfth N-type transistor MN12 can replicate the current generated by the sixth N-type transistor MN6. The generated current is sent to the ninth P-type transistor MP9 to balance the currents generated by the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 .

The output unit 170 includes a twelfth P-type transistor MP12 and a thirteenth N-type transistor MN13. The twelfth P-type transistor MP12 has a first terminal, a second terminal and a control terminal, the first terminal of the twelfth P-type transistor MP12 is coupled to the power supply voltage VPP, and the second terminal of the twelfth P-type transistor MP12 is coupled to The output terminal OUT of the amplifying circuit 100, and the control terminal of the twelfth P-type transistor MP12 is coupled to the control terminal of the ninth P-type transistor MP9. The thirteenth N-type transistor MN13 has a first terminal, a second terminal and a control terminal. The first terminal of the thirteenth N-type transistor MN13 is coupled to the output terminal OUT, and the second terminal of the thirteenth N-type transistor MN13 is coupled to the output terminal OUT. At the ground voltage GND, the control terminal of the thirteenth N-type transistor MN13 is coupled to the control terminal of the seven N-type transistors MN7.

3 is a schematic diagram of the current of the amplifying circuit 100 when the first input voltage signal VP and the second input voltage signal VN are equal and the common mode voltage of the two is half of the power supply voltage VDD. In this embodiment, the aspect ratio of the third P-type transistor MP3 may be a specific multiple of the aspect ratio of the first P-type transistor MP1, for example, twice, so that the first P-type transistor MP3 flows through the first P-type transistor MP3. The bias current IB1 is twice the current flowing through the first P-type transistor MP1. In addition, in order to realize that under this common mode voltage, the replica pair tube current flowing through the N-type transistor replica differential input unit 130 can account for half of the first bias current IB1, the width of the fifth N-type transistor MN5 can be set The aspect ratio may be equal to the aspect ratio of the third N-type transistor MN3. In addition, the width-to-length ratio of the fourth N-type transistor MN4 may also be the same specific multiple of the width-to-length ratio of the third N-type transistor MN3, for example, twice, so that the second bias flowing through the fourth N-type transistor MN4 The set current IB2 is twice the current flowing through the third N-type transistor MN3. Similarly, in order to realize that under this common mode voltage, the replica pair tube current flowing through the P-type transistor replica differential input unit 140 can account for half of the second bias current IB2, an eighth P-type transistor MP8 can be provided. The width to length ratio of is equal to the width to length ratio of the first P-type transistor MP1. In this case, the current value of the first bias current IB1 is twice the current value of the bias current IB3, and the current value of the second bias current IB2 is twice the current value of the bias current IB4, And the first bias current IB1 and the second bias current IB2 may have the same current value.

In this embodiment, since the P-type transistor differential amplifying unit 120 and the N-type transistor replica differential input unit 130 jointly receive the first bias current IB1, and the current value of the bias current IB3 provided by the fifth N-type transistor MN5 is half of the current value of the first bias current IB1, so the P-type transistor differential amplifying unit 120 will also flow a current whose magnitude is half of the first bias current IB1. In addition, when the first input voltage signal VP and the second input voltage signal VN are the same, in the P-type transistor differential amplifying unit 120, the fourth P-type transistor MP4 and the fifth P-type transistor MP5 will flow through the same magnitude of In the N-type transistor replica differential input unit 130, the tenth N-type transistor MN10 and the eleventh N-type transistor MN11 will also flow a current of the same magnitude. That is to say, the fourth P-type transistor MP4, the fifth P-type transistor MP5, the tenth N-type transistor MN10 and the eleventh N-type transistor MN11 will all flow through a quarter of the first bias current IB1, that is,

Similarly, the sum of the currents output by the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifying unit 150 should be the second bias current IB2, and the bias current IB4 provided by the eighth P-type transistor MP8 is the second bias current IB4. The four N-type transistors MN4 provide half of the bias current IB2, so the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifying unit 150 each output a current whose magnitude is half of the bias current IB2. In the case where the first input voltage signal VP and the second input voltage signal VN are the same, in the P-type transistor replica differential input unit 140, the sixth P-type transistor MP6 and the seventh P-type transistor MP7 will flow currents of the same magnitude , and in the N-type transistor differential amplifying unit 150, the eighth N-type transistor MN8 and the ninth N-type transistor MN9 will also flow a current of the same magnitude. That is to say, the sixth P-type transistor MP6, the seventh P-type transistor MP7, the eighth N-type transistor MN8 and the ninth N-type transistor MN9 will all flow through a quarter of the second bias current IB2, that is,

产生与电流

等量的复制电流至第七N型晶体管MN7，而第十二N型晶体管MN12则可依据流经第六N型晶体管MN6的电流

产生与电流

等量的复制电流，并使第九P型晶体管MP9另外输出第十二N型晶体管MN12所复制产生的电流。也就是说，如图3所示，流经第九P型晶体管MP9的电流总和为

相当于二分之一倍的第二偏置电流

而流经第七N型晶体管MN7的电流总和为

相当于二分之一倍的第一偏置电流

In addition, in this embodiment, the aspect ratio of the eleventh P-type transistor MP11 is equal to that of the tenth P-type transistor MP10 , and the aspect ratio of the twelve N-type transistor MN12 is equal to that of the sixth N-type transistor MN6 The width to length ratio is equal. In this case, the eleventh P-type transistor MP11 will depend on the current flowing through the tenth P-type transistor MP10

generate with current

The same amount of replication current is applied to the seventh N-type transistor MN7, and the twelfth N-type transistor MN12 is based on the current flowing through the sixth N-type transistor MN6.

generate with current

The same amount of current is copied, and the ninth P-type transistor MP9 additionally outputs the current copied by the twelfth N-type transistor MN12. That is to say, as shown in FIG. 3 , the sum of the currents flowing through the ninth P-type transistor MP9 is

Equivalent to one-half the second bias current

The sum of the currents flowing through the seventh N-type transistor MN7 is

Equivalent to one-half the first bias current

In this embodiment, the aspect ratio of the twelve P-type transistors MP12 may be four times that of the ninth P-type transistor MP9, and the aspect ratio of the thirteen N-type transistors MN13 may be the seventh N-type transistor. Four times the aspect ratio of the MN7. In this case, the twelfth P-type transistor MP12 will generate twice the second bias current IB2, namely 2IB2 according to the current flowing through the ninth P-type transistor MP9, and the thirteenth N-type transistor MN13 will According to the current flowing through the seventh N-type transistor MN7, twice the first bias current IB1, that is, 2IB1, is generated. Since the first bias current IB1 and the second bias current IB2 have substantially the same current value, the output current generated by the output unit 170 is substantially twice the first bias current IB1.

In addition, since the amplifier circuit 100 uses the complementary common-source amplifier group and the parallel current branch circuit, and the current balance unit 160 is used to balance the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150, the Therefore, when the common mode voltage of the first input voltage signal VP and the second input voltage signal VN changes, the current at the output terminal of the output unit 170 can still be maintained.

4 is a schematic diagram of the current of the amplifying circuit 100 when the first input voltage signal VP and the second input voltage signal VN are equal and the common mode voltage of the two is the power supply voltage VDD. As shown in FIG. 4 , when the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN becomes the power supply voltage VDD, both the P-type transistors MP4 and MP5 in the P-type transistor differential amplifying unit 120 will be turned off . Similarly, the P-type transistors MP6 and MP7 in the P-type transistor replica differential input unit 140 will be turned off

相对地，第十一P型晶体管MP11则会复制第十P型晶体管MP10所产生的电流

至第七N型晶体管MN7，因此第七N型晶体管MN7仍会流经电流

如此一来，第十二P型晶体管MP12将依据流经第九P型晶体管MP9的电流而产生两倍的第二偏置电流IB2，亦即2IB2，而第十三N型晶体管MN13则将依据流经第七N型晶体管MN7的电流而产生两倍的第二偏置电流IB2，亦即2IB2。由于第一偏置电流IB1与第二偏置电流IB2实质上具有相同的电流值，因此输出单元170所产生的输出端电流实质上仍为两倍的第一偏置电流IB1。In this case, since the fourth P-type transistor MP4 will be turned off, the sixth N-type transistor MN6 will not generate current, and the twelfth N-type transistor MN12 in the current balancing unit 160 will also not generate current. And the ninth P-type transistor MP9 will not output additional current to the twelfth N-type transistor MN12, so the ninth P-type transistor MP9 and the eighth N-type transistor MN8 will flow the same current

Conversely, the eleventh P-type transistor MP11 replicates the current generated by the tenth P-type transistor MP10

to the seventh N-type transistor MN7, so the seventh N-type transistor MN7 will still flow current

In this way, the twelfth P-type transistor MP12 will generate twice the second bias current IB2 according to the current flowing through the ninth P-type transistor MP9, that is, 2IB2, and the thirteenth N-type transistor MN13 will be generated according to the current flowing through the ninth P-type transistor MP9. The current flowing through the seventh N-type transistor MN7 generates twice the second bias current IB2, that is, 2IB2. Since the first bias current IB1 and the second bias current IB2 have substantially the same current value, the output current generated by the output unit 170 is still substantially twice that of the first bias current IB1.

In addition, when the first input voltage signal VP and the second input voltage signal VN are equal and the common mode voltage of the two is the ground voltage GND, the amplifying circuit 100 can also use the current balancing unit 160 to balance the P-type transistors according to a similar principle The current generated by the differential amplifying unit 120 and the N-type transistor differential amplifying unit 150 keeps the output current generated by the output unit 170 stable. Since the amplifying circuit 100 can maintain a constant current at the output terminal, when the amplifying circuit 100 is used in a charge pump, it will not affect the operating point of the charge pump, so that the operation of the charge pump is more accurate.

Since the amplifying circuit 100 can utilize complementary single-stage input common-source amplifier groups, such as the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150, to provide gain without using an additional feedback circuit, the required circuit Less area, more bandwidth, and lower power consumption. In addition, the amplifying circuit 100 can also balance the current of the common source amplifier group through a current branch circuit connected in parallel with the common source amplifier, such as the P-type transistor replicating the differential input unit 140 and the N-type transistor replicating the differential input unit 130, and the current balancing unit 160. Therefore, the output current can also be kept stable, thereby reducing the influence on the operating point of the charge pump. However, the present application is not limited to this. In some embodiments, in order to improve the gain of the amplifier circuit, a buffer feedback unit may also be added to the amplifier circuit.

FIG. 5 is a schematic diagram of an amplifying circuit 200 according to another embodiment of the present application. The amplifying circuit 200 and the amplifying circuit 100 have a similar structure and operate according to a similar principle, however, the amplifying circuit 200 may further include a buffer feedback unit 280 . The buffer feedback unit 280 can be coupled to the P-type transistor differential amplifying unit 220, the N-type transistor differential amplifying unit 250, the current balance unit 260 and the output unit 270, and can stabilize the P-type transistor differential amplifying unit 220 and the N-type transistor differential amplifying unit 250 generates a current and/or boosts the gain of the amplifier circuit 200 .

In addition, in some embodiments, the P-type transistor differential amplifying unit 220 , the P-type transistor replica differential input unit 240 , the N-type transistor replica differential input unit 230 , and the N-type transistor differential amplifying unit 250 may be the same as the P-type transistor differential amplifying unit 250 shown in FIG. 2 . The type transistor differential amplifying unit 120 , the P-type transistor replica differential input unit 140 , the N-type transistor replica differential input unit 130 , and the N-type transistor differential amplifying unit 150 use the same structure, but the present application is not limited thereto. In some embodiments, any one of the P-type transistor differential amplifying unit 220 , the P-type transistor replica differential input unit 240 , the N-type transistor replica differential input unit 230 , and the N-type transistor differential amplifying unit 250 may also utilize a common source The structure of the gate amplifier (CascodeAmplifier) is implemented to obtain larger input and output impedances.

FIG. 6 is a circuit diagram of a P-type transistor differential amplifying unit 220 according to an embodiment of the present application. As shown in FIG. 6 , the P-type transistor differential amplifying unit 220 may include P-type transistors MP1A, MP2A, MP3A and MP4A and N-type transistors MN1A, MN2A, MN3A and MN4A. The control terminals of the P-type transistors MP1A and MP2A can receive the first input voltage signal VP and the second input voltage signal VN respectively, while the control terminals of the P-type transistors MP3A and MP4A and the N-type transistors MN1A, MN2A, MN3A and MN4A can be respectively The corresponding bias voltages VB1A, VB2A and VB3A are received. In some embodiments, the bias voltages VB1A, VB2A, and VB3A may be provided, for example, by the bias unit 210 .

Furthermore, in some embodiments, any one of the P-type transistor differential amplifying unit 220 , the P-type transistor replica differential input unit 240 , the N-type transistor replica differential input unit 230 , and the N-type transistor differential amplifying unit 250 may also be utilized. The structure of the folded differential pair is implemented to achieve greater gain. FIG. 7 is a circuit diagram of an N-type transistor differential input unit 250 according to an embodiment of the present application.

In this embodiment, the biasing unit 210 may include a P-type transistor MP1B, the P-type transistor MP1B may receive the bias voltage VB1B, and may provide the biasing current IB2B to the P-type transistor replica differential input unit 240 and the N-type transistor differential amplifying unit 250. In this embodiment, the biasing unit 210 may further include an N-type transistor MN1B, and the N-type transistor MN1B may receive the biasing voltage VB2B and may provide another biasing current IB4B to the P-type transistor replicating the differential input unit 240 so that P The type transistor replica differential input unit 240 can correspondingly generate and output the bias current IB4B. In addition, the current value of the bias current IB4B may be half of the bias current IB2B. In this case, when the common mode voltage of the first input voltage signal VP and the second input voltage signal VN is half of the power supply voltage VDD, the The current flowing into the P-type transistor replica differential input unit 240 will be the same as the current flowing into the N-type transistor differential amplifying unit 250 , which is also half of the bias current IB2B. In some embodiments, the P-type transistor differential amplifying unit 220 is also implemented with a folded cascode circuit structure, and the bias current required by the N-type transistor replicating the differential input unit 230 can be correspondingly set according to a similar principle and bias voltage.

The N-type transistor differential amplifying unit 250 may include P-type transistors MP2B, MP3B, MP4B, MP5B, MP6B and MP7B and N-type transistors MN2B, MN3B, MN4B and MN5B. In this embodiment, in order to realize the folded structure, the N-type transistor differential amplifying unit 250 and the N-type transistor differential amplifying unit 150 in FIG. 2 can use opposite types of transistors to receive the input voltage. For example, as shown in FIG. 7 , the N-type transistors The control terminals of the P-type transistors MP2B and MP3B of the differential amplifying unit 250 can respectively receive the first input voltage signal VP and the second input voltage signal VN. P-type transistors MP4B and MP5B may receive bias voltage VB3B, while P-type transistors MP6B and MP7B may receive bias voltage VB4B. In addition, N-type transistors MN2B and MN3B can receive bias voltage VB5B, while N-type transistors MN4B and MN5B can receive bias voltage VB6B. In some embodiments, the bias voltages VB3B, VB4B, VB5B, and VB6B may be provided by the bias unit 210, for example.

且P型晶体管MP2B及MP3B将各流过四分之一的第一偏置电流IB1，即

In this embodiment, the input pairs in the N-type transistor differential amplifier unit 250, such as the P-type transistors MP2B and MP3B, may have a width-to-length ratio equal to the same type of input transistors, so that the same type of input pair can be reflected by duplicating the paired transistors. tube current changes. For example, when the first input voltage signal VP and the second input voltage signal VN are equal and their common mode voltage is half of the power supply voltage VDD, the N-type transistor differential amplifying unit 250 and the P-type transistor copy the differential input unit 240 will flow through the same current, for example one-half of the first bias current IB1, i.e.

And the P-type transistors MP2B and MP3B will each flow through a quarter of the first bias current IB1, namely

Since the N-type transistor differential amplifying unit 250 has a folded cascode circuit structure, a large gain can be achieved. However, since there are many stacked transistors, a large power consumption and a large power supply voltage may also be required. That is, the designer can implement the P-type transistor differential amplifying unit 220 , the P-type transistor replica differential input unit 240 , the N-type transistor replica differential input unit 230 , and the N-type transistor differential amplifying unit 250 with appropriate structures according to actual needs. .

To sum up, the amplifying circuits, related chips and electronic devices provided by the embodiments of the present application can utilize complementary single-stage input common-source amplifier groups to provide gain, and use a current branch circuit and a current balancing unit connected in parallel with the common-source amplifiers to provide gain. To balance the current of the common source amplifier group, it can also keep the output current stable, thereby reducing the impact on the operating point of the charge pump.

The foregoing description briefly sets forth features of certain embodiments of the application, so that those skilled in the art to which this application pertains can more fully understand the various aspects of the present disclosure. It should be apparent to those skilled in the art to which this application pertains that they can readily use the present disclosure as a basis to design or modify other processes and structures for carrying out the same purposes and/or of the embodiments described herein achieve the same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equivalent embodiments still belong to the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made without departing from the spirit of the present disclosure. with scope.

Claims (18)

1. An amplification circuit, comprising:

the P-type transistor differential amplification unit is used for receiving a first input voltage signal and a second input voltage signal;

an N-type transistor differential amplification unit for receiving the first input voltage signal and the second input voltage signal;

the P-type transistor copies a differential input unit for receiving the first input voltage signal and the second input voltage signal;

the N-type transistor copying differential input unit is used for receiving the first input voltage signal and the second input voltage signal;

the current balancing unit is used for balancing the currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit;

a bias unit for providing a first bias current to the P-type transistor differential amplifier unit and the N-type transistor replica differential input unit together, and providing a second bias current to the P-type transistor replica differential input unit and the N-type transistor differential amplifier unit together; and

the output unit is used for generating output end current according to a plurality of current signals generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit;

wherein:

the current value of the first bias current is the same as that of the second bias current; and

when the common-mode voltage of the first input voltage signal and the second input voltage signal changes, the current changes correspondingly generated by the P-type transistor differential amplification unit and the P-type transistor replica differential input unit and the current changes correspondingly generated by the N-type transistor replica differential input unit and the N-type transistor differential amplification unit have the same change amount and the opposite change direction, so that the output end current generated by the output unit is kept stable.

2. The amplification circuit of claim 1, wherein the bias unit comprises:

a first current mirror for generating a first replica current according to a received reference current; and

a second current mirror including a plurality of P-type transistors for generating the first bias current according to the first replica current; and

and a third current mirror including a plurality of N-type transistors for generating the second bias current according to the first replica current.

3. The amplification circuit of claim 2, wherein:

the first current mirror includes:

a first N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first N-type transistor being configured to receive the reference current, the second terminal of the first N-type transistor being coupled to a ground voltage, and the control terminal of the first N-type transistor being coupled to the first terminal of the first N-type transistor; and

a second N-type transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the second N-type transistor being coupled to the ground voltage and outputting the first replica current, and the control terminal of the second N-type transistor being coupled to the control terminal of the first N-type transistor;

the second current mirror includes:

a first P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first P-type transistor being coupled to a power supply voltage, the second terminal of the first P-type transistor being coupled to the first terminal of the second N-type transistor, and the control terminal of the first P-type transistor being coupled to the second terminal of the first P-type transistor;

a second P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second P-type transistor being coupled to the power voltage, and the control terminal of the second P-type transistor being coupled to the control terminal of the first P-type transistor; and

a third P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third P-type transistor being coupled to the power voltage, the second terminal of the third P-type transistor being configured to output the first bias current, and the control terminal of the third P-type transistor being coupled to the control terminal of the second P-type transistor; and

the third current mirror includes:

a third N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third N-type transistor being coupled to the second terminal of the second P-type transistor, the second terminal of the third N-type transistor being coupled to the ground voltage, and the control terminal of the third N-type transistor being coupled to the first terminal of the third N-type transistor; and

a fourth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth N-type transistor being configured to provide the second bias current, the second terminal of the fourth N-type transistor being coupled to the ground voltage, and the control terminal of the fourth N-type transistor being coupled to the control terminal of the third N-type transistor.

4. The amplifying circuit as set forth in claim 3, wherein the P-type transistor differential amplifying unit includes:

a fourth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth P-type transistor being coupled to the second terminal of the third P-type transistor, and the control terminal of the fourth P-type transistor being configured to receive the first input voltage signal;

a fifth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth P-type transistor being coupled to the second terminal of the third P-type transistor, and the control terminal of the fifth P-type transistor being configured to receive the second input voltage signal;

a sixth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth N-type transistor being coupled to the second terminal of the fourth P-type transistor, the second terminal of the sixth N-type transistor being coupled to the ground voltage, and the control terminal of the sixth N-type transistor being coupled to the first terminal of the sixth N-type transistor; and

a seventh N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh N-type transistor being coupled to the second terminal of the fifth P-type transistor, the second terminal of the seventh N-type transistor being coupled to the ground voltage, and the control terminal of the seventh N-type transistor being coupled to the first terminal of the seventh N-type transistor.

5. The amplification circuit of claim 4, wherein the P-type transistor replica differential input cell comprises:

a sixth P-type transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the sixth P-type transistor being coupled to the first terminal of the fourth N-type transistor, and the control terminal of the sixth P-type transistor being configured to receive the first input voltage signal; and

a seventh P-type transistor having a first end, a second end, and a control end, the first end of the seventh P-type transistor being coupled to the first end of the sixth P-type transistor, the second end of the seventh P-type transistor being coupled to the first end of the fourth N-type transistor, and the control end of the seventh P-type transistor being configured to receive the second input voltage signal.

6. The amplification circuit of claim 5, wherein:

the second current mirror further comprises an eighth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth P-type transistor being coupled to the power voltage, the second terminal of the eighth P-type transistor being coupled to the first terminal of the sixth P-type transistor, and the control terminal of the eighth P-type transistor being coupled to the control terminal of the second P-type transistor; and

the width-to-length ratio of the third P-type transistor is twice the width-to-length ratio of the first P-type transistor, and the channel width-to-length of the eighth P-type transistor is equal to the width-to-length ratio of the first P-type transistor.

7. The amplification circuit of claim 4, wherein the N-type transistor differential amplification unit comprises:

a ninth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the ninth P-type transistor being coupled to the power voltage, and the control terminal of the ninth P-type transistor being coupled to the second terminal of the ninth P-type transistor;

a tenth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the tenth P-type transistor being coupled to the power voltage, and the control terminal of the tenth P-type transistor being coupled to the second terminal of the tenth P-type transistor;

an eighth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth N-type transistor being coupled to the second terminal of the ninth P-type transistor, the second terminal of the eighth N-type transistor being coupled to the first terminal of the fourth N-type transistor, and the control terminal of the eighth N-type transistor being configured to receive the first input voltage signal; and

a ninth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the ninth N-type transistor being coupled to the second terminal of the tenth P-type transistor, the second terminal of the ninth N-type transistor being coupled to the first terminal of the fourth N-type transistor, and the control terminal of the ninth N-type transistor being configured to receive the second input voltage signal.

8. The amplification circuit of claim 7, wherein the N-type transistor replica differential input cell comprises:

a tenth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the tenth N-type transistor being coupled to the second terminal of the third P-type transistor, and the control terminal of the tenth N-type transistor being configured to receive the first input voltage signal; and

an eleventh N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eleventh N-type transistor being coupled to the second terminal of the third P-type transistor, the second terminal of the eleventh N-type transistor being coupled to the second terminal of the tenth N-type transistor, and the control terminal of the eleventh P-type transistor being configured to receive the second input voltage signal.

9. The amplification circuit of claim 8, wherein:

the third current mirror further comprises a fifth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth N-type transistor being coupled to the second terminal of the tenth N-type transistor, the second terminal of the fifth N-type transistor being coupled to the ground voltage, and the control terminal of the fifth N-type transistor being coupled to the control terminal of the third N-type transistor; and

the width-to-length ratio of the fourth N-type transistor is twice the width-to-length ratio of the third N-type transistor, and the width-to-length ratio of the fifth N-type transistor is equal to the width-to-length ratio of the third N-type transistor.

10. The amplification circuit of claim 7, wherein the current balancing unit comprises:

an eleventh P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eleventh P-type transistor being coupled to the power voltage, the second terminal of the eleventh P-type transistor being coupled to the first terminal of the seventh N-type transistor, and the control terminal of the eleventh P-type transistor being coupled to the control terminal of the tenth P-type transistor; and

a twelfth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth N-type transistor being coupled to the second terminal of the ninth P-type transistor, the second terminal of the twelfth N-type transistor being coupled to the ground voltage, and the control terminal of the twelfth N-type transistor being coupled to the control terminal of the sixth N-type transistor.

11. The amplification circuit of claim 10, wherein:

the width-to-length ratio of the eleventh P-type transistor is equal to the width-to-length ratio of the tenth P-type transistor; and

the width-to-length ratio of the twelve N-type transistors is equal to the width-to-length ratio of the sixth N-type transistor.

12. The amplification circuit of claim 7, wherein the output unit comprises:

a twelfth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth P-type transistor being coupled to the power voltage, the second terminal of the twelfth P-type transistor being coupled to an output terminal of the amplifying circuit, and the control terminal of the twelfth P-type transistor being coupled to the control terminal of the ninth P-type transistor; and

a thirteenth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the thirteenth N-type transistor being coupled to the output terminal, the second terminal of the thirteenth N-type transistor being coupled to the ground voltage, and the control terminal of the thirteenth N-type transistor being coupled to the control terminal of the seventh N-type transistor.

13. The amplification circuit of claim 12, wherein:

the width-to-length ratio of the twelve P-type transistors is four times that of the ninth P-type transistor; and

the thirteen N-type transistors have a width-to-length ratio four times that of the seventh N-type transistor.

14. The amplification circuit of claim 1, wherein at least one of the P-type transistor differential amplification unit, the P-type transistor replica differential input unit, the N-type transistor replica differential input unit, and the N-type transistor differential amplification unit comprises a folded differential pair structure.

15. The amplification circuit of claim 1, wherein at least one of the P-type transistor differential amplification unit and the N-type transistor differential amplification unit comprises a cascode amplifier.

16. The amplifying circuit of claim 1, further comprising a buffer feedback unit coupled to the P-type transistor differential amplifying unit, the N-type transistor differential amplifying unit and the current balancing unit for stabilizing the current generated by the P-type transistor differential amplifying unit and the N-type transistor differential amplifying unit and/or increasing the gain of the amplifying circuit.

17. A chip, comprising:

an amplifying circuit and a power supply circuit according to any one of claims 1 to 16, the power supply circuit being connected to the amplifying circuit, the power supply circuit supplying power to the amplifying circuit.

18. An electronic device, comprising:

the chip and housing of claim 17, the chip being disposed inside the housing.

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