CN114487762B

CN114487762B - Chip and userID detection circuit thereof

Info

Publication number: CN114487762B
Application number: CN202011263196.5A
Authority: CN
Inventors: 李侃; 钱永学; 孟浩; 蔡光杰; 黄鑫
Original assignee: Beijing Angrui Microelectronics Technology Co ltd
Current assignee: Beijing Angrui Microelectronics Technology Co ltd
Priority date: 2020-11-12
Filing date: 2020-11-12
Publication date: 2024-09-24
Anticipated expiration: 2040-11-12
Also published as: CN114487762A

Abstract

The application provides a chip and a userID detection circuit thereof. In the userID detection circuit, the first transistor and the second transistor have current limiting function, so that the current flowing through two resistors can be limited, namely, the current on the branch can be limited to a smaller value under the condition that the two resistors are not large, and the occupied area of the userID detection circuit is reduced on the basis of reducing the power consumption of the userID detection circuit; in addition, in the userID detection circuit, two inverters and two current mirror branches are used for realizing output, and a comparator and a bias voltage generator in the prior art are omitted, so that the power consumption and the occupied area of the userID detection circuit are further reduced.

Description

Chip and userID detection circuit thereof

Technical Field

The present invention relates to the field of power electronics, and in particular, to a chip and a userID detection circuit thereof.

Background

In general, in the design implementation of a chip, an identity code UserID needs to be set for the chip in order to identify the identity or the operating state of the chip.

In the prior art, there is a UserID detection circuit as shown in fig. 1. Five resistors, two comparators and a bias voltage generator are arranged in the detection circuit; the bias generator is used for providing bias current for the two comparators to ensure that the two comparators can work, the five resistors respectively form two voltage division branches and are combined with the two comparators to finish detection of the state of a USER_ID pin for setting a USERID mark, and then the USERID of the chip is identified.

In the UserID detection circuit, a large resistor is generally used to reduce the power consumption of the UserID detection circuit, so that the occupied area of the detection circuit is increased; in addition, in the UserID detection circuit, not only is the comparator itself lost, but also the bias current provided by the bias generator also causes the consumption of current and area, and further the power consumption and occupied area of the detection circuit are large. Therefore, how to reduce the power consumption of the UserID detection circuit and reduce the occupied area of the UserID detection circuit is a problem to be solved at present.

Disclosure of Invention

In view of the above, the present invention provides a chip and a UserID detection circuit thereof, so as to reduce the power consumption of the UserID detection circuit and reduce the occupied area of the UserID detection circuit.

In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:

In one aspect, the present application provides a userID detection circuit of a chip, including: a first transistor, a second transistor, a first current mirror leg, a second current mirror leg, a first resistor, a second resistor, a first inverter, and a second inverter; wherein:

the first transistor and the first resistor are connected in series between a power supply and a USER_ID pin of the chip;

the second transistor and the second resistor are connected in series between the USER_ID pin and ground;

The first current mirror branch and the second current mirror branch are both arranged between the power supply and the ground;

The first control end of the first current mirror branch and the first control end of the second current mirror branch are connected with the control end of the first transistor;

The second control end of the first current mirror branch and the second control end of the second current mirror branch are connected with the control end of the second transistor;

the midpoint of the first current mirror branch is connected with the input end of the first phase inverter;

The midpoint of the second current mirror branch is connected with the input end of the second inverter;

The output end of the first inverter is the first output end of the userID detection circuit, and the output end of the second inverter is the second output end of the userID detection circuit.

Optionally, the first current mirror leg includes: a third transistor and a fourth transistor; wherein:

the input end of the third transistor is connected with the power supply;

The output end of the third transistor is connected with the input end of the fourth transistor, and the connecting point is used as the midpoint of the first current mirror branch;

the output end of the fourth transistor is grounded;

The control end of the third transistor is used as a first control end of the first current mirror branch;

the control terminal of the fourth transistor is used as the second control terminal of the first current mirror branch.

Optionally, a current mirror ratio of the first transistor to the third transistor is greater than a current mirror ratio of the second transistor to the fourth transistor.

Optionally, the current mirror ratio of the first transistor to the third transistor is 2:1, and the current mirror ratio of the second transistor to the fourth transistor is 1:1.

Optionally, the second current mirror leg includes: a fifth transistor and a sixth transistor; wherein:

the input end of the fifth transistor is connected with the power supply;

The output end of the fifth transistor is connected with the input end of the sixth transistor, and the connecting point is used as the midpoint of the second current mirror branch;

the output end of the sixth transistor is grounded;

the control end of the fifth transistor is used as a first control end of the second current mirror branch;

the control terminal of the sixth transistor is used as the second control terminal of the second current mirror branch.

Optionally, a current mirror ratio of the first transistor to the fifth transistor is smaller than a current mirror ratio of the second transistor to the sixth transistor.

Optionally, the current mirror ratio of the first transistor to the fifth transistor is 1:1, and the current mirror ratio of the second transistor to the sixth transistor is 2:1.

Optionally, the transistors forming a current mirror with the first transistor in the first current mirror branch and the second current mirror branch, and the first transistor are PMOS transistors;

And the transistors forming a current mirror with the second transistor in the first current mirror branch and the second current mirror branch, and the second transistor are NMOS transistors.

Optionally, at least one current limiting transistor connected in series with the first transistor and the first resistor and having the same current direction as the first transistor is further included between the power supply and the user_id pin;

and at least one current limiting transistor which is connected with the second transistor and the second resistor in series and has the same current direction as the second transistor is also included between the USER_ID pin and the ground.

Another aspect of the application provides a chip comprising: a chip main circuit and a UserID detection circuit of the chip according to any one of the above aspects of the application.

According to the technical scheme, the invention provides a userID detection circuit. In the userID detection circuit, the first transistor and the second transistor have current limiting function, so that the current flowing through two resistors can be limited, namely, the current on the branch can be limited to a smaller value under the condition that the two resistors are not large, and the occupied area of the userID detection circuit is reduced on the basis of reducing the power consumption of the userID detection circuit; in addition, in the userID detection circuit, two inverters and two current mirror branches are used for realizing output, and a comparator and a bias voltage generator in the prior art are omitted, so that the power consumption and the occupied area of the userID detection circuit are further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a prior art UserID detection circuit;

fig. 2 and fig. 3 are schematic diagrams of two structures of a UserID detection circuit according to an embodiment of the present application;

fig. 4a, fig. 4b, and fig. 4c are schematic diagrams of three simulation experiment results of the UserID detection circuit on the detection of the user_id pin, respectively;

Fig. 5 is a schematic diagram of another structure of a UserID detection circuit according to another embodiment of the present application;

fig. 6 is a schematic structural diagram of a chip according to another embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the present application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the prior art, as shown in fig. 1, the UserID detection circuit specifically includes: bias generator, first comparator 01, second comparator 02 and five resistors (e.g., R1-R5 in fig. 1).

In the userID detection circuit, a bias generator is connected with bias ends of a first comparator 01 and a second comparator 02 and is used for providing bias current for the first comparator 01 and the second comparator 02 so as to ensure that the first comparator 01 and the second comparator 02 are in a normal working state; the first resistor R1 and the second resistor R2 are connected in series to form a first series branch, and the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are connected in series to form a second series branch; and, the first series branch and the second series branch are both arranged between the power supply VDD and the ground.

The midpoint of the first serial branch, namely the connection point of the first resistor R1 and the second resistor R2, is respectively connected with the user_id pin, the non-inverting input terminal of the first comparator 01 and the non-inverting input terminal of the second comparator 02; the first output end VREF1 of the second serial branch, namely the connection point of the third resistor R3 and the fourth resistor R4, is connected with the inverting input end of the first comparator 01 and provides a reference potential for the first comparator 01; the second output terminal VREF2 of the second series branch, i.e. the connection point of the fourth resistor R4 and the fifth resistor R5, is connected to the inverting input terminal of the second comparator 02 for providing the reference potential to the second comparator 02.

By setting the resistance values of the five resistors, the following principle can be realized:

when the user_id pin is connected to the power supply VDD, the potential of the non-inverting input terminal of the first comparator 01 is greater than the self reference potential, the output terminal CODE1 thereof outputs a high level, the potential of the non-inverting input terminal of the second comparator 02 is greater than the self reference potential, and the output terminal CODE2 thereof outputs a high level, and this state can be recorded as the first state of the user_id pin, and can be represented by CODE 1= "1", CODE 2= "1".

When the user_id pin is connected to ground, the potential of the non-inverting input terminal of the first comparator 01 is smaller than the self reference potential, the output terminal CODE1 thereof outputs a low level, the potential of the non-inverting input terminal of the second comparator 02 is smaller than the self reference potential, the output terminal CODE2 thereof outputs a low level, and the state can be recorded as a second state of the user_id pin, and can be represented by CODE 1= "0", CODE 2= "0".

When the user_id pin is in a floating state, the set relationship between the resistances of the first resistor R1 and the second resistor R2 can ensure that the potential at the connection point of the first resistor R1 and the second resistor R2 is smaller than the potential of the first output terminal VREF1 of the second serial branch and larger than the potential of the second output terminal VREF2 of the second serial branch, so that the potential at the non-inverting input terminal of the first comparator 01 is smaller than the self reference potential, the output terminal CODE1 thereof outputs a low level, the potential at the non-inverting input terminal of the second comparator 02 is larger than the self reference potential, the output terminal CODE2 thereof outputs a high level, and the state can be marked as the third state of the user_id pin, represented by CODE 1= "0", CODE 2= "1".

However, the above UserID detection circuit occupies a larger area and consumes larger power, and in order to solve the above problems, the present application provides a UserID detection circuit, whose structure is shown in fig. 2, specifically including: a first transistor M1, a second transistor M2, a first current mirror leg 10, a second current mirror leg 20, a first resistor R1, a second resistor R2, and a first inverter 30 and a second inverter 40.

In the userID detection circuit, a first transistor M1 and a first resistor R1 are connected in series between a power supply VDD and a user_ID pin of a chip, and a second transistor M2 and a second resistor R2 are connected in series between the user_ID pin of the chip and ground; and, the output terminal of the first transistor M1 may be connected to the control terminal thereof, and the input terminal of the second transistor M2 may be connected to the control terminal thereof.

Specifically, in practical applications, the series connection of the first transistor M1 and the first resistor R1 may be: as shown in fig. 2, an input end of the first transistor M1 is connected to the power supply VDD, an output end of the first transistor M1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to a user_id pin of the chip; the method can also be as follows: one end of the first resistor R1 is connected with a power supply VDD, the other end of the first resistor R1 is connected with the input end of the first transistor M1, and the output end of the first transistor M1 is connected with a user_ID pin of the chip; the two series connection modes of the first transistor M1 and the first resistor R1 may be selected according to the specific situation, and are not specifically limited herein, and are all within the protection scope of the present application.

It should be noted that, in practical application, the series connection manner of the second transistor M2 and the second resistor R2 is the same as the series connection manner of the first transistor M1 and the first resistor R1, and may be derived therefrom, which is not described in detail herein; the selection of the series connection mode of the first transistor M1 and the first resistor R1 and the selection of the series connection mode of the second transistor M2 and the second resistor R2 are independent selections, that is, they do not affect each other.

Optionally, the first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor, and in practical applications, including but not limited to the above embodiment, as long as devices capable of implementing the same function are within the protection scope of the present application, and the disclosure is not limited thereto.

In the UserID detection circuit, the first current mirror branch 10 and the second current mirror branch 20 are both disposed between the power supply VDD and ground; the first control end of the first current mirror branch 10 and the first control end of the second current mirror are connected with the control end of the first transistor M1; and the second control terminal of the first current mirror branch 10 and the second control terminal of the second current mirror are both connected to the control terminal of the second transistor M2.

The midpoint of the first current mirror leg 10 is connected to the input of the first inverter and the midpoint of the second current mirror leg 20 is connected to the input of the second inverter 40; the output terminal CODE1 of the first inverter 30 is a first output terminal of the UserID detection circuit, and the output terminal CODE2 of the second inverter 40 is a second output terminal of the UserID detection circuit.

Specifically, as shown in fig. 3, the structure of the first current mirror leg 10 specifically includes: a third transistor M3 and a fourth transistor M4.

In the first current mirror branch 10, the input end of the third transistor M3 is connected to the power supply VDD, the output end of the third transistor M3 is connected to the input end of the fourth transistor M4, and the connection point is the midpoint of the first current mirror branch 10; the output end of the fourth transistor M4 is grounded; the control terminal of the third transistor M3 serves as a first control terminal of the first current mirror leg 10; the control terminal of the fourth transistor M4 serves as a second control terminal of the first current mirror leg 10; the third transistor M3 is the same type as the first transistor M1, and is a PMOS transistor, and the fourth transistor M4 is the same type as the second transistor M2, and is an NMOS transistor.

Specifically, the structure of the second current mirror leg 20 is shown in fig. 3, and specifically includes: a fifth transistor M5 and a sixth transistor M6.

In the second current mirror branch 20, the input end of the fifth transistor M5 is connected to the power supply VDD, the output end of the fifth transistor M5 is connected to the input end of the sixth transistor M6, and the connection point is the midpoint of the second current mirror branch 20; the output end of the sixth transistor M6 is grounded; the control terminal of the fifth transistor M5 serves as a first control terminal of the second current mirror leg 20; the control terminal of the sixth transistor M6 serves as a second control terminal of the second current mirror leg 20; the fifth transistor M5 is the same type as the first transistor M1, and is a PMOS transistor, and the sixth transistor M6 is the same type as the second transistor M2, and is an NMOS transistor.

As can be seen from the above-described structures of the first current mirror branch 10 and the second current mirror branch 20, the first transistor M1 forms a current mirror with the third transistor M3 and the fifth transistor M5, respectively, and the second transistor M2 forms a current mirror with the fourth transistor M4 and the sixth transistor M6, respectively.

Therefore, the theoretical analysis of this UserID detection circuit is as follows:

when the user_id pin is connected to the power supply VDD, the first transistor M1 is not turned on, i.e., no current flows through the first resistor R1 and the first transistor M1, so that no current flows through the third transistor M3 and the fifth transistor M5 even if the drain-source voltages of the third transistor M3 and the fifth transistor M5 are high; however, at this time, the second transistor M2 is turned on, that is, a current flows through the second resistor R2 and the second transistor M2, so that even if the current flowing through the second resistor R2 and the second transistor M2 is very small, the midpoint potential of the first current mirror branch 10 and the midpoint potential of the second current mirror branch 20 can be pulled down to the ground level, so that the first inverter 30 and the second inverter 40 both output high levels, and the available CODE 1= "1", CODE 2= "1", that is, at this time, the user_id pin is in the first state.

When the user_id pin is connected to ground, the second transistor M2 is not turned on, i.e., no current flows through the second resistor R2 and the second transistor M2, so that no current flows through the fourth transistor M4 and the sixth transistor M6 even if the drain-source voltages of the fourth transistor M4 and the fifth transistor M5 are high; however, at this time, the first transistor M1 is turned on, that is, a current flows through the first resistor R1 and the first transistor M1, so that even if the current flowing through the first resistor R1 and the first transistor M1 is very small, the midpoint potential of the first current mirror branch 10 and the midpoint potential of the second current mirror branch 20 can be brought to the power supply VDD, so that the first inverter 30 and the second inverter 40 both output low level, and the available CODE 1= "0", CODE 2= "0", that is, at this time, the user_id pin is in the second state.

In order to maintain the same logic output as the UserID detection circuit in the prior art, the current mirror ratio of the first transistor M1 to the third transistor M3 is set to be greater than the current mirror ratio of the second transistor M2 to the fourth transistor M4, and the current mirror ratio of the first transistor M1 to the fifth transistor M5 is set to be smaller than the current mirror ratio of the second transistor M2 to the sixth transistor M6.

Therefore, when the user_id pin is in the floating state, the first transistor M1 and the second transistor M2 are both turned on, i.e., the first resistor R1, the first transistor M1, the second resistor R2, and the second transistor M2 have current flowing therethrough, so that the third transistor M3 and the fourth transistor M4 have current flowing therethrough, and the fifth transistor M5 and the sixth transistor M6 have current flowing therethrough, i.e., the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on; however, since the current mirror ratio of the first transistor M1 to the third transistor M3 is larger than that of the second transistor M2 to the fourth transistor M4, the voltage across the third transistor M3 is smaller than that across the fourth transistor M4, i.e., the midpoint potential of the first current mirror branch 10 is at a high level; in addition, since the current mirror ratio of the first transistor M1 to the fifth transistor M5 is smaller than the current mirror ratio of the second transistor M2 to the sixth transistor M6, the voltage across the fifth transistor M5 is greater than the voltage across the sixth transistor M6, i.e. the midpoint potential of the second current mirror branch 20 is at a low level, so the first inverter 30 outputs a low level, the second inverter 40 outputs a high level, and the available CODE 1= "0", CODE 2= "1" indicates that the user_id pin is at the third state.

Specifically, the current mirror ratio of the first transistor M1 to the third transistor M3 may be set to 2:1, the current mirror ratio of the second transistor M2 to the fourth transistor M4 may be set to 1:1, the current mirror ratio of the first transistor M1 to the fifth transistor M5 may be set to 1:1, and the current mirror ratio of the second transistor M2 to the sixth transistor M6 may be set to 2:1.

In order to verify the corresponding function of the userID detection circuit provided by the application, taking the current mirror ratio as an example, a simulation experiment is carried out on the userID detection circuit, and the experimental result is as follows:

When the user_id pin is connected to the power supply VDD, the simulation result is as shown in fig. 4a, where CODE 1= "1", CODE 2= "1", i.e., the first inverter 30 and the second inverter 40 output high levels; when the user_id pin is connected to ground, the simulation result is shown in fig. 4b, where CODE 1= "0", CODE 2= "0", i.e. the first inverter 30 and the second inverter 40 output low levels; when the user_id pin is in the floating state, the simulation result is shown in fig. 4c, where CODE 1= "0", CODE 2= "1", the first inverter 30 outputs a low level, and the second inverter 40 outputs a high level.

The foregoing is merely a preferred embodiment, and in practical applications, including but not limited to the foregoing embodiments, the present application is not limited thereto, and the present application can be applied to any case as appropriate.

It should be noted that, the setting of the current mirror ratio is only a preferred embodiment, that is, the foregoing embodiment is sampled, so that the consistency of the detection result of the user_id pin in the prior art can be ensured, and in practical applications, including but not limited to the foregoing setting manner, the setting may be determined according to the specific situation, and the setting is not limited herein, and all the setting manners are within the protection scope of the present application.

As can be seen from the above technical solution, in the UserID detection circuit provided by the present application, the first transistor M1 and the second transistor M2 have a current limiting effect, so that the current flowing through two resistors can be limited, that is, the current on the branch can be limited to a smaller value under the condition that the two resistors are not large, and thus the occupied area of the UserID detection circuit is reduced on the basis of reducing the power consumption of the UserID detection circuit; in addition, in the userID detection circuit, two inverters and two current mirror branches are used for realizing output, and a comparator and a bias voltage generator in the prior art are omitted, so that the power consumption and the occupied area of the userID detection circuit are further reduced.

Another embodiment of the present application provides a UserID detection circuit, whose structure is shown in fig. 5, further including, based on the above embodiment: two current limiting branches 50.

In the UserID detection circuit, a current limiting branch 50 is connected in series with a first transistor M1 and a first resistor R1, and the current direction is the same as that of the first transistor M1; the other current limiting branch 50 is connected in series with the second transistor M2 and the second resistor R2, and the current direction is the same as that of the second transistor M2.

It should be noted that, the connection relationship and the working principle of the other structures are the same as those of the above embodiments, and are not described here again, and reference may be made to the above description.

Specifically, as shown in fig. 5, the internal structure of the current-limiting branch 50 specifically includes: at least one current limiting transistor M. In this current limiting branch 50, when the number of current limiting transistors M is greater than 1, all current limiting transistors M are connected in series with the corresponding transistors and resistors, respectively, between the power supply VDD and the user_id pin, or between the user_id pin and ground.

For example, in the current limiting branch 50 connected in series with the first transistor M1 and the first resistor R1, it may be: all the current limiting transistors M are connected in series between the first transistor M1 and the first resistor R1, as shown in fig. 5; it may also be: all the current limiting transistors M are connected in series between the first transistor M1 and the power supply VDD; it is also possible that: all the current limiting transistors M are connected in series between the first resistor R1 and the USER_ID pin; more can be: a part of current limiting transistor M is connected in series between the first transistor M1 and the power supply VDD; the other part of the current limiting transistor M is connected in series between the first transistor M1 and the first resistor R1, which is not listed here, and is within the protection scope of the present application.

Note that, all the current limiting transistors M are transistors of the same type as the corresponding transistors; for example, the first transistor M1 is a PMOS transistor, and the current limiting transistor M connected in series between the power supply VDD and the user_id pin is also a PMOS transistor.

It should be noted that, in the UserID detection circuit provided by the present application, after the current limiting branch 50 is set, the current in the UserID detection circuit is smaller, so that the power consumption of the UserID detection circuit is reduced; in addition, after the current limiting branch 50 is set, the resistance value of the first resistor R1 or the second resistor R2 may be further reduced, so that the occupied area of the first resistor R1 or the second resistor R2 is further reduced, and further, the occupied area of the UserID detection circuit is further reduced.

Another embodiment of the present application provides a chip, whose internal structure is shown in fig. 6, specifically including: the chip main circuit 100 and the UserID detection circuit 200 provided in the above embodiment; the detection end of the userID detection circuit 200, that is, the connection point between the first resistor R1 and the second resistor R2, is connected to a user_id pin on the chip main circuit 100, and is used for detecting the state of the user_id pin on the chip main circuit 100, so as to determine the identity or the working state of the chip.

In the invention, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The above description is only of the preferred embodiment of the present invention, and is not intended to limit the present invention in any way. While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A UserID detection circuit for a chip, comprising: a first transistor, a second transistor, a first current mirror leg, a second current mirror leg, a first resistor, a second resistor, a first inverter, and a second inverter; wherein:

2. The UserID detection circuit of a chip of claim 1, wherein the first current mirror leg comprises: a third transistor and a fourth transistor; wherein:

the input end of the third transistor is connected with the power supply;

the output end of the fourth transistor is grounded;

3. The UserID detection circuit of the chip of claim 2 wherein the current mirror ratio of the first transistor to the third transistor is greater than the current mirror ratio of the second transistor to the fourth transistor.

4. The UserID detection circuit of claim 3 wherein the current mirror ratio of said first transistor to said third transistor is 2:1 and the current mirror ratio of said second transistor to said fourth transistor is 1:1.

5. The UserID detection circuit of a chip of claim 1, wherein the second current mirror leg comprises: a fifth transistor and a sixth transistor; wherein:

the input end of the fifth transistor is connected with the power supply;

the output end of the sixth transistor is grounded;

6. The UserID detection circuit of the chip of claim 5 wherein a current mirror ratio of said first transistor to said fifth transistor is less than a current mirror ratio of said second transistor to said sixth transistor.

7. The UserID detection circuit of claim 6 wherein the current mirror ratio of said first transistor to said fifth transistor is 1:1 and the current mirror ratio of said second transistor to said sixth transistor is 2:1.

8. The UserID detection circuit of a chip according to any one of claims 1-7 wherein the first and second current mirror branches, the transistors forming a current mirror with the first transistor, and the first transistor are PMOS transistors;

9. The UserID detection circuit of a chip according to any one of claims 1-7, further comprising at least one current limiting transistor connected in series with said first transistor and said first resistor and having the same current direction as said first transistor between said power supply and said user_id pin;

10. A chip, comprising: chip main circuit and UserID detection circuit of the chip according to any of claims 1-9.