CN114489220B - A low-power over-temperature protection circuit with no operational amplifier and no reference - Google Patents

Abstract

The invention discloses a low-power over-temperature protection circuit without an operational amplifier and without a reference, and relates to the fields of microelectronics and solid-state electronics. The invention mainly uses the voltage negatively correlated with the temperature as the signal input source, performs conversion in the detection circuit of the front stage, and adds a Schmitt trigger in the latter stage, thereby increasing the threshold value window. The feature of the present invention is that, by injecting temperature-related voltage and current, the competition current capability of PMOS tube and MOS tube is changed, so that the jump of input signal is related to temperature. Its structure is simple, no additional reference voltage and comparator are needed, which saves power consumption and circuit area. At the same time, it is set to an adjustable temperature protection range, which reduces the influence of power supply and process, and also increases the temperature threshold window, thus The stability of the overall circuit is guaranteed.

Description

A low-power over-temperature protection circuit with no operational amplifier and no reference

technical field

The invention relates to the fields of microelectronics and solid state electronics, in particular to circuits related to over-temperature protection in this field.

Background technique

With the increasing development of integrated circuits, their chip performance and integration have been greatly improved. At the same time, higher requirements have been put forward for the safety and reliability of chips. Ensuring the safe, stable and reliable operation of chips has become a major concern in the industry. , has received extensive attention. Among them, temperature, as one of the elements in PVT (process, voltage, temperature), is a key point that affects the stability of the chip. The power consumption of the chip and surrounding circuits during operation, the energy consumption of short circuits, load changes, and temperature changes in the surrounding environment will increase the internal temperature of the chip. If it reaches a certain threshold, it will cause irreversible damage to related devices. As a result, the life and performance of the chip will be greatly reduced, and will further affect the performance and stability of the overall system. Therefore, in the design of related chips, it is necessary to consider maintaining the operating temperature of the circuit within a certain range, so it is necessary to integrate in the chip The over-temperature protection circuit makes the whole chip give a signal to stop the system when the temperature is too high; when the temperature returns to normal, the output signal makes the system resume normal work, and a certain threshold value needs to be set between the stop work and the recovery state The window prevents the power consumption and the system from being turned on and off frequently due to the repeated jumps of the signal output, resulting in the abnormality of the overall function and the loss of components. Therefore, it can be seen that the characteristics of the over-temperature protection circuit are very important.

Some traditional over-temperature protection circuit structures are generally divided into two categories. The first type combines bipolar transistors with devices with positive temperature coefficients, such as Zener diodes, to control the switches of related circuits. , to generate the above-mentioned required control signal. This over-temperature protection circuit has a simple structure, but its precision is low, its dynamic range is poor, and it is greatly affected by the process, which may cause large errors, and it is easy to cause thermal oscillation of the output signal. ; The second type of over-temperature protection circuit usually needs a reference voltage, and at the same time needs a voltage that changes with temperature, such as the V _BE of the transistor or the voltage value of other components, and then compares the two by adding a comparator, so as to obtain the A temperature signal is required. The temperature detection of this structure is relatively accurate, but it increases the complexity of the circuit and requires an additional bandgap reference circuit and comparator, which increases the power consumption and area of the overall over-temperature protection circuit.

Contents of the invention

The present invention improves on the problems existing in the above-mentioned traditional over-temperature protection circuit method, and proposes a new circuit structure and method.

The invention is an over-temperature protection circuit without an operational amplifier and without a reference voltage, and its power consumption has certain advantages compared with the traditional structure. Its main content includes the basic detection structure unit, which is four cascaded MOS tubes, the first and the second are PMOS tubes, of which the first PMOS tube is connected to a voltage that is negatively correlated with temperature, and the second PMOS tube is connected to a voltage that is negatively correlated with temperature. Clock control signal; the third and fourth are NMOS tubes, of which the third NMOS tube is connected to the clock control signal, and the fourth PMOS tube is connected to a voltage that is negatively correlated with temperature; while the drain of the second PMOS tube, That is, the drain of the third NMOS transistor is connected to the subsequent Schmitt trigger structure through a wire, thereby generating a threshold window and avoiding repeated jumps of the output of the entire over-temperature protection system. The corresponding PMOS transistors and NMOS transistors are respectively connected in parallel at the drain and source ends of the first PMOS transistor and the fourth NMOS transistor. The number, length and width of the MOS transistors are based on the specific temperature accuracy requirements and adjustment range determines that the purpose of the structure is to

The technical solution of the present invention is a low-power over-temperature protection circuit without an operational amplifier and without a reference. The circuit includes: a pre-stage and a post-stage, and the pre-stage includes: M1 as a whole, the fifth PMOS tube M2, and the first NMOS tube M3 and M4 as a whole, wherein M1 as a whole includes: a first PMOS transistor M1a, a second PMOS transistor M1b, a third PMOS transistor M1c, a fourth PMOS transistor M1d, and M4 as a whole includes: a second NMOS transistor M4a, a third NMOS transistor M4b, The fourth NMOS transistor M4c, the fifth NMOS transistor M4d; the first PMOS transistor M1a, the fifth PMOS transistor M2, the first NMOS transistor M3, and the second NMOS transistor M4a are sequentially connected in series; the first PMOS transistor M1a, the second PMOS transistor M1b, the gates of the third PMOS transistor M1c and the fourth PMOS transistor M1d are connected together and connected to the voltage VCTAT signal that is negatively correlated with temperature; the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c, and the fourth PMOS transistor M1c The drains of the PMOS transistor M1d are connected in common; the source of the first PMOS transistor M1a is connected to the power signal VDD, and the source of the first PMOS transistor M1a is separated from the source of the second PMOS transistor M1b by a switch S1. The source of the second PMOS transistor M1b is separated from the source of the third PMOS transistor M1c by a switch S2, and the source of the third PMOS transistor M1c is separated from the source of the fourth PMOS transistor M1d by a switch S3;

The gate of the fifth PMOS transistor M2 is connected to the clock signal CLKN;

The gate of the first NMOS transistor M3 is connected to the clock signal CLK;

The gates of the second NMOS transistor M4a, the third NMOS transistor M4b, the fourth NMOS transistor M4c, and the fifth NMOS transistor M4d are commonly connected and connected to the voltage VCTAT signal that is negatively correlated with temperature; the second NMOS transistor M4a, The sources of the third NMOS transistor M4b, the fourth NMOS transistor M4c, and the fifth NMOS transistor M4d are connected together and grounded; the drain of the second NMOS transistor M4a is isolated from the drain of the third NMOS transistor M4b by a switch S4 The drain of the third NMOS transistor M4b is isolated from the drain of the fourth NMOS transistor M4c by a switch S5, and the drain of the fourth NMOS transistor M4c is separated from the drain of the fifth NMOS transistor M4d by a switch S6 isolation;

The latter stage includes: a sixth PMOS transistor M5, a seventh PMOS transistor M7, an eighth PMOS transistor M9, a sixth NMOS transistor M6, a seventh NMOS transistor M8, and an eighth NMOS transistor M10; the sixth PMOS transistor M5 The gate and the gate of the sixth NMOS transistor M6 are connected together and then connected to the drain of the fifth PMOS transistor M2; the source of the sixth PMOS transistor M5, the source of the seventh PMOS transistor M7, and the source of the eighth PMOS transistor M9 The source is commonly connected and connected to the power supply signal VDD; the drain of the sixth PMOS transistor M5, the drain of the seventh PMOS transistor M7, the gate of the eighth PMOS transistor M9, the drain of the sixth NMOS transistor M6, the drain of the seventh PMOS transistor M7 The drain of the NMOS transistor M8 and the gate of the eighth NMOS transistor M10 are connected in common; the source of the sixth NMOS transistor M6, the source of the seventh NMOS transistor M8, and the source of the eighth NMOS transistor M10 are connected in common and grounded ; The gate of the seventh PMOS transistor M7, the drain of the eighth PMOS transistor M9, the gate of the seventh NMOS transistor M8, and the drain of the eighth NMOS transistor M10 are jointly connected as the output of the over-temperature protection circuit end.

The components and the overall structure have a temperature sensor analog front-end offset calibration method based on a switched capacitor integrator. In the process of eliminating it, it needs to consume a certain period of time without requiring too much complicated circuit structure and excessive power consumption. Area, more use of its own body structure for self-calibration. In addition, compared with the traditional calibration method, it can be used in combination with it, which further optimizes the performance of the circuit, and has advantages in overall calibration efficiency and accuracy. If used alone, it also reduces additional operational amplifiers and filters.

Therefore, the present invention proposes an over-temperature protection circuit structure. Compared with the above two traditional circuit methods, the structure is simple, no additional reference voltage and comparator are needed, power consumption and circuit area are saved, and the The adjustable temperature protection range reduces the influence of power supply and process, and also increases the temperature threshold window, thus ensuring the stability of the overall circuit. The beneficial effect that the present invention proposes is, and document 1 [Li Shuzhen, Feng Quanyuan. A kind of design of low power consumption CMOS over-temperature protection circuit. Applied Science and Technology, 2017,44(01):14-17+22.] and document 2 [Ge Xingjie, Lu Feng. Design of 0.25μm CMOS New Over-temperature Protection Circuit. Electronics and Packaging, 2018, 18(06): 22-25.] Compared with the proposed over-temperature protection circuit, the over-temperature protection proposed by the present invention The implementation of the circuit structure is simple, the static power consumption is low, and at the same time, the temperature range of the over-temperature protection can be trimmed and controlled, so that the range of its variation with the voltage can be controlled even smaller.

Description of drawings

FIG. 1 is a schematic structural diagram of an over-temperature protection circuit of the present invention.

Fig. 2 is the simulation result of the over-temperature protection circuit of the present invention after the power supply voltage changes from 3.3V to 5.5V, and the influence is eliminated through circuit trimming.

Fig. 3 is a simulation result diagram of static operating current when the over-temperature protection circuit of the present invention is near the temperature trip point.

Detailed ways

Below in conjunction with accompanying drawing, describe content of the present invention in detail:

The content of the present invention and the simulation results all take the HGRACE 0.11 μm process as an example. The main content of the circuit structure based on this process in over-temperature protection and practical application is as follows; The over-temperature protection circuit is suitable for the over-temperature protection circuit that requires low power consumption, and at the same time has requirements for its complexity and area, and can be adjusted by subsequent related chips. It is triggered by the front-stage detection circuit and the rear-stage Schmitt The device is composed of two parts, in which the pre-amplifier circuit is four cascaded MOS tubes, the first and the second are PMOS tubes, and the first PMOS tube is connected to a voltage that is negatively correlated with temperature, and the second PMOS tube Connect to the clock control signal; the third and fourth are NMOS tubes, the third NMOS tube is connected to the clock control signal, the fourth PMOS tube is connected to a voltage that is negatively correlated with temperature; and the drain of the second PMOS tube , that is, the drain of the third NMOS transistor is connected to the subsequent Schmitt trigger structure through a wire, thereby generating a threshold window and avoiding repeated jumps of the output of the entire over-temperature protection system.

Its specific working mode is analyzed from the change from low temperature to high temperature. By adjusting the circuit settings reasonably, the value of the VCTAT signal is relatively large at low temperature, so the opening degree of the upper PMOS transistor M1 is not as good as that of the lower NMOS transistor M4. The middle output terminal voltage is pulled down to the GND-to-ground signal, that is, the output is low; and as the temperature gradually increases, the VCTAT signal gradually decreases, and when it reaches the critical point where the PMOS transistor M1 and the NMOS transistor M4 compete for current, the output The signal begins to reverse and jump, and the value of the VCTAT signal is relatively small at this time, so the opening degree of the lower NMOS transistor M4 is not as good as that of the upper PMOS transistor M1, so the middle output voltage is pulled up to the VDD power signal, that is, the output is high Level, the circuit completes the flip. At the same time, considering that the temperature change is relatively slow, the over-temperature protection circuit can be turned on and off regularly by setting the CLK clock signal, thereby reducing the power consumption of the overall system. When CLK is at a high level, both M2 and M3 are turned on , the front stage works normally, and when CLK is low level, both M2 and M3 are turned off, the front stage stops working, and the output is a low level signal. Usually, after determining the parameters and structure of the circuit, in the case of relatively fixed process angle, temperature, and power supply voltage, the relative ability of its competing current does not change much. Output inverted signal. Considering the voltage change and process deviation in the application, multiple MOS transistors can be connected in parallel at the positions of M1 and M4, and by adjusting their access, the pull-up capability of the PMOS transistor and the pull-down capability of the NMOS transistor can be adjusted. The shutdown temperature becomes lower, and the analysis shows that the pull-up capability of the PMOS transistor is ahead of the pull-down capability of the NMOS transistor due to process deviation and power supply voltage changes. Therefore, it is necessary to increase the parallel transistors incorporated into M4 and reduce the parallel transistors incorporated into M1. Enhance the pull-down capability, weaken the pull-up capability, and increase the temperature to maintain a low level; on the contrary, if the shutdown temperature becomes higher, it must be due to process deviation and power supply voltage changes that the pull-down capability of the NMOS tube is greater than the pull-up capability of the PMOS tube in advance, so it is necessary Increase the parallel tubes incorporated into M1, reduce the parallel tubes incorporated into M4, enhance the pull-up capability, weaken the pull-down capability, and reduce the temperature for maintaining low levels. The latter stage circuit is the basic Schmitt trigger, and its state is taken as the input signal by the output signal of the previous stage circuit. For the input signals of two different changing directions, negative decreasing and positive increasing, the Schmitt trigger has different Threshold voltage, so when the temperature changes from low to high and from high to low, that is, the input signal changes in both positive and negative directions, corresponding to different thresholds, so that the final OUT signal will have a certain hysteresis window to avoid the circuit at a temperature point Repeated jumps in the vicinity cause irreversible loss. The size of the specific hysteresis window can be adjusted according to the actual circuit application requirements on the structure of the Schmitt trigger and the parameters of the MOS tube. The hysteresis temperature set by the present invention is about 3°C. The exact value does not affect overall circuit performance.

Figure 2 is the simulation result of the over-temperature protection circuit after the power supply voltage changes from 3.3 V to 5.5 V, and the influence is eliminated through circuit trimming. The principle is as analyzed above. It can be seen that under the power supply voltage of 3.3 V and 5.5 V, the circuit can complete the jump, and at the same time, the error change of the shutdown temperature can be adjusted to within 1 °C after trimming.

Figure 3 shows the static operating current of the total circuit when the over-temperature protection circuit works at a power supply voltage of 3.3 V, which is about 2.27 μA. It can be seen that the total circuit current will suddenly increase when the level is reversed, but will return to low afterward. power state.

The performance comparison of the over-temperature protection circuit is shown in Table 1 below.

Table 1: Comparison of over-temperature protection circuits

Document 1 Document 2 this invention Process/μm 0.18 0.25 0.11 structure and whether there is an op amp complex structure, yes Moderate structure, no simple structure, no Static power consumption/μA 3.12 / 2.27 Hysteresis temperature/℃ 12.11 twenty one 3.00 Influence of power supply voltage on shutdown point/°C 1.75 1.7 less than 1

Claims (1)

1. A low-power over-temperature protection circuit with no operational amplifier and no reference, the circuit includes: a pre-stage and a post-stage, and the pre-stage includes: M1 as a whole, the fifth PMOS transistor M2, the first NMOS transistors M3 and M4 As a whole, M1 as a whole includes: the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c, the fourth PMOS transistor M1d, and the M4 as a whole includes: the second NMOS transistor M4a, the third NMOS transistor M4b, the fourth NMOS transistor The tube M4c, the fifth NMOS tube M4d; the first PMOS tube M1a, the fifth PMOS tube M2, the first NMOS tube M3, and the second NMOS tube M4a are sequentially connected in series; the first PMOS tube M1a, the second PMOS tube M1b, the The gates of the three PMOS transistors M1c and the fourth PMOS transistor M1d are connected together and connected to the voltage VCTAT signal that is negatively correlated with temperature; the first PMOS transistor M1a, the second PMOS transistor M1b, the third PMOS transistor M1c, and the fourth PMOS transistor M1d The drain of the first PMOS transistor M1a is connected to the power supply signal VDD, the source of the first PMOS transistor M1a is separated from the source of the second PMOS transistor M1b by a switch S1, and the second PMOS transistor The source of M1b is separated from the source of the third PMOS transistor M1c by a switch S2, and the source of the third PMOS transistor M1c is separated from the source of the fourth PMOS transistor M1d by a switch S3; The gate of the fifth PMOS transistor M2 is connected to the clock signal CLKN; The gate of the first NMOS transistor M3 is connected to the clock signal CLK; The gates of the second NMOS transistor M4a, the third NMOS transistor M4b, the fourth NMOS transistor M4c, and the fifth NMOS transistor M4d are commonly connected and connected to the voltage VCTAT signal that is negatively correlated with temperature; the second NMOS transistor M4a, The sources of the third NMOS transistor M4b, the fourth NMOS transistor M4c, and the fifth NMOS transistor M4d are connected together and grounded; the drain of the second NMOS transistor M4a is isolated from the drain of the third NMOS transistor M4b by a switch S4 The drain of the third NMOS transistor M4b is isolated from the drain of the fourth NMOS transistor M4c by a switch S5, and the drain of the fourth NMOS transistor M4c is separated from the drain of the fifth NMOS transistor M4d by a switch S6 isolation; The latter stage includes: a sixth PMOS transistor M5, a seventh PMOS transistor M7, an eighth PMOS transistor M9, a sixth NMOS transistor M6, a seventh NMOS transistor M8, and an eighth NMOS transistor M10; the sixth PMOS transistor M5 The gate and the gate of the sixth NMOS transistor M6 are connected together and then connected to the drain of the fifth PMOS transistor M2; the source of the sixth PMOS transistor M5, the source of the seventh PMOS transistor M7, and the source of the eighth PMOS transistor M9 The source is commonly connected and connected to the power supply signal VDD; the drain of the sixth PMOS transistor M5, the drain of the seventh PMOS transistor M7, the gate of the eighth PMOS transistor M9, the drain of the sixth NMOS transistor M6, the drain of the seventh PMOS transistor M7 The drain of the NMOS transistor M8 and the gate of the eighth NMOS transistor M10 are connected in common; the source of the sixth NMOS transistor M6, the source of the seventh NMOS transistor M8, and the source of the eighth NMOS transistor M10 are connected in common and grounded ; The gate of the seventh PMOS transistor M7, the drain of the eighth PMOS transistor M9, the gate of the seventh NMOS transistor M8, and the drain of the eighth NMOS transistor M10 are jointly connected as the output of the over-temperature protection circuit end.

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