CN114496025B

CN114496025B - 12T anti-radiation SRAM memory cell based on polarity reinforcing technology

Info

Publication number: CN114496025B
Application number: CN202210068744.1A
Authority: CN
Inventors: 赵强; 李正亚; 高珊; 郝礼才; 彭春雨; 卢文娟; 吴秀龙; 蔺智挺; 陈军宁
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2025-07-29
Anticipated expiration: 2042-01-20
Also published as: CN114496025A

Abstract

The present invention discloses a 12T radiation-resistant SRAM memory cell based on polarity reinforcement technology, comprising four NMOS transistors and eight PMOS transistors; internal storage nodes I2 and I3 are cross-coupled by P2 and P3, and external storage nodes I1 and I4 are cross-coupled by N1 and N2; P1 and P4 act as pull-up transistors, P1 and P4 reinforce I2 and I3, and I2 and I3 are completely surrounded by PMOS transistors, thus forming a polarity reinforcement structure; I2 is connected to the BLB through P7, I3 is connected to the BL through P8, I1 is connected to the BL through N3, I4 is connected to the BLB through N4, N3 and N4 are controlled by WL, and P7 and P8 are controlled by WWL. The present invention can improve the single-event upset resistance of the SRAM memory cell, and can significantly increase the write speed of the SRAM memory cell while sacrificing a smaller cell area, thereby reducing the power consumption of the SRAM memory cell.

Description

12T anti-radiation SRAM memory cell based on polarity reinforcing technology

Technical Field

The invention relates to the technical field of SRAM (Static Random Access Memory, chinese is static random access memory), in particular to a 12T (12T means 12 CMOS tubes) anti-irradiation SRAM memory cell based on a polarity reinforcing technology, which is a cell circuit structure capable of improving the writing speed of the memory cell and improving the single event upset (SINGLE EVENT Upset, SEU) resistance of the cell, and is hereinafter called RHMC-12T.

Background

With the rapid growth of the integrated circuit industry, static random access memory (sram) has become a key component of high performance Integrated Circuits (ICs). In aerospace electronics, which are almost indispensable components, high-energy particles from cosmic rays often are in a space radiation environment, occasionally causing temporary Single Event Upset (SEU) once they strike a sensitive node of a memory cell. At the same time, the storage node capacitance of SRAM cells decreases with decreasing total area, while the supply voltage decreases with technology development, which reduces the charge of the storage node, so the impact of high energy particles (e.g., neutrons) present in cosmic rays and ray particles) tends to lead to confusion of SEU. When energetic particles pass through the silicon substrate, minority carriers (electron and hole pairs) are generated, which are collected and accumulated at the source or drain diffusions, creating voltage transients at the sensitive nodes. If the accumulated power is greater than the power on the sensitive node, the data on the sensitive storage node is changed.

In order to solve the problem of the influence of the SEU of the SRAM unit and improve the SEU resistance of the memory unit, the prior art mainly comprises the following schemes:

(1) The circuit shown in fig. 1 is a Soft Error Tolerant 10. 10T SRAM BitCell (QUATRO T) circuit proposed by Shah m.jahinuzzamandeng and David j.rennie in 2009, and is composed of four PMOS transistors and six NMOS transistors, two of which are used as transfer transistors, and has poor writing capability, high writing delay, and high writing failure rate at high frequencies.

(2) The circuit shown in fig. 2 is a basic 6T SRAM memory cell, which is composed of two PMOS transistors and four NMOS transistors, and the memory cell uses the smallest number of transistors and therefore has the smallest area, but the circuit does not have any single-node flip-flop resistance.

(3) The circuit shown in FIG. 3 is a soft-error-aware-14T (SEA 14T) circuit proposed by Soumitra Pal in 2021, which consists of six PMOS transistors and eight NMOS transistors, wherein two NMOS transistors are used as transmission transistors, and the circuit has better SEU resistance, but the consumed area of the circuit is larger and the delay of writing data is higher.

(4) The circuit shown in fig. 4 is a Quadruple Cross-Coupled Memory (QCCM T) circuit proposed by Aibin Yan in 2019, which uses four access transistors, has a low read-write access time, can better tolerate single-node flip and few dual-node pair flip, but has a large static power consumption.

(5) The circuit shown in fig. 5 is a soft-error RESILIENT READ decoupled T (SRRD T) circuit proposed by Soumitra Pal in 2021, which is composed of eight PMOS transistors and four NMOS transistors, two NMOS transistors and two PMOS transistors as transfer transistors, which have a lower write delay but a higher read delay.

In view of this, the present invention has been made.

Disclosure of Invention

The invention aims to provide a 12T anti-radiation SRAM memory cell based on a polarity reinforcing technology, so as to solve the technical problems in the prior art. The invention not only can improve the single event upset resistance of the SRAM memory cell, but also can greatly improve the writing speed of the SRAM memory cell under the condition of sacrificing smaller cell area, and reduces the power consumption of the SRAM memory cell.

The invention aims at realizing the following technical scheme:

A12T anti-irradiation SRAM memory cell based on a polarity reinforcing technology comprises 4 NMOS transistors and 8 PMOS transistors, wherein the 4 NMOS transistors are respectively defined as N1, N2, N3 and N4, the 8 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6, P7 and P8, the internal storage node I2 and the internal storage node I3 are cross-coupled by the PMOS transistors P2 and P3, the external storage node I1 and the external storage node I4 are cross-coupled by the NMOS transistors N1 and N2, the NMOS transistors P1 and P4 serve as pull-up transistors, the NMOS transistors N1 and N2 serve as pull-down transistors, the PMOS transistors P1 and P4 reinforce the internal storage node I2 and the internal storage node I3, the internal storage node I2 and the internal storage node I3 are all surrounded by the PMOS transistors, a polarity reinforcing structure is formed, the internal storage node I2 is connected to a second bit line BLB through a PMOS transistor P7, the bit line I is connected to a second bit line BLL 3 through a PMOS transistor BLB 3, and a bit line BLL 4 is connected to an NMOS transistor 3 through a control bit line BLL 4, and a bit line BLL 4 is connected to an external storage node I3 through a control line BLL 4, and a bit line BLL 4 is connected to a bit line 3 through a control transistor BLL 4.

Preferably, the drain of the PMOS transistor P2 is electrically connected to the gate of the PMOS transistor P3 and the source of the PMOS transistor P5 at the internal storage node I2, the drain of the PMOS transistor P5 is grounded, the drain of the PMOS transistor P3 is electrically connected to the gate of the PMOS transistor P2 and the source of the PMOS transistor P6 at the internal storage node I3, the drain of the PMOS transistor P6 is grounded, the drain of the NMOS transistor N1 is electrically connected to the gate of the NMOS transistor N2 and the gate of the PMOS transistor P6 at the external storage node I1, the source of the NMOS transistor N1 is grounded, the drain of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N1 and the gate of the PMOS transistor P5 at the external storage node I4, the source of the PMOS transistor P1 is grounded, the gate of the PMOS transistor P1 is electrically connected to the internal storage node I2, the drain of the PMOS transistor P1 is electrically connected to the external storage node I1 and the source of the PMOS transistor P3, the drain of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P4 at the internal storage node I4;

The drain electrode of the PMOS transistor P7 is electrically connected with the internal storage node I2, the source electrode of the PMOS transistor P7 is electrically connected with the second bit line BLB, the grid electrode of the PMOS transistor P7 is electrically connected with the second word line WWL, the drain electrode of the PMOS transistor P8 is electrically connected with the internal storage node I3, the source electrode of the PMOS transistor P8 is electrically connected with the first bit line BL, and the grid electrode of the PMOS transistor P8 is electrically connected with the second word line WWL;

The drain of the NMOS transistor N3 is electrically connected with the external storage node I1, the source of the NMOS transistor N3 is electrically connected with the first bit line BL, the gate of the NMOS transistor N3 is electrically connected with the first word line WL, the drain of the NMOS transistor N4 is electrically connected with the external storage node I4, the source of the NMOS transistor N4 is electrically connected with the second bit line BLB, and the gate of the NMOS transistor N4 is electrically connected with the first word line WL.

Preferably, the gate lengths of all NMOS transistors and all PMOS transistors are 65nm, the gate widths of PMOS transistors P1 and P4 are 420nm, the gate widths of PMOS transistors P2 and P3 are 280nm, the gate widths of PMOS transistors P5 and P6 are 85nm, the gate widths of PMOS transistors P7 and P8 are 140nm, the gate widths of NMOS transistors N1 and N2 are 280nm, and the gate widths of NMOS transistors N3 and N4 are 140nm.

Compared with the prior art, the invention comprises 4 NMOS transistors and 8 PMOS transistors, wherein the internal storage node I2 and the internal storage node I3 are cross-coupled by the PMOS transistors P2 and P3, the external storage node I1 and the external storage node I4 are cross-coupled by the NMOS transistors N1 and N2, the PMOS transistors P1 and P4 are used as pull-up transistors, the NMOS transistors N1 and N2 are used as pull-down transistors, the PMOS transistors P1 and P4 reinforce the internal storage node I2 and the internal storage node I3, the internal storage node I2 and the internal storage node I3 are all surrounded by the PMOS transistors, a polarity reinforcing structure is formed, the NMOS transistors N3, the NMOS transistors N4, the PMOS transistors P7 and P8 are transmission transistors, the NMOS transistors N3 and N4 are controlled by first word lines, the PMOS transistors P7 and P8 are controlled by second word lines L, that is, namely, the invention adopts the principle that the flip-flop transistors of different types have different polarities and have the same design, and the internal storage node I can be turned over by the internal storage node I is reinforced by the invention, and the internal storage node I can be protected by the internal storage node I2 is stable by the aid of the principle of the flip-flop of the internal storage node I2. Meanwhile, the circuit uses four transmission transistors to read and write, when in the process of writing data, the bit line simultaneously writes the data into the internal nodes I1\I4 and I2\I3 through the transmission transistors N3, N4, P7 and P8, so that the storage node is easier to write the data, the data writing speed of the unit is greatly improved, and the circuit has lower power consumption due to the improvement of the writing speed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art Quattro 10T circuit;

FIG. 2 is a schematic diagram of a 6T circuit in the prior art;

FIG. 3 is a schematic diagram of a prior art SEA14T circuit;

FIG. 4 is a schematic diagram of a QCCM T circuit according to the prior art;

FIG. 5 is a schematic diagram of a SRRD T circuit according to the prior art;

FIG. 6 is a schematic diagram of a 12T anti-radiation SRAM memory cell (RHMC-12T for short) based on a polarity reinforcement technique according to an embodiment of the present invention;

FIG. 7 is a timing chart of a 12T anti-irradiation SRAM memory cell based on the polarity reinforcement technique provided in embodiment 1 of the present invention (simulation conditions: corner: TT; temperature:25 ℃ C.; VDD: 1.2V);

FIG. 8 is a schematic diagram of a transient waveform of a 12T anti-irradiation SRAM memory cell based on a polarity reinforcement technique according to embodiment 1 of the present invention (simulation conditions: VDD: 1.2V) in which different nodes are subjected to pulse injection of a dual-exponential current source at different times;

FIG. 9 is a graph showing EQM values of a prior art Quattro 10T circuit, 6T circuit, SEA14T circuit, QCCM T circuit, SRRD T circuit and a 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technique according to example 1 of the present invention (simulation conditions: VDD: 1.2V);

FIG. 10 is a graph of the prior art of Quattro 10T, 6T, SEA14T, QCCM T, SRRD T versus HSNM, RSNM, WSNM for a 12T irradiation-resistant SRAM cell based on the polarity reinforcing technique provided in example 1 of the present invention (simulation conditions: corner: TT; temperature:27 ℃ C.; VDD: 1.2V).

Detailed Description

The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention, and this is not limiting to the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

The terms that may be used herein will first be described as follows:

The terms "comprises," "comprising," "includes," "including," "has," "having" or other similar referents are to be construed to cover a non-exclusive inclusion. For example, inclusion of a feature (e.g., a starting material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, apparatus, step, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be construed as including not only the feature explicitly recited, but also other features known in the art that are not explicitly recited.

The 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technology provided by the present invention is described in detail below. What is not described in detail in the present invention belongs to the prior art known to those skilled in the art. The specific conditions are not noted in the examples of the present invention and are carried out according to the conditions conventional in the art or suggested by the manufacturer. The reagents or apparatus used in the examples of the present invention were conventional products commercially available without the manufacturer's knowledge.

Example 1

As shown in fig. 6, embodiment 1 of the present invention provides a 12T irradiation-resistant SRAM memory cell (RHMC-12T for short) based on a polarity reinforcement technology, whose structure mainly includes 4 NMOS transistors and 8 PMOS transistors, wherein the 4 NMOS transistors are respectively defined as N1, N2, N3, N4, and the 8 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6, P7, and P8. The internal storage node I2 and the internal storage node I3 are cross-coupled by a PMOS transistor P2 and a PMOS transistor P3, the external storage node I1 and the external storage node I4 are cross-coupled by an NMOS transistor N1 and an NMOS transistor N2, the PMOS transistor P1 and the PMOS transistor P4 are used as pull-up transistors, the NMOS transistor N1 and the NMOS transistor N2 are used as pull-down transistors, the PMOS transistor P1 and the PMOS transistor P4 strengthen the internal storage node I2 and the internal storage node I3, the internal storage node I2 and the internal storage node I3 are all surrounded by PMOS transistors, which form a polarity strengthening structure, the internal storage node I2 is connected to a second bit line BLB through a PMOS transistor P7, the internal storage node I3 is connected to a first bit line BL through a PMOS transistor P8, the external storage node I1 is connected to the first bit line BL through an NMOS transistor N3, the external storage node I4 is connected to a second bit line BLB through an NMOS transistor N4, and the NMOS transistors N3 and N4 are controlled by a first word line WL and the PMOS transistors P7 and WWL 8 are controlled by a second word line WWL 8.

Specifically, the 12T anti-irradiation SRAM memory cell based on the polarity reinforcing technology comprises a drain electrode of a PMOS transistor P2 and a grid electrode of a PMOS transistor P3, wherein a source electrode of the PMOS transistor P5 is electrically connected to an internal storage node I2, a drain electrode of the PMOS transistor P5 is grounded, a drain electrode of the PMOS transistor P3 and a grid electrode of the PMOS transistor P2, a source electrode of the PMOS transistor P6 is electrically connected to the internal storage node I3, and a drain electrode of the PMOS transistor P6 is grounded; the drain of the NMOS transistor N1 is electrically connected with the grid electrode of the NMOS transistor N2 and the grid electrode of the PMOS transistor P6 to the external storage node I1, the source electrode of the NMOS transistor N1 is grounded, the drain electrode of the NMOS transistor N2 is electrically connected with the grid electrode of the NMOS transistor N1 and the grid electrode of the PMOS transistor P5 to the external storage node I4, the source electrode of the NMOS transistor N2 is grounded, the source electrode of the PMOS transistor P1 is connected with the voltage VDD, the grid electrode of the PMOS transistor P1 is electrically connected with the internal storage node I2, the drain electrode of the PMOS transistor P1 is electrically connected with the external storage node I1 and the source electrode of the PMOS transistor P3, the source electrode of the PMOS transistor P4 is electrically connected with the internal storage node I4 and the source electrode of the PMOS transistor P2, and the internal storage node I2 are reinforced by the PMOS transistor P1 and the PMOS transistor P4, and the internal storage node I2 and the internal storage node I3 are all surrounded by the PMOS transistors with the polarity. The drain of the PMOS transistor P7 is electrically connected to the internal storage node I2, the source of the PMOS transistor P7 is electrically connected to the second bit line BLB, the gate of the PMOS transistor P7 is electrically connected to the second word line WWL, the drain of the PMOS transistor P8 is electrically connected to the internal storage node I3, the source of the PMOS transistor P8 is electrically connected to the first bit line BL, and the gate of the PMOS transistor P8 is electrically connected to the second word line WWL. The drain of the NMOS transistor N3 is electrically connected to the external storage node I1, the source of the NMOS transistor N3 is electrically connected to the first bit line BL, the gate of the NMOS transistor N3 is electrically connected to the first word line WL, the drain of the NMOS transistor N4 is electrically connected to the external storage node I4, the source of the NMOS transistor N4 is electrically connected to the second bit line BLB, and the gate of the NMOS transistor N4 is electrically connected to the first word line WL, that is, the NMOS transistor N3, the NMOS transistor N4, the PMOS transistor P7, and the PMOS transistor P8 are transfer transistors.

Further, in the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technique provided in embodiment 1 of the present invention, the gate lengths of all NMOS transistors and all PMOS transistors are 65nm, the gate widths of PMOS transistors P1 and P4 are 420nm, the gate widths of PMOS transistors P2 and P3 are 280nm, the gate widths of PMOS transistors P5 and P6 are 85nm, the gate widths of PMOS transistors P7 and P8 are 140nm, the gate widths of NMOS transistors N1 and N2 are 280nm, and the gate widths of NMOS transistors N3 and N4 are 140nm, so that the 12T irradiation-resistant memory cell based on the polarity reinforcing technique in embodiment 1 of the present invention can be increased in anti-interference performance by using these NMOS transistors and PMOS transistors, and if the dimensions of these transistors are changed, the functions of the designed circuits may be changed, and the capability of single event upset resistance may not be achieved.

Furthermore, the principle of the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technology provided in embodiment 1 of the present invention is as follows:

(1) In the hold phase, the first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is low, the second word line WWL is high, and the circuit is kept in an initial state and does not operate.

(2) In the read data phase, the first bit line BL and the second bit line BLB are precharged to a high level, the first word line WL is high level, the second word line WWL is high level, the NMOS transistor N3 and the NMOS transistor N4 are turned on, the PMOS transistor P7 and the PMOS transistor P8 are turned off, if the data stored in the cell circuit is '0', i.e. "i1=i3=0, i2=i4=1", the first bit line BL is discharged to the ground through the NMOS transistor N3 and the NMOS transistor N1 so that the bit line generates a voltage difference, and then the data is read out through the sense amplifier, and if the data stored in the cell circuit is '1', i.e. "i1=i3=1, i2=i4=0", the second bit line BLB is discharged to the ground through the NMOS transistor N4 and the NMOS transistor N2 so that the bit line generates a voltage difference, and then the data is read out through the sense amplifier.

(3) In the data writing phase, the first word line WL is at high level, and the second word line WWL is at low level. If the first bit line BL is high and the second bit line BLB is low, a '1' is written to the external storage node I1 and the internal storage node I3 through the NMOS transistor N3 and the PMOS transistor P8, respectively, and if the first bit line BL is low and the second bit line BLB is high, a '0' is written to the external storage node I1 and the internal storage node I3 through the NMOS transistor N3 and the PMOS transistor P8, respectively. In the writing process, since data is written into the storage nodes I1\i4 and I3\i2 through the NMOS transistor N3, the NMOS transistor N4, the PMOS transistor P7 and the PMOS transistor P8 at the same time, the storage nodes are easier to be written with data, the writing speed is greatly increased, and meanwhile, the power consumption of the circuit is reduced due to the great increase of the writing speed.

Compared with the prior art, in the 12T anti-irradiation SRAM memory unit based on the polarity reinforcement technology, when the improvement of irradiation resistance of a circuit structure is considered, if the memory node of the circuit is bombarded by particles, the internal memory node I2 and the internal memory node I3 of the circuit are surrounded by PMOS transistors, according to the polarity reinforcement principle, space particles bombard the sensitive node PMOS tube, voltage pulses of 0-1' are only generated at the nodes, the states of other transistors cannot be influenced by the pulses due to the existence of gate capacitance, the internal node I2 and the internal memory node I3 are effectively prevented from overturning, meanwhile, the stability of node data of the internal memory node I2 and the internal memory node I3 ensures that the external memory node I1 and the external memory node I4 can be restored to an initial state after the overturning, so that the SEU resistance of the circuit is greatly improved, and if other non-critical nodes are bombarded by particles, the memory unit is not easily influenced, therefore, the anti-single particle overturning capability of the memory unit can be improved, the SRAM memory unit can be greatly increased, and the power consumption of the memory unit can be greatly reduced under the condition that the SRAM memory unit is greatly sacrificed.

The following performance comparison analysis was performed on the prior art Quatro 10T circuit shown in fig. 1, the prior art 6T circuit shown in fig. 2, the prior art SEA14T circuit shown in fig. 3, the prior art QCCM T circuit shown in fig. 4, the prior art SRRD T circuit shown in fig. 5, and the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcement technique provided in embodiment 1 of the present invention shown in fig. 6:

(1) The 12T anti-irradiation SRAM memory cell based on the polar reinforcement technology provided in the embodiment 1 of the present invention was simulated (the simulation conditions are Corner: TT; temperature:25 ℃ C.; VDD: 1.2V), so that a timing waveform diagram as shown in FIG. 7 could be obtained. As can be seen from fig. 7, the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcement technology provided in embodiment 1 of the present invention can implement operations of writing '1', reading '1', writing '0' and reading '0' by the normal memory node.

(2) The 12T irradiation-resistant SRAM memory cell based on the polarity reinforcement technology provided in embodiment 1 of the present invention is simulated (the simulation condition is VDD: 1.2V), so that a transient waveform simulation diagram of the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcement technology provided in embodiment 1 of the present invention, as shown in fig. 8, in which different nodes are subjected to pulse injection of a double-exponential current source at different times, can be obtained. As can be seen from FIG. 8, the 12T anti-irradiation SRAM memory cell based on the polarity reinforcement technology provided by the embodiment 1 of the invention can realize all single-node flip recovery, and has better single-node and multi-node flip immunity characteristics.

(3) The simulation comparison (simulation condition: VDD: 1.2V) is performed on the prior art quad 10T circuit shown in fig. 1, the prior art 6T circuit shown in fig. 2, the prior art SEA14T circuit shown in fig. 3, the prior art QCCM T circuit shown in fig. 4, the prior art SRRD T circuit shown in fig. 5, and the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technology provided in embodiment 1 of the present invention shown in fig. 6, so that the following EQM (circuit performance metrics) value comparison chart shown in fig. 9 can be obtained. As can be seen from fig. 9, the circuit performance of embodiment 1 of the present invention is good.

(4) The prior art quad 10T circuit shown in fig. 1, the prior art 6T circuit shown in fig. 2, the prior art SEA14T circuit shown in fig. 3, the prior art QCCM T circuit shown in fig. 4, the prior art SRRD T circuit shown in fig. 5, and the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technique provided in embodiment 1 of the present invention shown in fig. 6 were subjected to simulation comparison (simulation conditions: corner: TT; temperature:27 ℃ and VDD: 1.2V), whereby HSNM (holding noise margin), RSNM (read noise margin) and WSNM (write noise margin) comparison charts shown in fig. 10 can be obtained as follows. As can be seen from fig. 10, the anti-interference capability of holding data, reading data, and writing data of embodiment 1 of the present invention is relatively good.

(5) The prior art quad 10T circuit shown in fig. 1, the prior art 6T circuit shown in fig. 2, the prior art SEA14T circuit shown in fig. 3, the prior art QCCM T circuit shown in fig. 4, the prior art SRRD T circuit shown in fig. 5, and the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technology provided in embodiment 1 of the present invention shown in fig. 6 were subjected to circuit area comparison, read/write time, and power consumption simulation comparison (simulation conditions: corner: TT; temperature:25 ℃, VDD: 1.2V), so that the circuit area, read/write time, and power consumption simulation comparison table shown in table 1 below could be obtained:

TABLE 1

SRAM memory cell circuit	Area of circuit (mum)	Read operation time (ps)	Write operation time (ps)	Power consumption (mu W)
					SRRD12T	8.82	90.00	38.80	57.59
6T	4.56	41.19	103.08	59.90
					Quatro 10T	7.09	60.73	389.40	62.75
QCCM12T	8.36	21.27	57.60	97.20
					SEA14T	9.05	48.00	100.42	58.44
Inventive example 1	8.76	46.20	39.22	57.35

As can be seen from Table 1, compared with five SRAM memory cell circuits in the prior art, the 12T anti-irradiation SRAM memory cell based on the polarity reinforcement technology provided by the embodiment 1 of the present invention has the lowest power consumption, and the write operation speed of the embodiment 1 of the present invention is equivalent to SRRD T circuits in the prior art, which is far better than other conventional SRAM memory cell circuits, and the read operation speed of the embodiment 1 of the present invention is far better than SRRD T circuits in the prior art, so that the embodiment of the present invention can greatly improve the read and write speeds of the SRAM memory cell at the expense of a smaller cell area, and can reduce the power consumption of the SRAM memory cell.

(6) Critical charge comparison simulations (simulation conditions: corner: TT; temperature:27 ℃ and VDD: 1.2V) were performed on the prior art quad 10T circuit shown in fig. 1, the prior art 6T circuit shown in fig. 2, the prior art SEA14T circuit shown in fig. 3, the prior art QCCM T circuit shown in fig. 4, the prior art SRRD T circuit shown in fig. 5, and the 12T irradiation-resistant SRAM memory cell based on the polarity reinforcing technique provided in embodiment 1 of the present invention shown in fig. 6, so that the critical charge comparison table shown in table 2 below could be obtained:

TABLE 2

As can be seen from Table 2, compared with the SRAM memory cell circuit in the prior art, the critical charge of embodiment 1 of the present invention is relatively high, which shows that the single event upset resistance of embodiment 1 of the present invention is relatively high.

In summary, the embodiment of the invention not only can improve the single event upset resistance of the SRAM memory cell, but also can greatly improve the writing speed of the SRAM memory cell under the condition of sacrificing smaller cell area, thereby reducing the power consumption of the SRAM memory cell.

The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.

Claims

1. The 12T anti-radiation SRAM memory cell based on the polarity reinforcing technology is characterized by comprising 4 NMOS transistors and 8 PMOS transistors, wherein the 4 NMOS transistors are respectively defined as N1, N2, N3 and N4, and the 8 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6, P7 and P8;

The internal storage node I2 and the internal storage node I3 are cross-coupled by a PMOS transistor P2 and a PMOS transistor P3, the external storage node I1 and the external storage node I4 are cross-coupled by an NMOS transistor N1 and an NMOS transistor N2, the PMOS transistor P1 and the PMOS transistor P4 are used as pull-up transistors, the NMOS transistor N1 and the NMOS transistor N2 are used as pull-down transistors, the PMOS transistor P1 and the PMOS transistor P4 strengthen the internal storage node I2 and the internal storage node I3, the internal storage node I2 and the internal storage node I3 are surrounded by PMOS transistors P1-P8, which form a polarity reinforcing structure, the internal storage node I2 is connected to a second bit line BLB through a PMOS transistor P7, the internal storage node I3 is connected to a first bit line BL through a PMOS transistor P8, the external storage node I1 is connected to the first bit line BL through an NMOS transistor N3, the external storage node I4 is connected to a second bit line BLB through an NMOS transistor N4, the NMOS transistor N3 and the PMOS transistors WL are surrounded by a first word line control P7 and a second word line WWL 8;

The drain of the PMOS transistor P2 is electrically connected to the gate of the PMOS transistor P3 and the source of the PMOS transistor P5 at the internal storage node I2, the drain of the PMOS transistor P5 is grounded, the drain of the PMOS transistor P3 is electrically connected to the gate of the PMOS transistor P2 and the source of the PMOS transistor P6 at the internal storage node I3, and the drain of the PMOS transistor P6 is grounded; the drain electrode of the NMOS transistor N1 is electrically connected with the grid electrode of the NMOS transistor N2 and the grid electrode of the PMOS transistor P6 to the external storage node I1, the source electrode of the NMOS transistor N1 is grounded, the drain electrode of the NMOS transistor N2 is electrically connected with the grid electrode of the NMOS transistor N1 and the grid electrode of the PMOS transistor P5 to the external storage node I4, and the source electrode of the NMOS transistor N2 is grounded;

2. The 12T irradiation-resistant SRAM memory cell of claim 1 wherein the gate lengths of all NMOS transistors and all PMOS transistors are 65nm, the gate widths of PMOS transistors P1 and P4 are 420nm, the gate widths of PMOS transistors P2 and P3 are 280nm, the gate widths of PMOS transistors P5 and P6 are 85nm, the gate widths of PMOS transistors P7 and P8 are 140nm, the gate widths of NMOS transistors N1 and N2 are 280nm, and the gate widths of NMOS transistors N3 and N4 are 140nm.