CN114497001B - Common-mode noise suppression filter based on three-dimensional integration technology - Google Patents
Common-mode noise suppression filter based on three-dimensional integration technology Download PDFInfo
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- CN114497001B CN114497001B CN202111604861.7A CN202111604861A CN114497001B CN 114497001 B CN114497001 B CN 114497001B CN 202111604861 A CN202111604861 A CN 202111604861A CN 114497001 B CN114497001 B CN 114497001B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/20—Inductors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
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Abstract
本发明公开了一种基于三维集成技术的共模噪声抑制滤波器，包括七个顶部RDL螺旋电感，七个顶部RDL螺旋电感的下方连接四个TSV电容。本发明能在实现共模噪声基本性能的同时，整体结构紧凑，集成度高。
The present invention discloses a common mode noise suppression filter based on three-dimensional integration technology, including seven top RDL spiral inductors, and four TSV capacitors are connected below the seven top RDL spiral inductors. The present invention can achieve the basic performance of common mode noise while having a compact overall structure and high integration.
Description
Technical Field
The invention belongs to the technical field of three-dimensional integrated circuits, and relates to a common mode noise suppression filter based on a three-dimensional integrated technology.
Background
Differential or balanced signals have become a popular technique in high-speed systems due to the good immunity of ground to external noise, small crosstalk between adjacent pairs, and signal integrity. However, in a true differential signal structure, there is unavoidable Common Mode (CM) noise, which has a great influence on the transmission signal. Such noise is caused by unbalanced output of the signal transmitting device, asymmetry of the two signal paths, or crosstalk from adjacent signal pairs.
Over the past few years, techniques for suppressing CM noise have been widely discussed, including the use of ferrite materials, ground fault structures, and the use of mushroom-shaped structural bisectors. These methods are all developed based on Printed Circuit Boards (PCBs), low temperature co-fired ceramics (LTCCs) or ferrite substrates, but they are not easily implemented on chip scale or three-dimensional chip structures due to the large horizontal chip area required.
Based on a non-reflection symmetrical circuit network, the passive device is integrated by a TSV three-dimensional integration technology through a complex circuit topological structure, so that a compact structure and higher integration level can be realized. The horizontal area of the chip is reduced while basic performance is realized.
Disclosure of Invention
The invention aims to provide a common mode noise suppression filter based on a three-dimensional integration technology, which can realize the basic performance of common mode noise and has compact overall structure and high integration level.
The technical scheme adopted by the invention is that the common mode noise suppression filter based on the three-dimensional integration technology comprises seven top RDL spiral inductors, and four TSV capacitors are connected below the seven top RDL spiral inductors.
The invention is also characterized in that:
the seven top RDL spiral inductors include RDL spiral inductor L1, RDL spiral inductor L2, RDL spiral inductor L3, RDL spiral inductor L4, RDL spiral inductor L5, RDL spiral inductor L6, RDL spiral inductor L7;
The RDL spiral inductor L1, the RDL spiral inductor L2, the RDL spiral inductor L3, the RDL spiral inductor L4, the RDL spiral inductor L5, the RDL spiral inductor L6 and the RDL spiral inductor L7 have the same structure and are formed by rotating RDLs with equal thickness and equal width.
The spiral inductor includes a rotation start port1 and a rotation end port2.
The four TSV capacitors comprise a TSV capacitor C1, a TSV capacitor C2, a TSV capacitor C3 and a TSV capacitor C4;
the TSV capacitor C1, the TSV capacitor C2, the TSV capacitor C3 and the TSV capacitor C4 have the same structure, and the TSV capacitor comprises a capacitor plate1, a capacitor plate2, a capacitor plate3 and a capacitor plate4, wherein an MIM capacitor is formed between the capacitor plate1 and the capacitor plate2, and an MIM capacitor is formed between the capacitor plate3 and the capacitor plate4;
The capacitor plate1 is connected with the capacitor plate3 through the TSV, and the capacitor plate2 is connected with the capacitor plate4 through the TSV.
The plate1 of the TSV capacitor C1 is respectively connected with the starting end port1 of the RDL spiral inductor L1 and the starting end port1 of the RDL spiral inductor L2;
the plate1 of the TSV capacitor C2 is respectively connected with the tail port2 of the RDL spiral inductor L2 and the starting port1 of the RDL spiral inductor L3;
The plate2 of the TSV capacitor C3 is respectively connected with the starting end port1 of the RDL spiral inductor L4 and the starting end port1 of the RDL spiral inductor L5;
the plate2 of the TSV capacitor C4 is respectively connected with the tail port2 of the RDL spiral inductor L5 and the starting port1 of the RDL spiral inductor L6;
Plate2 of the TSV capacitor C1, plate2 of the TSV capacitor C2, plate1 of the TSV capacitor C3 and plate1 of the TSV capacitor C4 are connected with the initial port1 of the spiral inductor L7, and the tail port2 of the spiral inductor L7 is grounded.
The beneficial effects of the invention are as follows:
1. The silicon-based substrate is adopted, and is compatible with the existing common silicon process products;
2. The RDL spiral inductor is adopted, so that the inductor can be realized while interconnection is realized without increasing the area;
3. The inductance device is realized by adopting the TSV technology, the integration level is high, and the horizontal area of the chip is reduced.
Drawings
FIG. 1 is a schematic three-dimensional structure of a common mode noise rejection filter based on three-dimensional integration techniques of the present invention;
FIG. 2 is a schematic diagram of spiral inductance in a common mode noise rejection filter based on three-dimensional integration techniques in accordance with the present invention;
FIG. 3 is a schematic diagram of TSV capacitance in a common mode noise rejection filter based on three-dimensional integration techniques in accordance with the present invention;
FIG. 4 is a schematic circuit diagram of a common mode noise rejection filter based on three-dimensional integration techniques of the present invention;
fig. 5 is a schematic structural diagram of a single TSV in the common mode noise suppression filter based on the three-dimensional integration technique of the present invention.
In the figure, a copper column, a silicon dioxide layer, a silicon substrate layer, an upper RDL, a lower RDL, an interconnection bond and an interconnection layer.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
The circuit diagram of the common mode noise suppression filter based on the three-dimensional integration technology is shown in fig. 4, the three-dimensional structure diagram is shown in fig. 1, and the common mode noise suppression filter comprises seven top RDL spiral inductors, seven top RDL spiral inductors and four TSV capacitors connected below.
The seven top RDL inductors comprise a spiral inductor L1, a spiral inductor L2, a spiral inductor L3, a spiral inductor L4, a spiral inductor L5, a spiral inductor L6 and a spiral inductor L7;
Spiral inductor L1, spiral inductor L2, spiral inductor L3, spiral inductor L4, spiral inductor L5, spiral inductor L6 and spiral inductor L7 have the same structure and are formed by rotating RDLs with equal thickness and equal width.
Fig. 2 is a schematic structural diagram of a spiral inductor. The spiral inductor includes a start port1 and a tail port2.
The four TSV capacitors comprise a TSV capacitor C1, a TSV capacitor C2, a TSV capacitor C3 and a TSV capacitor C4;
the TSV capacitor C1, the TSV capacitor C2, the TSV capacitor C3 and the TSV capacitor C4 have the same structure and are formed by connecting a plurality of TSVs with a capacitor electrode plate.
As shown in fig. 3, the TSV capacitor includes a capacitor plate1, a capacitor plate2, a capacitor plate3, and a capacitor plate4; MIM (metal-oxide-metal) capacitance is formed between the capacitance plate1 and the capacitance plate2, and MIM (metal-oxide-metal) capacitance is formed between the capacitance plate3 and the capacitance plate 4.
The capacitor plate1 and the capacitor plate2 are both an upper RDL4, and the capacitor plate3 and the capacitor plate4 are both a lower RDL5.
The upper RDL4 is connected to the interconnect layer 7 through the interconnect key 6, the interconnect key 6 is connected to the lower side of the interconnect layer 7, and the spiral inductors are connected to the upper side of the interconnect layer 7.
The capacitor plate1 is connected with the capacitor plate3 through 3 TSVs, and the capacitor plate2 is connected with the capacitor plate4 through 3 TSVs. Coupling capacitance is formed between the TSVs.
The plate1 of the TSV capacitor C1 is respectively connected with the starting end port1 of the spiral inductor L1 and the starting end port1 of the spiral inductor L2;
the plate1 of the TSV capacitor C2 is respectively connected with the tail port2 of the spiral inductor L2 and the starting port1 of the spiral inductor L3;
the plate2 of the TSV capacitor C3 is respectively connected with the starting end port1 of the spiral inductor L4 and the starting end port1 of the spiral inductor L5;
plate2 of the TSV capacitor C4 is connected with the tail port2 of the spiral inductor L5 and the starting port1 of the spiral inductor L6 respectively;
Plate2 of the TSV capacitor C1, plate2 of the TSV capacitor C2, plate1 of the TSV capacitor C3 and plate1 of the TSV capacitor C4 are connected with the starting end port1 of the spiral inductor L7. The end port2 of the spiral inductor L7 is grounded.
As shown in fig. 5, each TSV (through silicon via) includes a copper pillar 1, and a silicon dioxide layer 2 and a silicon substrate layer 3 are coaxially wrapped outside the copper pillar 1 in order.
Table 1 below shows the values of the devices of the common mode noise suppression filter based on the three-dimensional integration technique according to the present invention:
TABLE 1
| Inductance value (nH) | Capacitance value (PF) | ||
| L1、L3、L4、L6 | 0.25 | C1 | 0.1 |
| L2、L5 | 0.325 |
Claims (1)
1. The common mode noise suppression filter based on the three-dimensional integration technology is characterized by comprising seven top RDL spiral inductors, wherein four TSV capacitors are connected below the seven top RDL spiral inductors;
The seven top RDL spiral inductors include RDL spiral inductor L1, RDL spiral inductor L2, RDL spiral inductor L3, RDL spiral inductor L4, RDL spiral inductor L5, RDL spiral inductor L6, and RDL spiral inductor L7;
The RDL spiral inductor L1, the RDL spiral inductor L2, the RDL spiral inductor L3, the RDL spiral inductor L4, the RDL spiral inductor L5, the RDL spiral inductor L6 and the RDL spiral inductor L7 have the same structure and are formed by rotating RDLs with equal thickness and equal width;
the spiral inductor comprises a rotation start port1 and a rotation end port2;
the four TSV capacitors comprise a TSV capacitor C1, a TSV capacitor C2, a TSV capacitor C3 and a TSV capacitor C4;
the TSV capacitor C1, the TSV capacitor C2, the TSV capacitor C3 and the TSV capacitor C4 have the same structure, and the TSV capacitor comprises a capacitor plate1, a capacitor plate2, a capacitor plate3 and a capacitor plate4, wherein an MIM capacitor is formed between the capacitor plate1 and the capacitor plate2, and an MIM capacitor is formed between the capacitor plate3 and the capacitor plate4;
The capacitor plate1 is connected with the capacitor plate3 through the TSV, and the capacitor plate2 is connected with the capacitor plate4 through the TSV;
the plate1 of the TSV capacitor C1 is respectively connected with the starting end port1 of the RDL spiral inductor L1 and the starting end port1 of the RDL spiral inductor L2;
the plate1 of the TSV capacitor C2 is respectively connected with the tail port2 of the RDL spiral inductor L2 and the starting port1 of the RDL spiral inductor L3;
The plate2 of the TSV capacitor C3 is respectively connected with the starting end port1 of the RDL spiral inductor L4 and the starting end port1 of the RDL spiral inductor L5;
the plate2 of the TSV capacitor C4 is respectively connected with the tail port2 of the RDL spiral inductor L5 and the starting port1 of the RDL spiral inductor L6;
Plate2 of the TSV capacitor C1, plate2 of the TSV capacitor C2, plate1 of the TSV capacitor C3 and plate1 of the TSV capacitor C4 are connected with the initial port1 of the spiral inductor L7, and the tail port2 of the spiral inductor L7 is grounded.
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| CN115395914A (en) * | 2022-08-31 | 2022-11-25 | 西安理工大学 | Common mode rejection filter based on three-dimensional through silicon via passive device |
Citations (2)
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| CN109981071A (en) * | 2019-02-18 | 2019-07-05 | 西安电子科技大学 | A kind of three-dimensional low-pass filter based on coaxial through-silicon via and spiral inductance |
| CN110492861A (en) * | 2019-08-15 | 2019-11-22 | 中国电子科技集团公司第五十五研究所 | Novel GHz ultra wide band common mode noise rejection circuit topological structure |
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| JPH07122955A (en) * | 1993-10-26 | 1995-05-12 | Takeshi Ikeda | Noise filter |
| US20070057359A1 (en) * | 1997-04-08 | 2007-03-15 | Anthony Anthony A | Energy conditioning circuit assembly and component carrier |
| US8120445B2 (en) * | 2007-06-15 | 2012-02-21 | City University Of Hong Kong | Planar EMI filter comprising coreless spiral planar windings |
| JP6471995B2 (en) * | 2014-12-03 | 2019-02-20 | 国立大学法人信州大学 | Common mode filter |
| CN108987374B (en) * | 2018-06-22 | 2020-06-26 | 西安理工大学 | A three-dimensional capacitor based on TSV and RDL |
| US10433425B1 (en) * | 2018-08-01 | 2019-10-01 | Qualcomm Incorporated | Three-dimensional high quality passive structure with conductive pillar technology |
| US10637405B2 (en) * | 2018-08-14 | 2020-04-28 | Nxp Usa, Inc. | Wideband biasing of high power amplifiers |
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| CN214672913U (en) * | 2020-11-12 | 2021-11-09 | 南京国博电子股份有限公司 | IPD technology-based ultra-wideband and wide-stop-band-pass filter |
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| CN109981071A (en) * | 2019-02-18 | 2019-07-05 | 西安电子科技大学 | A kind of three-dimensional low-pass filter based on coaxial through-silicon via and spiral inductance |
| CN110492861A (en) * | 2019-08-15 | 2019-11-22 | 中国电子科技集团公司第五十五研究所 | Novel GHz ultra wide band common mode noise rejection circuit topological structure |
Non-Patent Citations (1)
| Title |
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| 《三位集成共模噪声抑制滤波器研究》;侯仓仓;《中国优秀硕士学位论文全文数据库 (信息科技辑)》;20240216;I135-410 * |
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