CN114497227A - A kind of multi-independent gate field effect transistor, preparation method and integrated circuit - Google Patents

Abstract

The invention discloses a multi-independent grid field effect transistor and a preparation method thereof, wherein the multi-independent grid field effect transistor comprises: a source, a drain, a channel region and a gate structure disposed on the insulating substrate; the channel region is connected with the source electrode and the drain electrode; the gate structure comprises a gate dielectric layer and a gate electrode layer which are arranged in a stacked mode; the gate electrode layer comprises more than two carbon nanotube gate electrodes which do not intersect with each other. The field effect transistor with multiple independent grids provided by the application obviously improves the micro-scale capability or the integration level capability, and provides a flexible and efficient novel field effect transistor device design for the integration of high-density devices in a super-large scale integrated circuit.

Description

A kind of multi-independent gate field effect transistor, preparation method and integrated circuit

technical field

The present application relates to the field of semiconductor technology, and in particular, to a multi-independent gate field effect transistor, a manufacturing method and an integrated circuit.

Background technique

Moore's Law requires the integration of integrated circuits to continuously improve. Device scaling is the main means to improve the integration level of traditional silicon-based complementary field effect transistor (CMOS) integrated circuits. The short-channel effect is a key factor limiting the scaling limit of traditional silicon-based planar devices. In order to overcome the short channel effect, gate-all-around field effect transistors are often used, including stacked nanosheet field effect transistors and nanowire field effect transistors, which is one of the technical paths for large-scale integrated circuits at the 5nm process node. Compared with commercial silicon-based planar FETs, silicon-on-insulator FETs, and fin FETs, gate-all-around FETs have stronger gate control capabilities, thereby improving the device's ability to suppress short-channel effects. For realizing devices and logic circuits in 5nm and below process nodes.

However, the gate patterning of the gate-all-around silicon-based field effect transistor requires a photolithography process, and its physical gate length is limited by the photolithography process, and it is difficult to achieve a physical gate length of less than 10 nanometers. In addition, in the traditional CMOS integrated circuit architecture, the combinational logic unit of X input is composed of 2X field effect transistors. The gate-all-around field effect transistor follows the CMOS architecture. The number of FETs in its logic circuit is limited by the CMOS architecture and cannot be reduced by reducing The number of field effect transistors required by the circuit increases the integration level.

SUMMARY OF THE INVENTION

The present invention provides a multi-independent gate field effect transistor, a preparation method and an integrated circuit, so as to solve or partially solve the problem that due to the limitation of the photolithography process, the physical gate length of the field effect transistor cannot be further reduced, resulting in its ability to improve the integration degree. limited technical issues.

In order to solve the above technical problems, according to an optional embodiment of the present invention, a multi-independent gate field effect transistor is provided, including:

A source electrode, a drain electrode, a channel region and a gate electrode structure arranged on an insulating substrate; the channel region connects the source electrode and the drain electrode; the gate electrode structure includes a gate dielectric layer arranged in layers and A gate electrode layer; the gate electrode layer includes two or more non-intersecting carbon nanotube gate electrodes.

Optionally, the channel region is disposed on the insulating substrate, and the gate dielectric layer is located between the channel region and the gate electrode layer.

Further, the FET also includes:

a first mask layer disposed on the gate structure;

a first passivation layer provided to cover the first mask layer and the source electrode and the drain electrode;

Wherein, the first mask layer is provided with a first gate metal connection that conducts the carbon nanotube gate electrode; the first passivation layer is provided with a first source lead-out electrode connected to the source , a first drain lead-out electrode connected to the drain and a first gate lead-out electrode connected to the first gate metal connection.

Optionally, the gate dielectric layer is located between the insulating substrate and the channel region; the gate electrode layer is located between the insulating substrate and the gate dielectric layer.

Further, the FET also includes:

a second mask layer disposed on the channel region;

a second passivation layer provided to cover the second mask layer and the source electrode and the drain electrode;

Wherein, the second mask layer and the gate dielectric layer are provided with a second gate metal connection that conducts the carbon nanotube gate electrode; the second passivation layer is provided with a connection to the source electrode A second source lead-out electrode, a second drain lead-out electrode connected to the drain, and a second gate lead-out electrode connected to the second gate metal connection.

Optionally, the channel region is a semiconductor-type carbon nanotube channel region.

Based on the same inventive concept, according to another optional embodiment of the present invention, a method for manufacturing a multi-independent gate field effect transistor is provided, the method comprising:

forming a stacked source, drain, channel region and gate structure on an insulating substrate;

Wherein, the gate structure includes a stacked gate dielectric layer and a gate electrode layer; the gate electrode layer includes two or more non-intersecting carbon nanotube gate electrodes.

Optionally, forming the stacked source electrode, drain electrode, channel region and gate structure on the insulating substrate includes:

forming the channel region on the insulating substrate;

forming the gate dielectric layer on the channel region;

Using a carbon nanotube film forming method, the gate electrode layer is formed on the gate dielectric layer;

forming a first mask layer on the gate electrode layer;

forming a first source region and a first drain region exposing the channel region on the first mask layer by an etching method;

The source is formed in the first source region, and the drain is formed in the first drain region.

Further, after the source electrode is formed in the first source region, and after the drain electrode is formed in the first drain region, the preparation method further includes:

A first passivation layer is formed on the first mask layer, the source electrode and the drain electrode;

A first source lead-out electrode connected to the source and a first drain lead-out electrode connected to the drain are formed on the first passivation layer.

Optionally, forming the stacked source electrode, drain electrode, channel region and gate structure on the insulating substrate includes:

Using a carbon nanotube film-forming method, the gate electrode layer is formed on the insulating substrate;

forming the gate dielectric layer on the gate electrode layer;

forming the channel region on the gate dielectric layer;

forming a second mask layer on the channel region;

forming a second source region and a second drain region exposing the channel region on the second mask layer by an etching method;

The source is formed in the second source region, and the drain is formed in the second drain region.

Based on the same inventive concept, according to another optional embodiment of the present invention, an integrated circuit is provided, including a mainboard and any of the field effect transistors in the foregoing technical solutions provided on the mainboard.

Through one or more technical solutions of the present invention, the present invention has the following beneficial effects or advantages:

The invention provides a multi-independent gate field effect tube. In terms of devices, the carbon nanotube array with a quasi-one-dimensional structure is formed by taking advantage of the controllable orientation of carbon nanotubes as a gate electrode layer. The carbon nanotube is a gate electrode, which breaks through the gate length limitation of the traditional photolithography process for field effect transistors, and reduces the physical gate length to the diameter dimension of a single carbon nanotube, that is, less than 2 nanometers; at the same time, the multi-independent gate field effect The tube takes advantage of the mutual isolation of non-intersecting carbon nanotube gate electrodes to form a natural multi-input AND gate and NOR gate unit, reducing the number of gates required by traditional X-input CMOS combinational logic circuits from 2X to X+ 1, breaking through the integration bottleneck in terms of circuit architecture; through the joint action of the above-mentioned devices and circuit architecture, the scaling capability or integration capability of the multi-independent gate field effect transistor is significantly improved, which is a high-end VLSI integrated circuit. Density device integration provides a flexible and efficient new FET device design.

The above description is only an overview of the technical solutions of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand , the following specific embodiments of the present invention are given.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be considered limiting of the invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

Fig. 1 shows the structural schematic diagram of the existing carbon nanotube field effect device;

FIG. 2 shows a multi-independent gate field effect transistor according to an embodiment of the present invention, and a circuit structure based on its circuit device structure combinational logic unit circuit architecture;

FIG. 3 shows a top view of a multi-independent gate field effect transistor with a top-gate structure design according to an embodiment of the present invention;

4 shows a cross-sectional view of a multi-independent gate field effect transistor designed with a top gate structure according to an embodiment of the present invention;

5A shows a top view of forming a semiconductor-type CNT channel according to an embodiment of the present invention;

5B shows a cross-sectional view of forming a semiconductor-type CNT channel according to an embodiment of the present invention;

Figure 5C shows a top view of active region patterning according to one embodiment of the present invention;

5D shows a cross-sectional view of active region patterning according to one embodiment of the present invention;

5E shows a top view of the deposition of a gate dielectric layer according to an embodiment of the present invention;

5F shows a cross-sectional view of gate dielectric layer deposition according to one embodiment of the present invention;

5G shows a top view of forming a metal-type CNT gate electrode layer according to an embodiment of the present invention;

5H shows a cross-sectional view of forming a metal-type CNT gate electrode layer according to an embodiment of the present invention;

5I shows a top view of forming a first mask layer according to an embodiment of the present invention;

5J shows a cross-sectional view of forming a first mask layer according to an embodiment of the present invention;

5K shows a top view of source-drain metal patterning according to one embodiment of the present invention;

5L shows a cross-sectional view of source-drain metal patterning according to one embodiment of the present invention;

5M shows a top view of the patterning of the first gate metal connection according to one embodiment of the present invention;

5N shows a cross-sectional view of the patterning of the first gate metal connection according to one embodiment of the present invention;

50 illustrates a top view of forming a first passivation layer according to an embodiment of the present invention;

5P shows a cross-sectional view of forming a first passivation layer according to an embodiment of the present invention;

6 shows a top view of a multi-independent gate field effect transistor with a back gate structure design according to an embodiment of the present invention;

7 shows a cross-sectional view of a multi-independent gate field effect transistor designed with a back gate structure according to an embodiment of the present invention;

8A shows a top view of forming a metal-type CNT gate electrode array according to an embodiment of the present invention;

8B shows a cross-sectional view of forming a metal-type CNT gate electrode array according to an embodiment of the present invention;

8C shows a top view of forming a gate dielectric layer according to an embodiment of the present invention;

8D shows a cross-sectional view of forming a gate dielectric layer according to an embodiment of the present invention;

8E shows a top view of forming a semiconductor-type channel region according to an embodiment of the present invention;

8F shows a cross-sectional view of forming a semiconductor-type channel region according to an embodiment of the present invention;

8G shows a top view of active region patterning according to one embodiment of the present invention;

8H shows a cross-sectional view of active region patterning according to one embodiment of the present invention;

8I shows a top view of forming a second mask layer according to one embodiment of the present invention;

8J shows a cross-sectional view of forming a second mask layer according to an embodiment of the present invention;

8K shows a top view of source-drain metal patterning according to one embodiment of the present invention;

8L shows a cross-sectional view of source-drain metal patterning according to one embodiment of the present invention;

8M shows a top view of a second gate metal connection patterning according to an embodiment of the present invention;

8N shows a cross-sectional view of the patterning of the second gate metal connection according to one embodiment of the present invention;

80 illustrates a top view of forming a second passivation layer according to an embodiment of the present invention;

8P shows a cross-sectional view of forming a second passivation layer according to an embodiment of the present invention;

Description of reference numbers:

1, insulating substrate; 2, channel region; 3, gate dielectric layer; 4, gate electrode layer; 51, first mask layer; 52, second mask layer; 61, source electrode; 62, drain electrode; 71, the first gate metal connection; 72, the second gate metal connection; 81, the first passivation layer; 82, the second passivation layer; 91, the first source extraction electrode; 92, the first drain extraction electrode; 93, the first gate lead-out electrode; 94, the second source lead-out electrode; 95, the second drain lead-out electrode; 96, the second gate lead-out electrode.

Detailed ways

In order to make the application more clearly understood by those skilled in the technical field to which the application belongs, the technical solutions of the application are described in detail below with reference to the accompanying drawings and through specific embodiments. Throughout the specification, unless specifically stated otherwise, terms used herein are to be understood as commonly used in the art. Therefore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict, the present specification takes precedence. Unless otherwise specified, various equipments and the like used in the present invention can be purchased from the market or can be prepared by existing methods.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

Further research shows that, on the one hand, the gate patterning of gate-all-around silicon-based FETs requires photolithography, and its physical gate length is limited by the photolithography process, and it is difficult to achieve a physical gate length of less than 10 nanometers; on the other hand, The gate-all-around FET adopts the method of reducing the channel size, especially the channel thickness, to enhance the gate control ability to suppress the short channel effect. The channel thickness control is achieved by a silicon/germanium silicon selective etching process. When the channel thickness is reduced to less than 5 nanometers, the problem of uniformity in etching and the rough surface formed by etching will seriously affect the performance of the device and circuit, so the effect of improving the short channel suppression capability of this type of device is limited. Therefore, the above two factors both limit the performance of the silicon-based gate-all-around device to improve the integration.

At present, a field effect transistor scheme based on carbon nanotubes (Carbon Nanotubes, CNT for short) to form a channel has also appeared, as shown in FIG. 1 . Due to the quasi-one-dimensional structure of carbon nanotubes, compared with silicon-based devices, carbon nanotube devices have a smaller channel size and stronger coupling between the gate and the channel, so their ability to suppress short-channel effects is stronger. Therefore, the physical channel length scaling limit of carbon nanotube field effect transistors is smaller than that of silicon-based devices, and it is one of the technical means for ultra-large-scale integration in the post-Moore era. However, the current carbon nanotube device structures all follow the gate structure in silicon-based CMOS devices, which are composed of a high dielectric constant (κ) metal gate dielectric and metal gate electrodes, and a photolithography process is required in the manufacturing process. Therefore, the physical gate length scaling of the existing carbon nanotube devices is also limited by the photolithography process, and its integration capability is limited.

In terms of improving the integration level by reducing the number of field effect transistors required by the circuit, the current multiple independent gate field effect transistor (Multiple Field Effect Transistor, MuFET for short) is a new device structure, which can be used to realize a new type of combinational logic circuit. , as shown in Figure 2; the number of field effect transistor gates required by the combinational logic circuit of X input is reduced from 2X to X+1, which improves the circuit integration level from the circuit architecture level. However, existing MIGFETs use silicon nanotube channels and metal gate electrodes. On the one hand, the diameter of silicon nanotubes is limited by the aforementioned etching process and cannot be reduced to less than 5 nanometers, which limits the improvement of the device's ability to suppress short-channel effects. On the other hand, the metal gate electrode process needs to use a photolithography process, and its scaling capability is limited. The above two factors together lead to the fact that the existing MIGFETs cannot be used to fabricate VLSIs in the post-Moore era.

Based on the above research basis, in an optional embodiment, the present invention provides a new multi-independent gate field effect transistor, including:

A source electrode, a drain electrode, a channel region and a gate electrode structure arranged on an insulating substrate; the channel region connects the source electrode and the drain electrode; the gate electrode structure includes a gate dielectric layer arranged in layers and A gate electrode layer; the gate electrode layer includes two or more non-intersecting carbon nanotube gate electrodes.

The above-mentioned multiple independent gate field effect transistors can improve the ability to shrink, and the principle of increasing the integration degree is: the multiple independent gate field effect transistors jointly improve the circuit integration degree from the two dimensions of the device and the circuit structure, breaking through the photolithography and combinational logic circuits in the traditional CMOS process. The limit of the number of gates on the circuit integration; in terms of devices, the multi-independent gate FET takes advantage of the controllable orientation of carbon nanotubes to form a carbon nanotube array with a quasi-one-dimensional structure as the gate electrode layer; in the gate electrode layer, A carbon nanotube is a gate electrode, which breaks through the gate length limitation of field effect transistors by the traditional lithography process, and can reduce the physical gate length to the diameter dimension of a single carbon nanotube, that is, less than 2 nanometers; at the same time, multiple independent The gate FET takes advantage of the mutual isolation of the non-intersecting carbon nanotube gate electrodes to form a natural multi-input AND gate and NOR gate unit, reducing the number of gates required by traditional X-input CMOS combinational logic circuits from 2X. To X+1, the integration bottleneck is broken from the aspect of the circuit structure; through the joint action of the above two aspects, the scaling capability or integration capability of the multiple independent gate field effect transistors provided by the present invention can be significantly improved, which is a very large-scale integrated circuit. The high-density device integration in the present invention provides a flexible and efficient new FET device design.

It should be noted that the carbon nanotube gate electrode uses metal-type carbon nanotubes, one carbon nanotube forms a gate electrode, and the diameter of the carbon nanotube is equal to the gate length. The gate electrode layer includes a plurality of carbon nanotubes arranged in parallel to form a CNT array, and the arrangement direction of the CNTs can be perpendicular to the channel length direction, or nearly perpendicular, thereby forming a plurality of independent CNT gate electrodes.

The carbon nanotube deposition method for forming the above-mentioned CNT gate electrode layer includes, but is not limited to, a wet film forming process and a pulling process. Among them, the wet film forming process utilizes the controllable orientation of carbon nanotubes by dispersing metal-type single-walled carbon nanotubes, diluting them in a suitable solvent, and then filtering, dipping, spraying, spin coating and other methods. Deposited on a corresponding substrate and dried to obtain sequentially arranged CNT arrays to form a gate electrode layer; the CNT density in the CNT arrays is controlled by the dilution process of the single-walled carbon nanotube dispersion.

For the pulling process, the metal-type carbon nanotube material is dispersed in a solvent to form a uniform carbon nanotube dispersion, and then the substrate is immersed in the dispersion (vertical immersion or flat immersion), and then the substrate is pulled upward; The interaction of the solution forms a thin solution film on the surface of the substrate where the liquid level is raised. After the solution film evaporates quickly, a uniform carbon nanotube film, that is, the CNT gate electrode layer, can be obtained on the substrate; The speed and pulling times can effectively control the density of carbon nanotube films.

Optionally, the insulating substrate may be a silicon dioxide/silicon substrate, or a sapphire substrate or the like;

Optionally, the channel region is a semiconductor-type carbon nanotube channel region, and the carbon nanotube channel region can be a carbon nanotube film formed according to a carbon nanotube film-forming process, and the carbon nanotube film is composed of a carbon nanotube array. or carbon nanotube network formation, which is not specifically limited here.

Optionally, the material of the gate dielectric layer may be hafnium dioxide (H _f O ₂ ), yttrium oxide (Y ₂ O ₃ ) and other high-κ metal gate dielectrics, and silicon dioxide and high-κ metal gate dielectric stacks any of the .

Optionally, for N-type MuFET, scandium (Sc) can be used to form the source-drain metal; for P-type MuFET, palladium (Pd), platinum (Pt), gold (Au) or high work function metal stack structure can be used Form the source and drain metal.

The multiple independent gate field effect transistor (MuFET) provided in this application can be designed in two structures, top gate and back gate, and the working mechanisms of the two structures are the same: in the top gate and back gate devices, the gate electrode layer: each in the CNT array. The CNTs are isolated from each other, thereby forming an independent gate structure. Each independent gate can modulate the potential barrier height in the channel through the field effect, thereby modulating the conductivity of the channel region. When all the CNT gate electrodes are turned on, the channel is turned on; when any one or more CNT gate electrodes are turned off, the channel is turned off, so that a single device realizes "NOR" logic.

The difference in the design of top gate and back gate structures mainly lies in the deposition sequence of the gate electrode CNT and the channel CNT in the process. Next, they will be described separately.

In an optional embodiment, as shown in FIG. 3 to FIG. 4 , a structural design of a top-gate MuFET is provided, as follows:

insulating substrate 1;

The source electrode 61, the drain electrode 62, the channel region 2 and the gate structure arranged on the insulating substrate 1;

The channel region 2 is connected to the source electrode 61 and the drain electrode 62; the gate structure includes a gate dielectric layer 3 and a gate electrode layer 4 that are stacked and arranged; the gate electrode layer 4 includes two or more, each other. Disjoint carbon nanotube gate electrodes; wherein the channel region 2 is provided on the insulating substrate 1 , and the gate dielectric layer 3 is located between the channel region 2 and the gate electrode layer 4 .

Specifically, in the MuFET designed with the top gate structure, the channel region 2 is formed on the insulating substrate 1 , the gate dielectric layer 3 is formed on the channel region 2 , and the gate electrode layer 4 is formed on the gate dielectric layer 3 in the order Laminate.

Optionally, as shown in FIG. 5A to FIG. 5P , the field effect transistor further includes:

a first mask layer 51 disposed on the gate structure;

A first passivation layer 81 covering the first mask layer 51 and the source electrode 61 and the drain electrode 62 is provided; wherein, the carbon nanotubes are provided in the first mask layer 51 to conduct the carbon nanotubes. The first gate metal connection 71 of the gate electrode; the first passivation layer 81 is provided with a first source lead-out electrode 91 connected to the source electrode 61 and a first drain lead-out electrode 92 connected to the drain electrode 62 and a first gate lead-out electrode 93 connected to the first gate metal connection 71 .

The first mask layer 51 may be a hard mask, and the material of the hard mask may be any one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride, or other insulator materials different from gate dielectrics.

The material of the first passivation layer 81 may be any one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride or other insulators different from the gate dielectric.

Optionally, the first gate metal connection 71 may use copper (Cu), chromium/copper (Cr/Cu) metal stack, tungsten/copper (W/Cu) metal stack, or other metal stacks compatible with silicon-based semiconductor back-end processes material formed. The gate metal connection is used to conduct the gate electrode and the gate extraction electrode.

Optionally, the material of the first source lead-out electrode 91 and the first drain lead-out electrode 92 may be copper (Cu) or other materials compatible with the silicon-based semiconductor back-end process to form the lead-out structure.

In another optional embodiment of the MuFET designed based on the aforementioned top-gate structure, the corresponding preparation method includes:

forming the channel region 2 on the insulating substrate 1;

forming the gate dielectric layer 3 on the channel region 2;

Using a carbon nanotube film forming method, the gate electrode layer 4 is formed on the gate dielectric layer 3;

forming a first mask layer 51 on the gate electrode layer 4;

By an etching method, a first source region and a first drain region exposing the channel region 2 and a first gate metal region exposing the gate electrode layer 4 are formed on the first mask layer 51;

The source electrode 61 is formed in the first source region, the drain electrode 62 is formed in the first drain region, and the first gate metal connection 71 is formed in the first gate metal region;

A first passivation layer 81 is formed on the first mask layer 51 and the source electrode 61 and the drain electrode 62;

A first source lead-out electrode 91 connected to the source electrode 61 , a first drain lead-out electrode 92 connected to the drain electrode 62 , and a first gate metal connection 71 are formed on the first passivation layer 81 of the first gate lead-out electrode 93 .

Next, in conjunction with the specific implementation process, the above preparation scheme is further described:

Step S100: providing a silicon dioxide insulating substrate;

Step S101 : diluting the semiconductor-type single-walled CNT dispersion to modulate the CNT density in the channel region;

Step S102: using the diluent to deposit a CNT film to form a CNT channel;

Referring to FIG. 5A and FIG. 5B , in this embodiment, a pull-up film-forming process is used to deposit semiconductor-type CNTs to form a channel region 2 of the MuFET, and the structure of the channel region 2 may be a CNT array or a CNT network. It should be noted that, in the CNT pulling film forming process, the density of the CNT film is controlled by controlling the pulling speed and the pulling times, so as to realize the control of parameters such as the equivalent channel width and on-state current in the CNT MuFET. Purpose. Unless otherwise specified, this embodiment is described by taking a CNT array as an example.

Step S103: active region photolithography, etching, and patterning;

Referring to FIG. 5C and FIG. 5D , an electron beam lithography process can be used to pattern the active region of the device.

Step S104: atomic layer deposition of high-κ metal gate dielectric;

Referring to FIG. 5E and FIG. 5F , an atomic layer deposition (Atomic Layer Deposition, ALD) process is used for gate oxide deposition to form a gate dielectric layer 3 . Any material can be used to form the gate dielectric layer 3 : high-κ metal gate dielectric such as hafnium dioxide (H _f O ₂ ), yttrium oxide (Y ₂ O ₃ ), and a silicon dioxide/high-κ metal gate dielectric stack.

Step S105 : using the diluent CNT to pull and form a film to form a CNT gate electrode array;

Referring to FIGS. 5G and 5H , a metal-type CNT array is deposited by a CNT array film forming process to form the gate electrode layer 4 . In the pull-up film formation process, the CNT density in the array is controlled by controlling the pull-up speed and the pull-up times, so as to control the spacing of the CNT gate electrodes.

Step S106: chemical vapor deposition of the first mask layer;

Referring to FIG. 5I and FIG. 5J , a chemical vapor deposition (Chemical Vapor Deposition, CVD) process is used for hard mask deposition. The hard mask can be made of any of the following materials, including: silicon dioxide, silicon nitride, silicon oxynitride, or other insulator materials different from the gate dielectric.

Step S107: photolithography of source and drain regions;

Referring to FIG. 5K and FIG. 5L, a photolithography process is used to complete the patterning of the source and drain regions.

Step S108: etching the first mask layer and etching the gate dielectric layer;

The etching of the first mask layer 51 and the etching of the high-κ metal gate dielectric layer 3 are sequentially performed to expose the semiconductor-type CNTs in the source and drain regions, that is, the channel region 2 . The etching process of the first mask layer 51 and the gate dielectric layer 3 includes but is not limited to chemical etching or reactive ion etching.

Step S109 : metal evaporation and metal patterning in the source and drain regions

The metal deposition of the source and drain regions is completed by a metal evaporation process, and the metal patterning of the source and drain regions is completed by means of metal stripping or etching. Scandium (Sc) can be used to form the source-drain metal in N-type MuFET, and palladium (Pd), platinum (Pt), gold (Au) or high work function metal stack structure can be used to form source-drain metal in P-type MuFET.

Step S110: the first gate metal connection photolithography;

Referring to FIG. 5M and FIG. 5N, a photolithography process is used to complete the patterning of the gate metal connection.

Step S111 : etching the first mask layer to expose the CNT electrodes in the metal through hole region;

The metal-type CNTs in the metal via region are exposed by hard mask etching. Hardmask etching processes include, but are not limited to, chemical etching and reactive ion etching.

Step S112: metal through hole evaporation and metal patterning;

The metal deposition of the source and drain regions is completed by a metal evaporation process, and the patterning of the gate metal connection is completed by means of metal stripping or etching. The gate metal connections are formed using copper (Cu), chromium/copper (Cr/Cu) metal stacks, tungsten/copper (W/Cu) metal stacks, or other materials compatible with silicon-based semiconductor back-end processing.

Step S113: depositing a first passivation layer;

Referring to FIG. 5O and FIG. 5P, the passivation layer is deposited by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process. The first passivation layer 81 can be made of any of the following materials, including silicon dioxide, silicon nitride, silicon oxynitride, or other insulators different from gate dielectrics.

Step S114: photolithography of source, drain, and gate lead-out electrodes, and etching of passivation layer

The photolithography process is used to complete the patterning of source, drain and gate metal extraction.

A first passivation layer 81 etch is performed, exposing the metal contacts. The passivation layer etching process includes, but is not limited to, chemical etching and reactive ion etching.

Step S115 : metal evaporation and metal patterning of the lead electrode;

The deposition of metal extraction is completed by a metal evaporation process, and the patterning of the metal extraction is completed by means of metal stripping or etching. Copper (Cu) or other materials compatible with silicon-based semiconductor back-end processes are used to form metal leads to complete the preparation of CNT-based MuFET devices as shown in FIGS. 3 and 4 .

This embodiment provides a method for fabricating a multi-independent gate field effect transistor with a top gate structure. Sc/Pd metal is used to form the source and drain electrodes of the N-type and P-type devices, respectively, and H _f O ₂ and Y ₂ O are used. ₃ , etc. high κ metal gate dielectric, the gate dielectric layer is formed by atomic layer deposition method; and through the CNT array deposition process, semiconductor-type carbon nanotubes are used to form a channel region on the insulating substrate, and the gate dielectric layer is formed by pulling. The film method forms metal-type carbon nanotubes arranged side by side and perpendicular to the channel direction, thereby forming a plurality of independent CNT gate electrodes. This process takes advantage of the controllable orientation of CNTs to form a quasi-one-dimensional CNT gate electrode on the gate dielectric layer, breaking through the limitation of the gate length of the device by photolithography in the traditional process and reducing the physical gate length to less than 2 nanometers. At the same time, the advantage of mutual isolation between gate electrodes CNT is used to form a natural multi-input AND gate and NOR gate unit, which reduces the number of gates required by traditional X-input CMOS combinational logic circuits from 2X to X+1, from The circuit architecture breaks through the integration bottleneck; the combination of the above two aspects fully exploits the potential of CNTs in improving circuit integration, and provides a flexible and efficient preparation of new FETs for high-density device integration in VLSI Program.

In another optional embodiment, as shown in FIG. 6 to FIG. 7 , a structural design of a back-gate MuFET is provided, as follows:

insulating substrate 1;

The source electrode 61, the drain electrode 62, the channel region 2 and the gate structure arranged on the insulating substrate 1;

The channel region 2 is connected to the source electrode 61 and the drain electrode 62; the gate structure includes a gate dielectric layer 3 and a gate electrode layer 4 that are stacked and arranged; the gate electrode layer 4 includes two or more, each other. Disjoint carbon nanotube gate electrodes; wherein, the gate dielectric layer 3 is located between the insulating substrate 1 and the channel region 2 ; the gate electrode layer 4 is located between the insulating substrate 1 and the between the gate dielectric layers 3 .

Specifically, in the MuFET with a back-gate design, the gate electrode layer 4 is formed on the insulating substrate 1 , the gate dielectric layer 3 is formed on the gate electrode layer 4 , and the channel region 2 is formed on the gate dielectric layer 3 in the sequence. cascading.

Optionally, as shown in FIG. 8A to FIG. 8P , the field effect transistor further includes:

a second mask layer 52 disposed on the channel region 2;

A second passivation layer 82 is provided to cover the second mask layer 52 and the source electrode 61 and the drain electrode 62 ; wherein, the second mask layer 52 and the gate dielectric layer 3 are provided with The second gate metal connection 72 of the carbon nanotube gate electrode is turned on; the second passivation layer 82 is provided with a second source lead-out electrode 94 connected to the source electrode 61 and connected to the drain electrode 62 A second drain extraction electrode 95 and a second gate extraction electrode 96 connected to the second gate metal connection 72 .

The second mask layer 52 may be a hard mask, and the material of the hard mask may be any one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride, or other insulator materials different from gate dielectrics.

The material of the second passivation layer 82 can be any one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride or other insulators different from the gate dielectric.

Optionally, the second gate metal connection 72 may use copper (Cu), chromium/copper (Cr/Cu) metal stack, tungsten/copper (W/Cu) metal stack, or other metal stacks compatible with silicon-based semiconductor back-end processes material formed.

Optionally, the material of the second source lead-out electrode 94 and the second drain lead-out electrode 95 may be copper (Cu) or other materials compatible with the silicon-based semiconductor back-end process to form the lead-out structure.

In another optional embodiment of the MuFET designed based on the above-mentioned back gate structure, the corresponding preparation method includes:

Using a carbon nanotube film forming method, the gate electrode layer 4 is formed on the insulating substrate 1;

forming the gate dielectric layer 3 on the gate electrode layer 4;

forming the channel region 2 on the gate dielectric layer 3;

forming a second mask layer 52 on the channel region 2;

By an etching method, a second source region and a second drain region exposing the channel region 2 and a second gate metal region exposing the gate electrode layer 4 are formed on the second mask layer 52;

The source electrode 61 is formed in the second source region, the drain 62 is formed in the second drain region, and a second gate metal connection 72 is formed in the second gate metal region;

A second passivation layer 82 is formed on the second mask layer 52 and the source electrode 61 and the drain electrode 62;

A second source lead-out electrode 94 connected to the source electrode 61 , a second drain lead-out electrode 95 connected to the drain electrode 62 , and the second gate metal connection 72 are formed on the second passivation layer 82 The second gate lead-out electrode 96 .

Next, in conjunction with the specific implementation process, the above preparation scheme is further described:

Step S200: providing a silicon dioxide insulating substrate;

Step S201 : using a metal type single-walled CNT dispersion to form a CNT wet film to form a CNT gate electrode array;

Referring to FIG. 8A and FIG. 8B , a metallic CNT array is deposited by a CNT wet array film forming process to form a gate electrode. The wet film forming process adopts the diluted one-armed carbon nanotube dispersion of the previous steps, thereby controlling the CNT density in the array to achieve the purpose of gate electrode spacing in the CNT MuFET.

Step S202: gate dielectric layer deposition;

Referring to FIG. 8C and FIG. 8D , an atomic layer deposition (ALD) process is used for gate oxide deposition. The gate oxide may use any of the following materials, including: hafnium dioxide (H _f O ₂ ), yttrium oxide (Y ₂ O ₃ ) and other high-κ metal gate dielectrics, and silicon dioxide/high-κ metal gate dielectric stacks.

Step S203 : using a semiconductor type single-walled CNT dispersion to form a CNT wet film to form a CNT channel region;

Referring to FIG. 8E and FIG. 8F, semiconductor-type CNTs are deposited on the gate dielectric layer 3 by a wet film formation process to form the channel region 2 of the MuFET, and the structure can be a CNT array or a CNT network. Taking the CNT array as an example, in the wet film formation process, the CNT density in the array or network is controlled by controlling the dilution of the one-armed carbon nanotube dispersion, so as to realize the regulation of the equivalent width and opening of the channel in the CNT MuFET. The purpose of parameters such as state current. Unless otherwise specified, a CNT array is used as an example for description in this embodiment.

Step S204: active area photolithography and etching, patterning;

Referring to FIG. 8G and FIG. 8H, the patterning of the active region of the device is performed using an electron beam lithography process.

Step S205: chemical vapor deposition of a hard mask to form a second mask layer;

Referring to FIG. 8I and FIG. 8J, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process is used for hard mask deposition. The hard mask can be made of any of the following materials, including: silicon dioxide, silicon nitride, silicon oxynitride, or other insulator materials different from the gate dielectric.

Step S206: source and drain region photolithography, patterning;

Referring to FIG. 8K and FIG. 8L, the patterning of the source and drain regions is completed by using a photolithography process.

Step S207: etching the second mask to expose the CNT channel region;

The hard mask etching and gate oxide etching are sequentially performed to expose the semiconductor-type CNTs in the source and drain regions. Hardmask and gate oxide etching processes include, but are not limited to, chemical etching and reactive ion etching.

Step S208: metal evaporation and patterning in the source and drain regions

The metal deposition of the source and drain regions is completed by a metal evaporation process, and the metal patterning of the source and drain regions is completed by means of metal stripping or etching. Scandium (Sc) is used to form source-drain metal in N-type MuFET, and source-drain metal is formed by palladium (Pd), platinum (Pt), gold (Au) or high work function metal stack structure in P-type MuFET.

Step S209: second gate metal connection photolithography, patterning;

Referring to FIG. 8M and FIG. 8N, the patterning of the second gate metal connection 72 is completed using a photolithography process.

Step S210 : etching the hard mask, etching the gate dielectric layer, and exposing the CNT gate electrode in the metal through hole region;

By performing a hard mask etch on the second mask layer 52, the metal-type CNTs in the metal via region are exposed. Hardmask etching processes include, but are not limited to, chemical etching and reactive ion etching.

Step S211: evaporation and patterning of the second gate metal connection;

The metal deposition of the source and drain regions is completed by a metal evaporation process, and the patterning of the gate metal connection is completed by means of metal stripping or etching. The second gate metal connection 72 is formed using copper (Cu), chromium/copper (Cr/Cu) metal stack, tungsten/copper (W/Cu) metal stack, or other materials compatible with silicon-based semiconductor back-end processing.

Step S212: deposition of a second passivation layer;

Referring to FIGS. 8O and 8P, the deposition of the second passivation layer 82 is performed using a chemical vapor deposition process. The passivation layer can be made of any of the following materials, including: silicon dioxide, silicon nitride, silicon oxynitride or other insulator materials different from the gate dielectric. The second passivation layer 82 is used to isolate each contact electrode to prevent contamination and device aging.

Step S213: photolithography and patterning of source, drain, and gate lead-out electrodes;

The photolithography process is used to complete the patterning of source, drain and gate metal extraction.

Etching of the second passivation layer 82 is performed, exposing the metal contacts. The passivation layer etching process includes, but is not limited to, chemical etching and reactive ion etching.

Step S214: lead electrode metal evaporation and metal stripping;

The deposition of metal extraction is completed by a metal evaporation process, and the patterning of the metal extraction is completed by means of metal stripping or etching. Copper (Cu) or other materials compatible with the back-end process of silicon-based semiconductors are used to form metal leads to complete the preparation of CNT MuFETs as shown in FIG. 6 and FIG. 7 .

This embodiment provides a method for preparing a multi-independent gate field effect transistor with a back-gate structure. A gate electrode having a plurality of independent CNT gate electrodes is formed on an insulating substrate by using a metal-type carbon nanotube through a CNT array deposition process. Then use high κ metal gate dielectrics such as H _f O ₂ and Y ₂ O ₃ to form a gate dielectric layer on the gate electrode layer by atomic layer deposition; A CNT channel region is formed on the dielectric layer. The preparation method takes advantage of the controllable orientation of CNTs, forms a quasi-one-dimensional CNT gate electrode on an insulating substrate, breaks through the limitation of the gate length of the device by photolithography in the traditional process, and reduces the physical gate length to less than 2 nanometers; at the same time; , taking advantage of the mutual isolation between gate electrodes CNTs to form natural multi-input AND gates and NOR gate units, reducing the number of gates required by traditional X-input CMOS combinational logic circuits from 2X to X+1, from the circuit The architecture breaks through the integration bottleneck; the combination of the above two aspects fully explores the potential of CNTs in improving circuit integration, and provides a flexible and efficient preparation scheme for new FETs for high-density device integration in VLSI .

According to the same inventive concept of the previous embodiment, in yet another optional embodiment, an integrated circuit is also provided, and the integrated circuit may be an AC-DC conversion circuit, a high-voltage conversion circuit or a half-bridge rectifier circuit. integrated circuit. The integrated circuit includes a mainboard and any of the field effect transistors provided in the foregoing embodiments, and the field effect transistors are arranged on the mainboard. Since the principle of solving the problem of the integrated circuit is similar to that of the aforementioned field effect transistor, the implementation of the integrated circuit can refer to the implementation of the aforementioned field effect transistor, and the repetition will not be repeated.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Through one or more embodiments of the present invention, the present invention has the following beneficial effects or advantages:

The invention provides a multi-independent grid field effect transistor and a preparation method; wherein, in terms of devices, the multi-independent grid field effect transistor takes advantage of the controllable orientation of carbon nanotubes to form a carbon nanotube array with a quasi-one-dimensional structure as a grid The electrode layer, in the gate electrode layer, a carbon nanotube is a gate electrode, which breaks through the gate length limitation of the traditional photolithography process on the field effect transistor, and reduces the physical gate length to the diameter dimension of a single carbon nanotube, that is Below 2 nanometers; at the same time, the multi-independent gate FET takes advantage of the mutual isolation of the non-intersecting carbon nanotube gate electrodes to form a natural multi-input AND gate and NOR gate unit, and the traditional X input CMOS combinational logic circuit. The number of required gates has been reduced from 2X to X+1, breaking through the integration bottleneck in terms of circuit architecture; through the combined effects of the above-mentioned devices and circuit architecture, the scaling capability or integration of multi-independent gate FETs is significantly improved It provides a flexible and efficient new FET device design for high-density device integration in VLSI.

While the preferred embodiments of the present application have been described, additional changes and modifications to these embodiments may occur to those of ordinary skill in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiment and all changes and modifications that fall within the scope of this application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (11)

1. A multi-independent gate field effect transistor, wherein the field effect transistor comprises: A source electrode, a drain electrode, a channel region and a gate electrode structure arranged on an insulating substrate; the channel region connects the source electrode and the drain electrode; the gate electrode structure includes a gate dielectric layer arranged in layers and A gate electrode layer; the gate electrode layer includes two or more non-intersecting carbon nanotube gate electrodes. 2 . The field effect transistor of claim 1 , wherein the channel region is disposed on the insulating substrate, and the gate dielectric layer is located between the channel region and the gate electrode layer. 3 . . 3. The field effect transistor of claim 2, further comprising: a first mask layer disposed on the gate structure; a first passivation layer provided to cover the first mask layer and the source electrode and the drain electrode; Wherein, the first mask layer is provided with a first gate metal connection that conducts the carbon nanotube gate electrode; the first passivation layer is provided with a first source lead-out electrode connected to the source , a first drain lead-out electrode connected to the drain and a first gate lead-out electrode connected to the first gate metal connection. 4 . The field effect transistor of claim 1 , wherein the gate dielectric layer is located between the insulating substrate and the channel region; the gate electrode layer is located between the insulating substrate and the channel region. 5 . between the gate dielectric layers. 5. The field effect transistor of claim 4, further comprising: a second mask layer disposed on the channel region; a second passivation layer provided to cover the second mask layer and the source electrode and the drain electrode; Wherein, the second mask layer and the gate dielectric layer are provided with a second gate metal connection that conducts the carbon nanotube gate electrode; the second passivation layer is provided with a connection to the source electrode A second source lead-out electrode, a second drain lead-out electrode connected to the drain, and a second gate lead-out electrode connected to the second gate metal connection. 6 . The field effect transistor of claim 1 , wherein the channel region is a semiconductor-type carbon nanotube channel region. 7 . 7. A preparation method of a multi-independent gate field effect transistor, wherein the preparation method comprises: forming a stacked source, drain, channel region and gate structure on an insulating substrate; Wherein, the gate structure includes a stacked gate dielectric layer and a gate electrode layer; the gate electrode layer includes two or more non-intersecting carbon nanotube gate electrodes. 8 . The preparation method according to claim 7 , wherein the forming a layered source electrode, a drain electrode, a channel region and a gate electrode structure on the insulating substrate comprises: 8 . forming the channel region on the insulating substrate; forming the gate dielectric layer on the channel region; Using a carbon nanotube film forming method, the gate electrode layer is formed on the gate dielectric layer; forming a first mask layer on the gate electrode layer; forming a first source region and a first drain region exposing the channel region on the first mask layer by an etching method; The source is formed in the first source region, and the drain is formed in the first drain region. 9 . The preparation method of claim 8 , wherein the source electrode is formed in the first source region, and the preparation method is performed after the drain electrode is formed in the first drain region. 10 . Also includes: A first passivation layer is formed on the first mask layer, the source electrode and the drain electrode; A first source lead-out electrode connected to the source and a first drain lead-out electrode connected to the drain are formed on the first passivation layer. 10. The preparation method according to claim 7, wherein the forming the stacked source electrode, drain electrode, channel region and gate electrode structure on the insulating substrate comprises: Using a carbon nanotube film-forming method, the gate electrode layer is formed on the insulating substrate; forming the gate dielectric layer on the gate electrode layer; forming the channel region on the gate dielectric layer; forming a second mask layer on the channel region; forming a second source region and a second drain region exposing the channel region on the second mask layer by an etching method; The source is formed in the second source region, and the drain is formed in the second drain region. 11 . An integrated circuit, characterized in that it comprises a main board and the field effect transistor according to any one of claims 1 to 6 arranged on the main board. 12 .

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