CN114491395A - Current domain system design applied to analog front-end signal processing based on FFT algorithm - Google Patents

Abstract

Due to the orthogonal frequency division characteristic of the FFT algorithm, the algorithm has natural advantages in the analog processing of the radio frequency front-end receiver. Especially, a perfect FFT operation system is needed in the ofdm demodulation process used in the current 4G and 5G communications. The invention provides a system design applied to analog front end signal processing based on an FFT algorithm, which is used for analog front end processing when a radio frequency front end receiver receives an extremely high frequency modulation multi-frequency signal. It is characterized by comprising: and inputting the ultrahigh frequency sampling holding circuit at the front end for realizing subsequent discrete Fourier transform calculation. And the input transconductance amplifier is used for converting the input discrete voltage signal into a current signal. And the FFT calculation core module is used for converting the time domain current signal into a current value representing frequency domain information by performing multiply-add operation. And the output trans-impedance amplifier is used for converting the current signal after the FFT operation into a voltage signal.

Description

Design of a current-domain system for analog front-end signal processing based on FFT algorithm

technical field

The invention proposes a system design based on FFT algorithm applied to analog front-end signal processing, specifically relates to the technical field of analog integrated circuit design, in particular to a discrete multiply-add operation circuit system with a high-speed sampling switch. The system can handle the demodulation process of high-speed multi-frequency signals. The modulated multi-frequency signal is divided into a low-frequency single-frequency signal.

Background technique

With the rapid development of Internet of Things (IoT) technology, the physical layer requires high-speed wireless solutions. Therefore, according to Shannon's theorem, the development of wireless communication technology must be accompanied by wider bandwidth. In traditional software radio systems, radio frequency (RF) signals are usually processed in the digital domain through analog-to-digital conversion. This places higher speed and dynamic range requirements on the front-end analog-to-digital converter (ADC). Time-domain ADCs can address speed limitations, but each sub-ADC requires the same dynamic range (DR) requirements to meet the overall signal to noise and distortion ratio (SNDR) requirements. On the other hand, higher bandwidth means higher sampling frequency, which means more power consumption.

In a digital signal processor (DSP), FFT is the core component of Orthogonal Frequency Division Multiplexing (OFDM) demodulation processing, and is the core component of 4G Long Term Evolution (LTE) and 5G New Radio (NR). ) important techniques used in . The high frequency modulated signal is demodulated by a Fast Fourier Transform (FFT) algorithm. But more and more broadband systems put forward higher requirements for digital demodulation. For example, the increased bandwidth and channels make the power and area of the digital domain unacceptable. Therefore, the current demodulation is more inclined to process this process in the analog domain, so as to reduce the performance requirements of the subsequent ADC.

In the current existing analog front-end FFT algorithm system design, one is to complete all addition and multiplication operations in the form of a purely passive switched capacitor circuit. Among them, the addition process realizes the voltage addition process through the standard charge redistribution process, and the multiplication requires an uncharged empty capacitor and two capacitors that store the charge representing the charge to be performed to realize the coefficient multiplication through charge redistribution. Such a purely passive form has high accuracy, but due to the need to balance kT/C noise and the effects of charge injection and clock feedthrough, etc., the required capacitance area is large and the trade-off between switching speed and accuracy is also limited. the speed of such a system. Another operation that uses op amps for multiplication and addition is a big limitation on accuracy, and there is no big advantage in power consumption.

At present, there is no analog front-end FFT system that can realize higher precision at high speed at home and abroad. Therefore, the present invention proposes an analog front-end design that realizes FFT algorithm in the current domain, which can avoid all addition operations to generate additional hardware. In the current domain, the calculation accuracy of the multiplication can be controlled by the current mirror to achieve higher accuracy.

SUMMARY OF THE INVENTION

The present invention provides a current domain system design based on FFT algorithm and applied to analog front-end signal processing, which can realize a 64-channel current domain FFT algorithm system and achieve high speed and medium precision.

In order to achieve the above purpose, the present invention adopts a fully differential circuit system, the input uses a bootstrap boost capacitor lower-level board sampling module, and then converts the discrete voltage signal into a current signal through the current-assisted local negative feedback transconductance amplifier Gm, and then passes The FFT calculation module converts the signal in the time domain into a signal with specific frequency information to complete all FFT operations, and finally realizes the function of converting the current signal back to the voltage signal through a transimpedance amplifier _AR with source negative feedback.

The specific FFT algorithm selects the radix-4 time decimation butterfly algorithm, and the series of the calculation system can be determined according to the different number of points. The multiplication accuracy in the system circuit is chosen according to this algorithm to confirm the actual circuit accuracy. Figure 1 is a schematic diagram of the basic butterfly of the radix-4 time extraction algorithm. Compared with the traditional radix-2 algorithm, the radix-4 time extraction butterfly algorithm has a certain degree of increase in the complexity of the basic matrix, but under the same number of points, the radix-4 butterfly algorithm takes the power of 4 as the base, so it can be The number of operation stages is reduced by half, which can further reduce the transmission of noise in practical circuits, thereby improving linearity and accuracy.

The FFT calculation core module adopts the calculation method in the current domain, and by using the calculation method in the current domain, additional hardware modules can be avoided for addition in the calculation. The addition of current is realized by hardware wiring. At the same time, the multiplication of the current coefficient is calculated by the proportional amplification function of the current mirror, which accelerates the calculation speed of the entire system. The cascode current mirror ensures the calculation accuracy of the current ratio calculation. Among them, the cascode transistor adopts a self-cascade structure to achieve stable drain-source voltage in a low power supply voltage environment.

The input and output conversion stages of the FFT calculation all use a local negative feedback method to realize high-speed transconductance amplifiers and transimpedance amplifiers. Among them, the high-speed transconductance amplifier adopts the current auxiliary branch to open the shunt at each peak value of the differential signal, so as to realize the high linearity design under the smaller gain. The high-speed transimpedance amplifier adopts the form of source negative feedback to reduce the equivalent noise effect of the tail current source to realize a high-gain high-precision transimpedance amplifier.

The advantages of the invention are as follows: compared with other analog front-end FFT algorithm circuit systems, the radix-4 time decimation butterfly algorithm is selected, and the number of stages is reduced by half compared with the traditional radix-2 time decimation butterfly algorithm under the same number of points. , which first has advantages at the algorithm level, that is, for practical circuits, more series means greater noise transfer, because the reduction of series will reduce noise from the system level, while the base-4 time The improvement of the complexity of the basic matrix brought by the extraction is only the improvement of the matrix size, and does not involve the increase of the angle of the unit circle, so it will bring great benefits in the actual circuit.

At the same time, the system adopts the implementation of the current domain. Compared with the traditional implementation of the voltage domain, the additional hardware overhead of all addition operations can be completely avoided, because the addition of the current can be completed only by wire connection. Another advantage of operating in the current domain is that the speed is very fast. Here, using the cascode current mirror as the current coefficient multiplier to adjust the size of the tail pipe to control the size of the parasitic capacitance can greatly increase the -3dB bandwidth, thereby reducing Limit the speed in FFT simulation calculations. The use of transconductance and transimpedance amplifiers with local negative feedback can achieve faster speeds on the premise that the accuracy of the input-output conversion stage is greater than the accuracy of the entire system, and the auxiliary current feedback branch and source negative feedback branch will not generate The large power consumption further ensures the power consumption of the overall system.

Description of drawings

Figure 1 is the basic block diagram of the radix-4 time decimation FFT butterfly algorithm.

FIG. 2 is an overall frame diagram of a current domain system design based on an FFT algorithm and applied to analog front-end signal processing provided by the present invention.

FIG. 3 is a circuit diagram of an input conversion stage of a current domain system design based on FFT algorithm and applied to analog front-end signal processing provided by the present invention.

FIG. 4 is a circuit diagram of an output conversion stage of a current domain system design based on FFT algorithm and applied to analog front-end signal processing provided by the present invention.

Detailed ways

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

First of all, the system is a discrete time processing system, so after the input signal enters the system, a sample and hold module needs to be performed to obtain a discrete voltage input signal. In order to maintain a constant switch on-resistance Ron, the accuracy of sampling is much higher than the accuracy of the system so that the accuracy of the system is not affected. The specific sampling and holding module is a sampling switch with bootstrap, and then in order to prevent the influence of charge injection, etc., the input signal is sampled successively according to the clock control in the form of capacitor lower plate sampling, and the clock adopts a 64-channel non-overlapping clock. Each switch is controlled. The capacitance value selection of the sampling capacitor Cs here is mainly selected according to the influence of kT/C noise.

The input signal enters the input conversion stage after sampling. The specific circuit of the input conversion stage is shown in Figure 3. It is a fully differential transconductance stage circuit. In order to maintain good linearity, the current on the road is converted into a current signal and a cascode current mirror is used as the output stage, which can improve the output impedance to achieve higher current accuracy.

After the input signal passes through the input conversion stage, it enters the calculation module of the FFT algorithm. The order of the input signal is arranged according to the input order in the radix-4 algorithm, and then the corresponding coefficient multiplication and current are carried out according to the multiplication coefficient determined by the twiddle factor of each stage. Addition operation. Here, the size of the current is controlled by adjusting the width-length ratio of the pair of tubes that controls the proportional coefficient of the current to control the speed.

Finally, through the output conversion stage, the calculated current signal is converted into a voltage signal. In order to reduce the contribution of the current source tube to the equivalent noise, the source negative feedback method is used to reduce the noise contribution, and the resistor R is used to adjust the level of this stage. The gain makes the output signal swing within a suitable range.

Claims (4)

1. The invention provides a current domain system design applied to analog front end signal processing based on FFT algorithm, which is used for analog front end processing when a radio frequency front end receiver receives an extremely high frequency modulation multi-frequency signal, and is characterized by comprising the following steps: the system comprises an input front-end ultrahigh frequency sampling and holding circuit, an input transconductance amplifier, an FFT (fast Fourier transform) calculation core module and an output transimpedance amplifier, wherein the input front-end ultrahigh frequency sampling and holding circuit is used for realizing subsequent discrete Fourier transform calculation, the input transconductance amplifier is used for converting an input discrete voltage signal into a current signal, the FFT calculation core module is used for performing multiply-add operation on a time domain current signal to convert the time domain current signal into a current value representing frequency domain information, and the output transimpedance amplifier is used for converting the current signal after FFT operation into a voltage signal.

2. The design of the current domain system applied to analog front end signal processing based on the FFT algorithm as claimed in claim 1, wherein the selected algorithm is the radix-4 butterfly algorithm, the number of stages of the computing system can be determined according to different points, the number of stages of the system and the complexity of the basic multiply-add operation are determined by the selection of the algorithm, and the multiplication precision in the system circuit is selected according to the algorithm to confirm the actual circuit precision.

3. The design of the current domain system applied to analog front-end signal processing based on the FFT algorithm as recited in claim 2, wherein the FFT computation core module adopts a current domain computation method, the current domain computation method can avoid the use of an additional hardware module for addition in computation, the current addition is realized in a hardware wire connection manner, and the current coefficient multiplication is computed through the proportional amplification function of the current mirror, so as to accelerate the computation speed of the whole system, the cascode current mirror ensures the computation accuracy of the current proportion computation, and the cascode tube therein adopts a self-cascade structure to realize stable drain-source voltage in a low supply voltage environment.

4. The current domain system design applied to analog front-end signal processing based on the FFT algorithm as recited in claim 3, wherein the input/output conversion stages of the FFT computation all use a local negative feedback manner to implement a high-speed transconductance amplifier and a transimpedance amplifier, wherein the high-speed transconductance amplifier uses a current auxiliary branch to turn on and shunt at each peak of the differential signal to implement a high linearity design with a small gain, and the high-speed transimpedance amplifier uses a source negative feedback manner to reduce the equivalent noise effect of the tail current source to implement a high-gain high-precision transimpedance amplifier.

Images