CN114510897A - A Physical Verification Method of Standard Cell Library - Google Patents

Abstract

The application provides a physical verification method of a standard cell library, which comprises the following steps: randomly selecting a first unit, a second unit, a third unit, a fourth unit and a fifth unit which are arranged according to the width; splicing each unit with the self and other units left and right respectively, and marking the spliced units as a standard unit I, a standard unit II, a standard unit III, a standard unit IV and a standard unit V; each unit is spliced left and right with the left and right mirror images of the unit, and then the unit is spliced left and right, and the unit is marked as a mirror image unit I, a mirror image unit II, a mirror image unit III, a mirror image unit IV and a mirror image unit V; respectively splicing each unit and the corresponding mirror image unit up and down, and marking as a splicing unit I, a splicing unit II, a splicing unit III, a splicing unit IV and a splicing unit V; splicing the standard units I to five and the splicing units I to five into a test layout; and checking the design rule of the test layout.

Description

A Physical Verification Method of Standard Cell Library

technical field

The present application relates to the field of integrated circuit design, and in particular, to a physical verification method of a standard cell library.

Background technique

The standard cell library is a collection of basic logic cells developed based on mature and stable processes. Each standard cell library has hundreds to thousands of cells, and the cell types are very rich, including basic cells, combinational logic cells, sequential logic cells, and special cells. The standard cell library is the basic database for the automatic design of very large scale integrated circuits (VLSI, Very Large Scale Integration). , place and route library and other data.

With the improvement of the integration and working speed of monolithic integrated circuits, it has become a necessary condition for VLSI chip design to design and develop a standard cell library that complies with process design rules, has correct logic functions, complete model data and accurate electrical characteristics. After the standard cell library is developed, the system must be fully tested and verified. It is very important to ensure the integrity and accuracy of the standard cell library, which is the key to ensuring the success of chip design and tape-out.

With the rapid development of integrated circuit technology, especially when entering the process nodes of 40nm, 28nm, 14nm FinFET, etc., the design of the standard cell library has become more and more complicated, and the layout design of a single cell has also become very complicated. , the physical verification of the cell library becomes particularly important.

However, the current physical verification of standard cell libraries remains problematic. Therefore, it is necessary to develop more efficient and reliable technical solutions.

SUMMARY OF THE INVENTION

The present application provides a physical verification method for a standard cell library, which can accurately present the design rule verification errors of the standard cell library, and can cover various situations in an all-round way. The method is simple and fast, and waste is avoided.

The present application provides a physical verification method for a standard cell library, comprising: randomly selecting five types of cells to be tested arranged by width as a standard cell library, which are respectively marked as cell one, cell two, cell three, cell four and cell five; Splicing each unit with itself and other units on the left and right respectively, and label the spliced units as standard unit 1, standard unit 2, standard unit 3, standard unit 4 and standard unit 5; The mirror image is spliced left and right, and then left and right splicing is performed, and the spliced units are marked as mirror unit 1, mirror unit 2, mirror unit 3, mirror unit 4 and mirror unit 5; each unit and the corresponding mirror unit are spliced up and down respectively. , mark the spliced units as splicing unit 1, splicing unit 2, splicing unit 3, splicing unit 4 and splicing unit 5; splicing the standard unit 1 to standard unit 5 and the splicing unit 1 to splicing unit 5 into a test layout ; perform a design rule check on the test layout.

In some embodiments of the present application, the order of the width of the five units to be tested is: unit 1 > unit 2 > unit 3 > unit 4 > unit 5.

In some embodiments of the present application, the width is the dimension in the left-right direction.

In some embodiments of the present application, each unit is spliced left and right with itself and other units, and the spliced units are marked as standard unit 1, standard unit 2, standard unit 3, standard unit 4 and standard unit 5, including : Unit 1 is spliced left and right with unit 1 to unit 5, and marked as standard unit 1; unit 2 is spliced left and right with unit 2 to unit 5, and marked as standard unit 2; unit 3 is respectively connected with unit 3 to Unit 5 is spliced left and right, and marked as standard unit 3; unit 4 is spliced left and right with unit 4 and unit 5, and marked as standard unit 4; unit 5 and unit 5 are spliced left and right, and marked as standard unit 5 .

In some embodiments of the present application, each unit is spliced left and right with its own left and right mirror images, and then left and right splicing is performed, and the spliced units are marked as mirror unit 1, mirror unit 2, mirror unit 3, and mirror unit 4. And the mirror image unit 5 includes: respectively splicing units 1 to 5 with their respective left and right mirror images, and then splicing them left and right, and marking it as mirror unit 1; respectively splicing units 2 to 5 with their respective left and right mirror images Perform left and right splicing, and mark it as mirror unit 2; respectively splicing units 3 to 5 with their respective left and right mirror images, and then perform left and right splicing, and mark it as mirror unit 3; The mirror image is spliced left and right, and then left and right spliced, and marked as mirror image unit four; the left and right mirror images of unit five and unit five are left and right spliced, and marked as mirror image unit five.

In some embodiments of the present application, each unit and the corresponding mirror image unit are spliced up and down respectively, and the spliced units are marked as splicing unit 1, splicing unit 2, splicing unit 3, splicing unit 4 and splicing unit 5 include: : splicing several units one on the upper and lower sides of the mirror unit one, the total width of the several units one is greater than or equal to the width of the mirror image unit one, wherein, when the mirror image unit one is smaller than the width of the several units one , the insufficient part is filled with unit five, and the unit after splicing is marked as splicing unit one; several units two are spliced on the upper and lower sides of mirror unit two, and the total width of said several units two is greater than or equal to the width of said mirror unit two , wherein, when the mirror image unit two is smaller than the width of the several units two, the insufficient part is filled with the unit five, and the spliced unit is marked as the splicing unit two; several units three are spliced on the upper and lower sides of the mirror image unit three , the total width of the plurality of units 3 is greater than or equal to the width of the mirror unit 3, wherein, when the mirror unit 3 is smaller than the width of the plurality of units 3, the insufficient part is filled with unit 5, and the spliced unit marks It is the splicing unit 3; several units 4 are spliced on the upper and lower sides of the mirror image unit 4, and the total width of the several units 4 is greater than or equal to the width of the mirror image unit 4, wherein, when the mirror image unit 4 is larger than the several units When the width of four is small, the insufficient part is filled with unit five, and the unit after splicing is marked as unit four; several units five are spliced on the upper and lower sides of the mirror unit five, and the total width of the several units five is equal to the mirror unit. The width of five, the spliced unit is marked as spliced unit five.

In some embodiments of the present application, splicing the standard unit 1 to the standard unit 5 and the splicing unit 1 to the splicing unit 5 into a test layout includes: arranging the standard unit 1 to the standard unit 5 in three rows up and down respectively, and arranging longitudinally in sequence In the lower left corner of the layout; splicing splicing unit 1 to splicing unit 5 on the right side of the corresponding standard unit 1 to standard unit 5 respectively, and move one step to the right in turn until the splicing is completed; complete the test in the moved gap filling unit 5 territory.

In some embodiments of the present application, the method for calculating the number of steps is: dividing the width of the corresponding unit by the width of unit five.

In some embodiments of the present application, when standard cells 1 to 5 are arranged in three rows up and down, and are vertically arranged in the lower left corner of the layout in order, if the power types of adjacent standard cells are different, one of the standard cells needs to be installed Mirror up and down.

In some embodiments of the present application, the test layout is rectangular.

In the physical verification method of the standard cell library described in this application, five kinds of cells to be tested are randomly selected according to the size, and the five kinds of cells to be tested are randomly spliced in all directions, and then physical verification is carried out, so that the standard cell library can be accurately presented The design rule verification error can cover all kinds of situations in all aspects, the method is simple and fast, and waste is avoided.

Description of drawings

The following drawings describe in detail exemplary embodiments disclosed in this application. Where like reference numbers refer to similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, the accompanying drawings are for illustration and description purposes only, and are not intended to limit the scope of the application, and other embodiments are also possible The same accomplishes the inventive intent in this application. It should be understood that the figures are not drawn to scale. in:

Fig. 1 is the flow chart of the physical verification method of the standard cell library described in the embodiment of the application;

FIG. 2 is a schematic structural diagram of a test layout in the physical verification method of a standard cell library according to an embodiment of the present application.

Detailed ways

The following description provides specific application scenarios and requirements of the present application, and is intended to enable those skilled in the art to make and use the contents of the present application. Various partial modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and without departing from the spirit and scope of the application. application. Therefore, the present application is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical solutions of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

The verification after the completion of the standard cell design of a semiconductor integrated circuit requires not only Design Rule Check (DRC), Layout Versus Schematic test (LVS), and Electrical Rule Check (ERC) The verification of the entire standard cell library also needs to be verified. In some verification methods, the physical verification of the entire cell library is verified by Cadence's EDI and Synopsys' ICCAPR tool, but this verification method has the following shortcomings: the design is relatively small; All are taken into account; too many resources would be wasted to verify at the process level.

In view of the above problems, the present application provides a method for physical verification of a standard cell library. Five types of cells to be tested are randomly selected according to their size, and the five types of cells to be tested are randomly spliced in all directions, and then physical verification is carried out, which can accurately The design rule verification errors of the standard cell library are presented, which can cover various situations in all aspects, and the method is simple and fast, avoiding waste.

FIG. 1 is a flowchart of a physical verification method for a standard cell library according to an embodiment of the present application. Referring to FIG. 1 , an embodiment of the present application provides a physical verification method for a standard cell library, including:

Step S110: randomly select five types of cells to be tested arranged by width as a standard cell library, which are respectively marked as cell one, cell two, cell three, cell four and cell five;

Step S120: splicing each kind of unit with itself and other units left and right respectively, marking the spliced units as standard unit one, standard unit two, standard unit three, standard unit four and standard unit five;

Step S130 respectively performs left-right splicing of each unit with its own left and right mirror images, and then performs left-right splicing, and marks the spliced units as mirror unit 1, mirror unit 2, mirror unit 3, mirror unit 4, and mirror unit 5;

Step S140: splicing each unit and the corresponding mirror image unit up and down respectively, and marking the spliced units as splicing unit 1, splicing unit 2, splicing unit 3, splicing unit 4 and splicing unit 5;

Step S150: splicing the standard unit 1 to the standard unit 5 and the splicing unit 1 to the splicing unit 5 into a test layout;

Step S160: Perform design rule checking on the test layout.

The physical verification method of the standard cell library described in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1 , in step S110 , five types of cells to be tested arranged by width are randomly selected as a standard cell library, which are respectively marked as cell one, cell two, cell three, cell four and cell five.

Table 1

Table 1 shows the names and structures of the five units to be tested.

Referring to Table 1, in some embodiments of the present application, the order of the width of the five units to be tested is: unit 1 > unit 2 > unit 3 > unit 4 > unit 5. In some embodiments of the present application, the width is the dimension in the left-right direction.

Wherein, the unit 1, unit 2, unit 3 and unit 4 are functional units, unit 5 may be a filling unit or a functional unit, and the width of unit 5 is the smallest basic unit width, namely unit 1 and unit 2 The widths of unit 3 and unit 4 are all integer multiples of the width of unit 5.

In addition, it should be noted that the size relationship between the five units to be tested is shown in Table 1 according to the size ratio, but in the following, different units to be tested will be randomly spliced. The size of the unit to be tested is drawn as the same size (different units to be tested are represented by the shape of the same cell, and are distinguished only by different filling patterns), which is only used to illustrate how different units to be tested are spliced together.

Table 2

Table 2 shows the schematic structures of the five units to be tested.

Referring to Table 2, for the sake of simplicity, cells with the same size and different patterns are used to represent different units to be tested, wherein sub-tables A and B represent the left and right sides of each unit to be tested. In the following text, the unit to be tested needs to be randomly spliced, and the splicing of different sides is also different, so it is necessary to use different symbols to distinguish the left side and the right side.

Continue to refer to as shown in FIG. 1, step S120, splicing each kind of unit with itself and other units left and right respectively, marking the spliced units as standard unit one, standard unit two, standard unit three, standard unit four and standard unit five .

table 3

Table 3 shows the schematic structures of different standard cells.

Referring to Table 3, in some embodiments of the present application, each unit is spliced left and right with itself and other units, and the spliced units are marked as standard unit one, standard unit two, standard unit three, and standard unit. 4 and standard unit 5, the performed splicing includes: splicing unit 1 to unit 1 to unit 5 left and right respectively, and marking it as standard unit 1; splicing unit 2 to unit 2 to unit 5 respectively left and right, and marking it as standard Unit 2; splicing unit 3 with unit 3 to unit 5 left and right respectively, and mark it as standard unit 3; splicing unit 4 with unit 4 and unit 5 respectively left and right, and label it as standard unit 4; unit 5 and unit Five are spliced left and right and marked as standard unit five.

The purpose of step S120 is to realize the left and right splicing between any two units (including the same unit). Specifically, referring to Table 3, the standard unit one includes the splicing of unit one and unit one (including the splicing of different sides, That is, A is connected to A, B is connected to B, and A is connected to B); the splicing of unit one and unit two (including the splicing of different sides, that is, A is connected to A, B is connected to B, and A is connected to B); the splicing of unit one and unit three ( Including the splicing of different sides, that is, A is connected to A, B is connected to B, and A is connected to B); the splicing of unit one and unit four (including the splicing of different sides, that is, A is connected to A, B is connected to B, and A is connected to B); unit one Splicing with unit five (including splicing on different sides, that is, A to A, B to B, and A to B).

Similarly, referring to Table 3, the standard unit 2 includes the splicing of unit 2 and unit 2 (including splicing on different sides, that is, A connects to A, B connects to B, and A connects to B); the splicing of unit 2 and unit 3 (including the splicing of different sides, that is, A is connected to A, B is connected to B, and A is connected to B); the splicing of unit two and unit four (including the splicing of different sides, that is, A is connected to A, B is connected to B, and A is connected to B); unit The splicing of the second and the fifth unit (including the splicing of different sides, that is, A to A, B to B, and A to B).

Similarly, by analogy, the standard unit 3 includes the splicing of unit 3 and unit 3 to unit 5; the standard unit 4 includes the splicing of unit 4 and unit 4 and the splicing of unit 4 and unit 5; the standard unit 5 realizes the splicing of unit 5 And the splicing of unit five.

As can be seen from the above, step S120 can realize all left and right splicing between any two units.

In some embodiments of the present application, the order of the width of the five standard cells is: standard cell one > standard cell two > standard cell three > standard cell four > standard cell five. In some embodiments of the present application, the width is the dimension in the left-right direction.

Continue to refer to Fig. 1, step S130, carry out left and right splicing of each kind of unit and its mirror image on the left and right respectively, then carry out left and right splicing, mark the unit after splicing as mirror unit one, mirror unit two, mirror unit three, mirror unit four and Mirror unit five.

Table 4

Table 4 shows the schematic structures of different mirror units.

Referring to Table 4, in some embodiments of the present application, each unit is spliced left and right with its own left and right mirror images, and then left and right splicing is performed, and the spliced units are marked as mirror unit one, mirror unit two, and mirror images. Unit 3, mirror unit 4 and mirror unit 5 include: unit 1 to unit 5 are respectively spliced left and right with their respective left and right mirror images, and then left and right spliced, and marked as mirror unit 1; The mirror image is spliced left and right, and then left and right spliced, and marked as mirror unit 2; unit 3 to unit 5 are respectively spliced left and right with their respective left and right mirrors, and then left and right spliced, and marked as mirror unit 3; unit 4 and unit 4 and Unit 5 is spliced left and right with the respective left and right mirror images, and then left and right splicing is performed, and is marked as mirror image unit 4; Unit 5 and the left and right mirror images of unit 5 are spliced left and right, and marked as mirror image unit 5.

The purpose of step S130 is to realize mirror splicing of different units and re-splicing after mirror splicing, so as to prepare for the next step to realize top-bottom splicing.

In some embodiments of the present application, the order of the width of the five mirroring units is: mirroring unit 1 > mirroring unit 2 > mirroring unit 3 > mirroring unit 4 > mirroring unit 5. In some embodiments of the present application, the width is the dimension in the left-right direction.

Continue to refer to as shown in Figure 1, step S140, each kind of unit and the corresponding mirror image unit are respectively spliced up and down, and the spliced units are marked as splicing unit 1, splicing unit 2, splicing unit 3, splicing unit 4 and splicing unit 5 .

table 5

Table 5 shows the schematic structures of different splicing units.

Referring to Table 5, in some embodiments of the present application, each kind of unit and the corresponding mirror image unit are respectively spliced up and down, and the spliced units are marked as splicing unit 1, splicing unit 2, splicing unit 3, splicing unit. Fourth and the splicing unit 5, the splicing performed includes: splicing several units one on the upper and lower sides of the mirror image unit one, the total width of the several units one is greater than or equal to the width of the mirror image unit one, wherein, when the mirror image unit one Unit one is smaller than the width of several units one, the insufficient part is filled with unit five, and the unit after splicing is marked as unit one; several units two are spliced on the upper and lower sides of mirror unit two, and the two units are The total width is greater than or equal to the width of the mirror image unit 2, wherein, when the mirror image unit 2 is smaller than the width of the several units 2, the insufficient part is filled with the unit 5, and the spliced unit is marked as the splicing unit 2; Unit 3 is spliced on the upper and lower sides of mirror unit 3, and the total width of the plurality of units 3 is greater than or equal to the width of the mirror unit 3. Wherein, when the mirror unit 3 is smaller than the width of the plurality of units 3, insufficient Parts are filled with unit 5, and the unit after splicing is marked as splicing unit 3; several units 4 are spliced on the upper and lower sides of the mirror image unit 4, and the total width of the several units 4 is greater than or equal to the width of the mirror image unit 4, wherein, When the width of the mirror image unit 4 is smaller than the width of the several units 4, the insufficient part is filled with the unit 5, and the spliced unit is marked as the splicing unit 4; The total width of several units five is equal to the width of the mirror image unit five, and the unit after splicing is marked as splicing unit five.

It should be noted that Table 5 only schematically shows how different splicing units are formed by splicing. When the width of the mirror image unit is smaller than that of the corresponding units, the insufficient part is filled with unit 5, which is omitted in Table 5 for filling. unit five.

In some embodiments of the present application, the order of the width of the five splicing units is: splicing unit 1 > splicing unit 2 > splicing unit 3 > splicing unit 4 > splicing unit 5. In some embodiments of the present application, the width is the dimension in the left-right direction.

The purpose of step S140 is to realize the top-bottom splicing of each unit and any unit, including the top-bottom splicing of different sides (A and A, A and B, B and B). Specifically, similar to step S120 to realize the left and right splicing of any two units, as shown in Table 5, the splicing unit 1 includes the upper and lower splicing of the unit 1 and the unit 1; the upper and lower splicing of the unit 1 and the unit 2; the unit 1 and the unit The upper and lower splicing of unit 3; the upper and lower splicing of unit 1 and unit 4; the upper and lower splicing of unit 1 and unit 5.

Similarly, by analogy, the splicing unit 2 includes the upper and lower splicing of the unit 2 and the unit 2 to the unit 5; the splicing unit 3 includes the upper and lower splicing of the unit 3 and the unit 3 to the unit 5; the splicing unit 4 includes the unit 4. The upper and lower splicing of unit 4 and unit 4 and unit 5; the splicing unit 5 realizes the upper and lower splicing of unit 5 and unit 5.

Continuing to refer to FIG. 1, in step S150, the standard unit 1 to the standard unit 5 and the splicing unit 1 to the splicing unit 5 are spliced into a test layout.

FIG. 2 is a schematic structural diagram of a test layout in the physical verification method of a standard cell library according to an embodiment of the present application.

Referring to FIG. 2 , in some embodiments of the present application, splicing the standard unit 1 to the standard unit 5 and the splicing unit 1 to the splicing unit 5 into a test layout includes: arranging the standard unit 1 to the standard unit 5 up and down respectively. Three rows are arranged vertically in the lower left corner of the layout in sequence; splicing unit 1 to splicing unit 5 are respectively spliced to the right side of the corresponding standard unit 1 to standard unit 5, and move one step to the right in turn until the splicing is completed; after moving The void-filling unit five completes the beta layout.

In some embodiments of the present application, the method for calculating the number of steps is: dividing the width of the corresponding unit by the width of unit five. For example, the width of unit one is 12.04 microns, and the width of unit five is 0.28 microns, then the splicing unit one moves to the right by 12.04/0.28 steps, that is, 43 steps. The distance of each step can be equal to the minimum distance (width of unit five) 0.28 microns, or it can be an integer multiple of the width of unit five, that is, an integer multiple of 0.28 microns.

In some embodiments of the present application, when standard cells 1 to 5 are arranged in three rows up and down, and are vertically arranged in the lower left corner of the layout in order, if the power types of adjacent standard cells are different, one of the standard cells needs to be installed Mirror up and down.

In some embodiments of the present application, the test layout is rectangular. Referring to Figure 2, in order to make the entire layout into a rectangle, several units five can be used to fill all the empty places, and the entire layout can be supplemented into a rectangle to avoid unnecessary falsehoods.

In some embodiments of the present application, during the splicing process of the entire layout, it is noted that the boundaries of each unit in the horizontal direction and the vertical direction are flush to avoid errors.

In some embodiments of the present application, step 110 , step 120 , step 130 , step 140 , and step 150 do not represent a sequence.

The layout shown in Figure 2 can ensure that all units can be involved in any direction of up and down splicing, left and right splicing, and mirror splicing, ensuring full coverage of verification.

Continuing to refer to FIG. 1 , in step S160, a design rule check is performed on the test layout. The test layout can be checked for design rules using any suitable tool or software or the like.

In some embodiments of the present application, the standard cell library may be adjusted according to the inspection report generated after the design rule inspection is performed.

In the physical verification method of the standard cell library described in this application, five kinds of cells to be tested are randomly selected according to the size, and the five kinds of cells to be tested are randomly spliced in all directions, and then physical verification is carried out, so that the standard cell library can be accurately presented The design rule verification error can cover all kinds of situations in all aspects, the method is simple and fast, and waste is avoided.

In conclusion, after reading the contents of this application, those skilled in the art can understand that the foregoing contents of the application may be presented by way of example only, and may not be limiting. Although not explicitly described herein, it will be understood by those skilled in the art that this application is intended to cover various reasonable changes, improvements and modifications to the embodiments. Such changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

It should be understood that the term "and/or" as used in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

It should be understood that the terms "comprising", "including", "including" or "including", when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements and/or components, but The presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof is not excluded.

It will also be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference signs refer to the same elements throughout the specification.

Furthermore, this specification describes exemplary embodiments with reference to idealized exemplary cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes illustrated are foreseeable due to, for example, manufacturing techniques and/or tolerances. Thus, example embodiments should not be construed as limited to the shapes of regions shown herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched area shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device nor to limit the scope of example embodiments.

Claims (10)

1. A physical verification method for a standard cell library, comprising:

randomly selecting five units to be tested which are arranged according to the width as a standard unit library, and respectively marking the units as a unit I, a unit II, a unit III, a unit IV and a unit V;

each unit is spliced with the self unit and other units left and right respectively, and the spliced units are marked as a standard unit I, a standard unit II, a standard unit III, a standard unit IV and a standard unit V;

each unit is spliced left and right with the left and right mirror image of the unit, and then the unit after splicing is marked as a mirror image unit I, a mirror image unit II, a mirror image unit III, a mirror image unit IV and a mirror image unit V;

respectively splicing each unit with the corresponding mirror image unit up and down, and marking the spliced units as a splicing unit I, a splicing unit II, a splicing unit III, a splicing unit IV and a splicing unit V;

splicing the standard units I to five and the splicing units I to five into a test layout;

and checking the design rule of the test layout.

2. The physical verification method of a standard cell library of claim 1, wherein the width of the five units under test are in the order of: unit one > unit two > unit three > unit four > unit five.

3. The physical verification method of a standard cell library of claim 1, wherein the width is a dimension in the left-right direction.

4. The physical verification method of the standard cell library of claim 1, wherein each cell is left-right spliced with itself and other cells, and the spliced cells are labeled as standard cell one, standard cell two, standard cell three, standard cell four and standard cell five, comprising:

splicing the first unit with the first unit to the fifth unit left and right respectively, and marking the first unit as a standard unit I;

splicing the unit two with the units two to five left and right respectively, and marking as a standard unit two;

splicing the unit III with the units III to V left and right respectively, and marking as a standard unit III;

splicing the unit four with the unit four and the unit five respectively left and right, and marking as a standard unit four;

and splicing the unit five and the unit five left and right, and marking as a standard unit five.

5. The physical verification method of the standard cell library of claim 1, wherein the step of splicing each cell with its own left and right mirror image left and right respectively and then left and right, and the step of marking the spliced cells as mirror image cell one, mirror image cell two, mirror image cell three, mirror image cell four and mirror image cell five comprises the steps of:

splicing the units I to V with the respective left and right mirror images left and right, then splicing left and right, and marking as mirror image unit I;

splicing the units two to five with the respective left and right mirror images left and right, then splicing left and right, and marking as a mirror image unit two;

splicing the units three to five with the respective left and right mirror images left and right, then splicing left and right, and marking as a mirror image unit three;

respectively splicing the unit four and the unit five with respective left and right mirror images, then splicing left and right, and marking as a mirror image unit four;

and splicing the unit five and the left and right mirror images of the unit five left and right, and marking as a mirror image unit five.

6. The physical verification method of the standard cell library of claim 1, wherein each cell is vertically spliced with the corresponding mirror image cell, and the spliced cells are marked as splicing cell one, splicing cell two, splicing cell three, splicing cell four and splicing cell five, comprising:

splicing a plurality of units I on the upper side and the lower side of a mirror image unit I, wherein the total width of the units I is more than or equal to that of the mirror image unit I, when the mirror image unit is smaller than the width of the units I, the insufficient parts are filled with a unit V, and the spliced units are marked as splicing units I;

splicing a plurality of second units on the upper side and the lower side of the second mirror image unit, wherein the total width of the second units is larger than or equal to that of the second mirror image unit, when the second mirror image unit is smaller than the width of the second units, the insufficient parts are filled with fifth units, and the spliced units are marked as second splicing units;

splicing a plurality of units III on the upper side and the lower side of a mirror image unit III, wherein the total width of the unit III is more than or equal to that of the mirror image unit III, when the mirror image unit III is smaller than the width of the unit III, the insufficient part is filled with a unit V, and the spliced unit is marked as a spliced unit III;

splicing a plurality of units IV on the upper side and the lower side of a mirror image unit IV, wherein the total width of the unit IV is more than or equal to the width of the mirror image unit IV, when the mirror image unit IV is smaller than the width of the unit IV, the insufficient part is filled with a unit V, and the spliced unit is marked as a spliced unit IV;

splicing the five units on the upper side and the lower side of the mirror image unit five, wherein the total width of the five units is equal to that of the mirror image unit five, and the spliced unit is marked as a spliced unit five.

7. The physical verification method of the standard cell library according to claim 1, wherein the splicing of the standard cells one to five and the splicing of the splicing cells one to five into a test layout comprises:

respectively arranging three rows of standard units from one standard unit to five standard units from top to bottom, and longitudinally arranging the standard units at the lower left corner of the layout in sequence;

splicing the first splicing unit to the fifth splicing unit to the right sides of the corresponding first standard unit to the fifth standard unit respectively, and moving the first splicing unit to the right side of the corresponding fifth standard unit by one step number in a rightward mode until the splicing is finished;

and completing the test layout in the moved gap filling unit V.

8. The physical verification method of a standard cell library of claim 7, wherein the step count is calculated by: the width of the corresponding cell is divided by the width of cell five.

9. The physical verification method of the standard cell library according to claim 7, wherein three rows of the first standard cell to the fifth standard cell are arranged up and down respectively, and when the standard cells are longitudinally arranged at the lower left corner of the layout in sequence, if the power types of the adjacent standard cells are different, one of the standard cells needs to be mirrored up and down.

10. The method of physical verification of a library of standard cells of claim 1 wherein the test layout is rectangular.

Images