CN114510899B - Chip wiring method, chip wiring device, electronic equipment and storage medium - Google Patents
Chip wiring method, chip wiring device, electronic equipment and storage medium Download PDFInfo
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- CN114510899B CN114510899B CN202210175248.6A CN202210175248A CN114510899B CN 114510899 B CN114510899 B CN 114510899B CN 202210175248 A CN202210175248 A CN 202210175248A CN 114510899 B CN114510899 B CN 114510899B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
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Abstract
The invention relates to a chip wiring method, a chip wiring device, an electronic device and a storage medium, wherein the chip wiring method comprises the steps of adjusting wiring spacing between adjacent wires based on wiring parameters of the wires in an initial wiring state report, and generating a predicted wiring state report; the routing parameters include at least one of routing density, routing type, and corresponding empirical defect size distribution, and routing the chip based on the predicted routing status report. The invention solves the technical problem that the prior art can not well control the chip failure probability caused by the chip defect, and reduces the probability of the chip failure caused by the defect falling on the chip wiring or between the wirings by a method of the back-end physical realization.
Description
Technical Field
The invention belongs to the field of layout wiring, and particularly relates to a chip wiring method, a chip wiring device, electronic equipment and a storage medium.
Background
With the development of semiconductor technology, in order to solve the problem of high cost, the requirement on the yield of chips is higher and higher. For the wafer manufacturing factory (Foundry), defects in the manufacturing process cannot be completely avoided due to the complex process of the chip. At present, most of defects controllable by a wafer manufacturing factory can be in the range of tens of nanometers to tens of micrometers, and if the defects fall on a wafer in the manufacturing process, the defects are very easy to cause short circuit and open circuit of internal wiring of a chip, so that the chip is invalid. Therefore, for ultra-large scale deep submicron integrated circuit fabrication, defect is an important factor affecting yield.
Defect generally refers to a physical contamination or imperfection present on a wafer, and is generally caused by several factors:
1. physical variability (e.g., dust, process residues, and abnormal reaction products) on Wafer.
2. Chemical contamination (e.g., residual chemicals, organic solvents).
3. Abnormal imaging caused by pattern defects (such as development (Photo) or lithography (Etch), mechanical scratch deformation, and abnormal color caused by uneven thickness).
4. Wafer itself or lattice defects caused during the manufacturing process.
The existence of layout defects is currently an unavoidable problem in the industry, and especially for very large scale chips, the impact of deadly defects (KILLER DEFECT) on yield is amplified. Therefore, in order to improve the yield of the chip, a special design method is required to be adopted from the design point of view, so that the probability of failure caused by defects in the production process is reduced, and the production yield of the chip is improved.
In the prior art, the failure probability caused by defect of a large-area chip is generally reduced by controlling the manufacturing process flow through the wafer manufacturing factory focus, and capturing the defects in the manufacturing process through various sensors, so as to reduce the number of deadly defects KILLER DEFECT in the manufacturing process as much as possible. In order to meet the requirements of performance, power consumption, area and the like of the chip, the design angle is not used for preventing the defect, so that the probability of failure of the defect is still uncontrollable.
Disclosure of Invention
The invention provides a chip wiring method, a chip wiring device, electronic equipment and a storage medium, which aim to solve the technical problem that the chip failure probability is high due to the fact that the chip defect cannot be well controlled in the prior art. The invention reduces the probability of chip failure caused by the defect falling on the chip wiring or between the wirings by a method of back-end physical realization.
The technical scheme of the invention is as follows:
A chip wiring method comprising the steps of:
Adjusting wiring intervals between adjacent wires based on wiring parameters of the wires in the initial wiring state report to generate a predicted wiring state report, wherein the wiring parameters comprise at least one of wiring density, wiring type and corresponding empirical defect size distribution;
and carrying out wiring design on the chip based on the predicted wiring state report.
Further defined is a step of adjusting a routing pitch between adjacent wires based on routing parameters of the wires in the initial routing status report, comprising:
And adjusting the wiring spacing between adjacent wires in a predetermined area based on the wiring parameters of the wires in the initial wiring status report, wherein the predetermined area is determined based on the wiring density and the empirical defect size.
It is further defined that,
The adjusting of the wiring pitch between adjacent wires includes expanding the wiring pitch between associated wires and/or shrinking the wiring pitch between non-associated wires,
The related wirings comprise wirings which are mutually affected after being conducted;
the non-associated wirings include wirings which do not affect each other after being conducted.
Further defined, the step of adjusting the wiring pitch between adjacent wires in the predetermined area based on the wiring parameters of the wires in the initial wiring status report includes:
dividing the predetermined region into a first predetermined region and a second predetermined region based on the wiring density, the wiring density of the first predetermined region being greater than the wiring density of the second region;
Adjusting the wiring spacing of adjacent wires in the first preset area based on the wiring density, the wire type and the corresponding empirical defect size distribution of the first preset area; and adjusting the wiring spacing of adjacent wires in the second predetermined area based on the wiring density, the wire type and the corresponding empirical defect size distribution of the second predetermined area.
Further defined, the adjacent wirings are two adjacent signal lines, and the wiring distance between the two adjacent signal lines is enlarged by 1.5 times to 2 times.
And further limiting the adjacent wiring to be adjacent power lines and ground lines, and adjusting the distance between the power lines and the ground lines to be larger than the maximum end value of the interval with the largest proportion in the empirical defect size distribution interval.
Further defined, the adjusting the wiring pitch between adjacent wires in the predetermined area includes:
The wiring pitch between adjacent wirings in the predetermined area is determined based on the total area of the predetermined area, the wiring density of the predetermined area, the wiring degree of the predetermined area, and the number of wirings of the predetermined area.
A chip wiring device comprising:
the predicted wiring state report generation module is used for obtaining wiring parameters of the wires in the initial wiring report, and adjusting the wiring spacing between adjacent wires to generate a predicted wiring state report, wherein the wiring parameters comprise at least one of wiring density, wiring type and corresponding empirical defect size distribution;
And a wiring design module that performs wiring design on the chip based on predicting the wiring status report.
An electronic device comprising a processor and a memory coupled to each other, wherein,
The memory is used for storing program instructions for realizing the chip wiring method;
the processor is used for executing the program instructions stored in the memory.
A computer-readable storage medium storing a program file executed to implement the above-described chip wiring method.
The invention has the beneficial effects that:
1. According to the invention, the wiring state report is obtained, and the wiring distance between adjacent wirings is adjusted according to the information (namely the wiring density) of the wiring crowding degree (congestion) in the chip layout wiring stage, so that the probability of defect falling on a signal line is reduced, and the functional failure problem caused by chip signal short circuit or open circuit is reduced.
2. The method comprises the steps of dividing a preset area into a first preset area and a second preset area based on wiring density, dividing the preset area into the first preset area and the second preset area, wherein the wiring density of the first preset area is larger than that of the second area, dividing the adjustable area of the wiring of the whole chip into the first preset area and the second preset area, and adjusting the wiring method according to different crowding types (wiring densities), so that the wiring can be adjusted in a targeted manner according to different wiring densities.
3. According to the chip wiring method provided by the invention, during layout design, the influences of defects are considered, the increase of the widths, the intervals and the like of the wirings is properly regulated, the probability that the defects fall between the power supply and the ground wire is reduced, and the chip failure caused by the defects is effectively prevented.
Drawings
FIG. 1 is a flow chart of a chip wiring method of the present invention;
FIG. 2 is a schematic diagram showing the layout of different layout congestion levels;
FIG. 3 is a schematic diagram of a full chip routing congestion type area division;
FIG. 4 is a diagram showing the defect optimizing effect before and after increasing the wiring pitch;
FIG. 5 is a diagram showing the defect optimizing effect before and after increasing the wiring pitch;
FIG. 6 is a diagram showing defect optimization effects before and after increasing the power network spacing;
FIG. 7 is a schematic diagram of a chip wiring device according to the present invention;
FIG. 8 is a schematic diagram of an electronic device according to the present invention;
FIG. 9 is a schematic diagram of a computer readable storage medium according to the present invention;
wherein, the 1-predictive wiring status report generation module, the 2-wiring design module.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention. The invention provides a chip wiring method, which is realized by a back-end physical method to reduce the probability of chip failure caused by the defect falling on chip wiring or between wirings.
As shown in fig. 1, a flowchart of a chip wiring method according to the present invention is shown, and specifically the method includes:
And step S01, adjusting the wiring spacing between adjacent wires based on the wiring parameters of the wires in the initial wiring state report to generate a predicted wiring state report, wherein the wiring parameters comprise at least one of wiring density, wiring type and empirical defect size distribution.
The wiring density is the total area of the wires per unit area, as shown in fig. 2, the uncongested wires are small in wiring density, the crowded wires are large in wiring density, the types of the wires generally include signal wires, power wires, ground wires and the like, and in an embodiment, the types of the wires further include wire widths. Specifically, the pitch between the traces is determined based on the trace width in generating the predicted trace status report also taking into account the trace width. The empirical defect size distribution refers to the distribution interval and interval duty ratio of the empirical defect size obtained by detecting and analyzing the defect data existing in the conventional molded chip and analyzing and counting.
And S02, carrying out wiring design on the chip based on the generated predicted wiring state report.
The step of adjusting the wiring distance between adjacent wires based on the wiring parameters of the wires in the initial wiring status report comprises the step of adjusting the wiring distance between the adjacent wires in a predetermined area based on the wiring parameters of the wires in the initial wiring status report, wherein the predetermined area is determined based on the wiring density and the empirical defect size, and the predetermined area also refers to an adjustable area of the wiring parameters on the chip. It is understood that the predetermined area refers to an area where a failure phenomenon is liable to occur, that is, a wiring crowded area. In this embodiment, the wiring pitch between adjacent wires in the wiring congestion area is adjusted, so that the probability of failure between adjacent wires in the congestion area can be reduced. According to the wiring parameters of the wirings in the wiring state report, the wiring congestion degree information (namely the wiring density) is determined, the wiring interval between adjacent wirings is adjusted, the probability of defect falling on a signal line can be well reduced, the functional failure problem caused by chip signals, power short circuits or open circuits is reduced, the probability of chip failure caused by defect falling on the chip wirings or between the wirings is reduced mainly through a method of rear-end physical implementation, and the yield of chips is improved.
In the chip, there is also an unadjustable area, in which the wiring density is very high and there is no space for wiring adjustment, and this area is set as an unadjustable area. Specifically, the area where the wiring density is equal to or higher than the first density is a non-predetermined area, i.e., an unadjustable area, because the wiring is too dense without an adjustment space, and the area where the wiring density is lower than the first density is an adjustable area. The first density is generally 90%, although other density values may be used according to actual needs. The adjustment of the wiring pitch and the wiring width according to the present application is based on the area with the margin, and has an adjustment space.
In an embodiment, when the wiring spacing between adjacent wires is adjusted, the wiring spacing between associated wires can be enlarged and/or the wiring spacing between non-associated wires can be reduced, the associated wires comprise power wires and/or signal wires which are mutually affected after being conducted, and the non-associated wires comprise power wires and/or signal wires which are not mutually affected after being conducted. As shown in fig. 6, the left schematic diagram in fig. 6 shows a wiring schematic diagram of the power supply line VDD and the ground line VSS, wherein the distance between the power supply line VDD and the ground line VSS is small, and when dust (black part) falls in between the power supply line VDD and the ground line VSS, a short circuit is caused. To solve this problem, the pitch between the associated power supply lines VDD and ground lines VSS is increased, and the pitch between the non-associated power supply lines VDD and ground lines VSS is reduced while the pitch between the associated power supply lines VDD and ground lines VSS is increased in order not to affect the area of the chip, and in fig. 6, a and c are both power supply lines VDD and bd are both ground lines VSS, wherein a and b and c and d are both associated power supply lines VDD and ground lines VSS, and b and c are both non-associated power supply lines VDD and ground lines VSS.
And generating an adaptive wiring interval adjustment rule according to the wiring density, the wiring type and the corresponding empirical defect size distribution of the preset area, wherein the adjustment rule is that the wiring interval becomes larger, the probability of defects falling in gaps among wirings is increased, or the probability of defects not completely covering the wirings is increased.
The specific regulation rule is that the wiring pitch is larger than the maximum end value of the interval with the largest proportion in the empirical defect size distribution interval. For example, if the empirical defect sizes are too much distributed, the most occupied section of the empirical defect size distribution section is the size section corresponding to the protruding section of the normal distribution, and the maximum value of the section is taken to ensure that most defects will not cause chip failure. Defects can fall between lines and also on a single line. If the interval between the wires is larger than the maximum value of the interval, the probability that the defect falls in the gap between the wires can be increased, and the yield of the chip is further improved. The width of the wire is increased, and even if the defect falls on the wire, the basic performance of the wire can be ensured because the size of the defect is smaller than the width of the wire. When the wiring pitch is larger than the maximum end value of the interval with the largest proportion among the empirical defect size distribution intervals, the two connected wires are not short-circuited even if dust falls between the two wires.
And adjusting the wiring spacing in the area according to the generated adjustment rule:
Specifically, the layout and wiring tool expands the intervals of the wirings in the corresponding region according to the generated adjustment rule, and reduces the overall unit wiring density. In the production process, the probability of short circuit or open circuit of a signal line caused by defect occurrence on a wafer is greatly reduced, so that the probability of functional failure of a chip caused by defect occurrence is reduced as a whole.
Specifically, the adjusting of the wiring spacing between adjacent wires in the preset area comprises determining the wiring spacing between adjacent wires in the preset area based on the total area of the preset area, the wiring density of the preset area, the wiring degree of the preset area and the wiring quantity of the preset area. In one embodiment, the total area of the adjustable region is defined as S, the area wiring density is k, the wiring length is l, the original wiring pitch is d, and the adjustment rule is that the adjusted wiring pitch d=s (1-k)/(n-1) ×l. Where n is the number of wires in the area.
Specifically, in order to generate an adjustment rule in a targeted manner, wiring adjustment is facilitated, the failure probability of a chip is improved, the method further comprises the steps of dividing an adjustable area into a first preset area, dividing the wiring density into a second preset area with a second density which is smaller than the first density, dividing the wiring density into a second preset area with a wiring density which is smaller than or equal to the second density, namely, the wiring density of the first preset area is larger than the wiring density of the second area, adjusting the wiring spacing of adjacent wires in the first preset area based on the wiring density, the wiring type and the corresponding empirical defect size distribution of the first preset area, and adjusting the wiring spacing of adjacent wires in the second preset area based on the wiring density, the wiring type and the corresponding empirical defect size distribution of the second preset area. Preferably, the first density is 90% and the second density is 50%. In the second region, i.e., the wiring density is 50% or less, it is indicated that the region has a void area of half or more of the total area of the region, and the regulation rule for the region is that the wiring pitch is enlarged by 1.5-2 times or the wiring width is enlarged by 1.5-2 times.
In embodiment 1, the whole chip is divided into a plurality of areas (regions) according to the information of the wiring Congestion degree (wiring density) in the chip layout wiring stage, and the wiring intervals (Pitch) in the areas with different wiring densities are respectively adjusted according to the wiring Congestion degree (Congestion) state of each area, so that the wiring intervals of the areas with smaller wiring densities on the chip are increased, the average wiring intervals of all chip signal lines (including digital signals, analog signal lines and the like) on the chip are increased, the probability that defects fall in gaps between wirings is increased, and the probability that defects fall on the signal lines is reduced.
As shown in fig. 3, for the signal lines with narrower width, the wiring information of the whole chip is divided into different areas according to the information of the wiring crowding degree (Congestin) in the chip layout and wiring stage, such as two areas respectively represented by green and blue areas in the figure, wherein green is a non-crowding area of the wiring, and blue is a relatively crowding area of the wiring.
For two areas, different wiring rules (Non-default Routing Rule) are generated, so that local wiring adjustment is performed, different wiring intervals are respectively set for signal lines in different areas, for example, the green area is adjusted by using the largest wiring interval, the comparison chart before and after adjustment is shown in fig. 4, the blue area is adjusted by using a larger wiring interval, and the comparison chart before and after adjustment is shown in fig. 5.
And the wiring of the blue and green areas is set to be restricted by a wiring rule, the interval of the wirings in the areas is enlarged by a layout wiring tool according to the set rule, so that the overall unit wiring density is reduced, and if defects are generated on wafers in the production process, the probability of signal line short circuit or open circuit is greatly reduced, so that the functional failure probability of chips caused by the defects is reduced as a whole.
After the adjustment, when the defect occurs in the blue and green areas, the probability of falling on the signal line is reduced due to the increased wiring interval pitch, so that the functional failure probability of the whole chip caused by the defect is reduced.
Example 2 for a Power Mesh wire (Power Mesh) with a larger width, the short and open circuit caused by the defect is more fatal. For layout implementation, chip failure caused by defect needs to be considered from layout planning. Because the power lines are arranged in pairs, when power network planning is performed, the probability that the defect falls between the power lines can be effectively reduced by increasing the relative distance (Spacing) between the power lines, and the failure risk is reduced.
In the traditional power/ground wire wiring method, in order to reduce the coupling capacitance between the power and the ground, the minimum distance is adopted between the power wires and the ground wires so as to ensure the strength of a power network. However, if the defect falls between the power line and the ground line, the short circuit of the power supply network is very easy to be caused, the local power supply current is increased, and the transistor is burnt out, so that the chip is invalid.
According to the empirical defect size distribution and wiring density provided by a factory, the spacing between the power supply and the ground wires is formulated, so that the spacing between the power supply and the ground wires is properly increased while the design requirement is met, the probability that the defect falls between the power supply and the ground wires can be effectively reduced, and the short circuit problem is prevented. As shown in fig. 6, the effects before and after adjustment are schematically shown. By adopting the method, the wiring spacing between the power supply and the ground wire is properly increased, even if a defect occurs in the production process, the probability that the defect falls between the power supply and the ground wire is reduced, the chip failure caused by the short circuit of the power supply network is prevented, and the yield of the chip can be effectively improved.
The invention also provides a chip wiring device, in particular as shown in FIG. 7, which comprises a predicted wiring state report generating module 1 and a wiring design module 2;
The predicted wiring state report generation module 1 is used for acquiring wiring parameters of wires in the initial wiring report, adjusting the wiring spacing between adjacent wires and generating a predicted wiring state report, wherein the wiring parameters comprise at least one of wiring density, wiring type and corresponding empirical defect size distribution;
and the wiring design module 2 is used for carrying out wiring design on the chip based on the predicted wiring state report.
Referring to fig. 8, the electronic device of the present invention includes a processor and a memory coupled to each other, wherein the memory is used for storing program instructions for implementing the chip wiring method described above, and the processor is used for executing the program instructions stored in the memory.
Referring to fig. 9, a computer-readable storage medium of the present invention has stored thereon a program file, which is executed to implement the above-described chip wiring method.
Claims (8)
1. A chip wiring method, comprising the steps of:
Adjusting wiring intervals between adjacent wires based on wiring parameters of the wires in the initial wiring state report to generate a predicted wiring state report, wherein the wiring parameters comprise at least one of wiring density, wiring type and corresponding empirical defect size distribution;
The method comprises the steps of dividing a preset area into a first preset area and a second preset area based on the wiring density, wherein the wiring density of the first preset area is larger than that of the second preset area, adjusting the wiring spacing of the adjacent wires in the first preset area based on the wiring density, the wiring type and the corresponding empirical defect size distribution of the first preset area, and adjusting the wiring spacing of the adjacent wires in the second preset area based on the wiring density, the wiring type and the corresponding empirical defect size distribution of the second preset area;
and carrying out wiring design on the chip based on the predicted wiring state report.
2. The chip wiring method according to claim 1, wherein,
The adjusting of the wiring pitch between adjacent wires includes expanding the wiring pitch between associated wires and/or shrinking the wiring pitch between non-associated wires,
The related wirings comprise wirings which are mutually affected after being conducted;
the non-associated wirings include wirings which do not affect each other after being conducted.
3. The chip wiring method according to claim 1, wherein the adjacent wirings are two adjacent signal lines, and the wiring pitch of the two adjacent signal lines is enlarged by 1.5 times to 2 times.
4. The chip wiring method according to claim 1 or 3, wherein the adjacent wirings are adjacent power lines and ground lines, and a distance between the power lines and the ground lines is adjusted to be larger than a maximum end value of a section with the largest ratio among the empirical defect size distribution sections.
5. The chip wiring method according to claim 1, wherein adjusting a wiring pitch between adjacent wirings in a predetermined region comprises:
The wiring pitch between adjacent wirings in the predetermined area is determined based on the total area of the predetermined area, the wiring density of the predetermined area, the wiring degree of the predetermined area, and the number of wirings of the predetermined area.
6. A chip wiring device, comprising:
The predicted wiring state report generation module (1) is used for acquiring wiring parameters of wires in the initial wiring report, and adjusting the wiring spacing between adjacent wires to generate a predicted wiring state report, wherein the wiring parameters comprise at least one of wiring density, wiring type and corresponding empirical defect size distribution;
The method comprises the steps of dividing a preset area into a first preset area and a second preset area based on the wiring density, wherein the wiring density of the first preset area is larger than that of the second preset area, adjusting the wiring spacing of the adjacent wires in the first preset area based on the wiring density, the wiring type and the corresponding empirical defect size distribution of the first preset area, and adjusting the wiring spacing of the adjacent wires in the second preset area based on the wiring density, the wiring type and the corresponding empirical defect size distribution of the second preset area;
And a wiring design module (2) for performing wiring design on the chip based on the predicted wiring status report.
7. An electronic device comprising a processor and a memory coupled to each other, wherein,
The memory is used for storing program instructions for realizing the chip wiring method according to any one of claims 1-5;
the processor is used for executing the program instructions stored in the memory.
8. A computer-readable storage medium, characterized in that a program file is stored, which is executed to implement the chip wiring method according to any one of claims 1 to 5.
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Country or region after: China Address after: 710075 4th floor, block a, No.38, Gaoxin 6th Road, high tech Zone, Xi'an City, Shaanxi Province Applicant after: Xi'an Ziguang Guoxin Semiconductor Co.,Ltd. Address before: 710075 4th floor, block a, No.38, Gaoxin 6th Road, high tech Zone, Xi'an City, Shaanxi Province Applicant before: XI''AN UNIIC SEMICONDUCTORS Co.,Ltd. Country or region before: China |
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