CN114513191A - Correction device and method - Google Patents

Abstract

A correction device comprises a signal generator and a processor. The signal generator is used for providing an input signal to a filter circuit, wherein the filter circuit has an actual time constant and is used for receiving the input signal to output an output signal. The processor is used for calculating an actual gain according to the output signal and the input signal, comparing the actual gain with a target gain to obtain a comparison result, and judging whether to adjust the actual time constant of the filter circuit according to the comparison result. The invention also provides a correction method.

Description

Correction device and method

technical field

The present application relates to a calibration device and method, and particularly to a calibration device and method suitable for filter circuits.

Background technique

Generally speaking, filters are an integral part of wireless communication systems. However, the frequency response of the filter is very likely to deviate from the original design setting due to process changes, thereby affecting the quality of signal demodulation.

To solve the above-mentioned problems, a correction circuit is conventionally additionally provided, the correction circuit having the same time constant as the filter circuit to be corrected. By adjusting the capacitance value of the capacitor in the correction circuit, the time constant of the correction circuit can reach the target value. Finally, the capacitance setting corresponding to the target value is provided to the filter circuit to complete the correction. However, the above method can only compensate for the variation of capacitance or resistance caused by process variation, and cannot further compensate for variation of other components (eg, operational amplifier) due to variation of manufacturing process. Therefore, it is necessary to improve the traditional correction method.

SUMMARY OF THE INVENTION

One aspect of the present application provides a correction device. The correction device includes a signal generator and a processor. The signal generator is used for providing an input signal to a filter circuit, wherein the filter circuit has a real time constant and is used for receiving the input signal to output an output signal. The processor is used for calculating the actual gain according to the output signal and the input signal, comparing the actual gain and the target gain to obtain a comparison result, and judging whether to adjust the actual time of the filter circuit according to the comparison result constant. The present application also provides a calibration method.

Another aspect of the present application provides a calibration method. The correction method includes: providing an input signal to a filter circuit, wherein the filter circuit has an actual time constant; receiving an output signal from the filter circuit; calculating an actual gain according to the output signal and the input signal; gain and target gain to obtain a comparison result; and determine whether to adjust the actual time constant of the filter circuit according to the comparison result.

To sum up, the calibration device and calibration method of the present invention can adjust the filter circuit by directly comparing the actual gain and the target gain of the filter circuit to compensate for various components in the filter circuit (such as resistors, capacitors or op amps) due to process variations. In this way, the filter circuit can be corrected back to the originally designed setting value to facilitate signal demodulation.

Description of drawings

FIG. 1 is a block diagram illustrating a calibration apparatus according to some embodiments of the present application.

2A is a schematic diagram illustrating a frequency response of a filter circuit affected by process variation according to some embodiments of the present application.

2B is a schematic diagram illustrating a corrected frequency response of a filter circuit affected by process variations according to some embodiments of the present application.

3 is a schematic diagram illustrating the frequency response of another filter circuit affected by process variation according to some embodiments of the present application.

FIG. 4 is a circuit diagram illustrating a filter circuit according to some embodiments of the present application.

FIG. 5 is a flowchart illustrating a calibration method according to some embodiments of the present application.

Symbol Description

10: Filter circuit

100: Correction device

102: Signal generator

104: Processor

VIN: input signal

VOUT: output signal

gmr: actual gain

gm0: target gain

f ₁ : actual center frequency

f ₀ : default center frequency

A: Amplifier

R: resistance

C: Capacitor

I _in+ : the first input signal

I _in- : the second input signal

Q _in+ : the third input signal

Q _in- : the fourth input signal

I _out+ : the first output signal

I _out- : the second output signal

Q _out+ : the third output signal

Q _out- : Fourth output signal

S210, S220, S230, S240, S250, S260: Steps

Detailed ways

The following is a detailed description with examples and accompanying drawings, but the described specific embodiments are only used to explain the present invention, not to limit the present invention, and the description of structural operations is not used to limit the order of its execution, any recombination of components The structure of the present invention and the resulting device with equal efficacy are all within the scope of the present application.

The terms used in the present disclosure and the claims, unless otherwise specified, generally have the common meaning of each term in the field, as well as the common meaning in the disclosed content and the specific content.

In addition, "coupled" or "connected" as used herein may refer to two or more components in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or may refer to Two or more components operate or act upon each other.

Referring to FIG. 1 , one embodiment of the present application relates to a calibration device 100 . The calibration device 100 includes a signal generator 102 and a processor 104, and is used for calibrating the filter circuit 10 affected by process variations.

In this embodiment, the filter circuit 10 can be a band-pass filter, and is designed to have a default center frequency f ₀ and a predetermined time constant τ ₀ corresponding to the default center frequency f ₀ . However, under the influence of process variation, the time constant of the filter circuit 10 is different from the originally designed value, and the bandwidth and center frequency of the filter circuit 10 are also different from the originally designed value. For example, the filter circuit 10 affected by the process variation has an actual time constant τ ₁ different from the preset time constant τ ₀ and an actual center frequency f ₁ different from the default center frequency f ₀ .

Structurally, the signal generator 102 is coupled to the filter circuit 10 , and the processor 104 is coupled to the signal generator 102 and the filter circuit 10 . In this embodiment, the signal generator 102 may include a crystal oscillator (not shown in the figure) and a low-pass filter (not shown in the figure), and the processor 104 may be a central processing unit or a calculator chip.

For a better understanding of the present invention, the operation of the correction device 100 will be discussed in the following paragraphs in conjunction with the accompanying drawings. As shown in FIG. 1 , the signal generator 102 provides an input signal V _IN to the filter circuit 10 according to an instruction (not shown) from the processor 104 , wherein the frequency of the input signal V _IN is equal to the original frequency of the filter circuit 10 . The default center frequency f ₀ of the design.

The filter circuit 10 receives the input signal V _IN to output the output signal V _OUT to the processor 104 . The processor 104 receives the output signal V _OUT and calculates the actual gain gm _r according to the output signal V _OUT and the input signal V _IN . Specifically, the processor 104 divides the output signal V _OUT by the input signal V _IN to generate a ratio, and uses the absolute value of the ratio as the actual gain gm _r .

In this embodiment, the filter circuit 10 has a target gain gm _{0 at the originally designed default center frequency f 0 .} It can be understood that the target gain gm ₀ is the maximum gain value that the filter circuit 10 should have at the originally designed default center frequency f ₀ . As an example of practical application, the filter circuit 10 is designed to have a gain value of 1.5 (ie, the target gain gm ₀ ) at 300 MHz (ie, the default center frequency f ₀ ). That is, when the frequency of the input signal V _IN is 300 MHz, the output signal V _OUT should ideally be 1.5 times stronger than the input signal V _IN at 300 MHz.

However, the filter circuit 10 subject to process variation has an actual center frequency f ₁ that is different from the default center frequency f ₀ . That is, the maximum gain value change of the filter circuit ₁₀ occurs at the actual center frequency f1. At this time, if the input signal V _IN with the default center frequency f ₀ is input to the filter circuit 10 , the actual gain gm _r calculated by the processor 104 will not be the originally designed maximum gain value of the filter circuit 10 . Taking the above practical application example, the strength of the output signal V _OUT at 300MHz will be less than 1.5 times that of the input signal V _IN , in other words, the actual gain gm _r is less than 1.5 (ie, the target gain gm ₀ ).

After the actual gain gm _r is calculated, the processor 104 can compare the actual gain gm _r with the target gain gm ₀ to obtain a comparison result. Ideally, the processor 104 obtains a result that the actual gain gm _r at the default center frequency f ₀ is equal to the target gain gm ₀ by comparing the actual gain gm _r with the target gain gm ₀ . However, if the filter circuit 10 is affected by process variations, the processor 104 will obtain the result that the actual gain gm _r at the default center frequency f ₀ is not equal to the target gain gm ₀ by comparing the actual gain gm _r with the target gain gm ₀ .

Accordingly, the processor 104 can further determine whether to adjust the time constant of the filter circuit 10 according to the comparison result, so as to correct the frequency response of the filter circuit 10 to the originally designed value.

Specifically, referring to FIG. 2A , in this embodiment, the frequency response of the filter circuit 10 (indicated by the dotted line) is affected by process variation, so that the actual center frequency f ₁ is smaller than the default center frequency f ₀ . As shown in FIG. 2A , the processor 104 compares the actual gain gm _r with the target gain gm ₀ , and obtains a result that the actual gain gm _r is smaller than the target gain gm ₀ . Taking the above practical application example as an example, the actual center frequency f ₁ may be 100 MHz which is less than 300 MHz, and the actual gain gm _r may be 0.75 which is less than 1.5. When the actual gain gm _r is less than the target gain gm ₀ , the processor 104 can be used to adjust the capacitance value of at least one capacitor (not shown in the figure) in the filter circuit 10 (or at least one resistor (not shown in the figure) in the filter circuit 10 ) to adjust the actual time constant τ ₁ of the filter circuit 10 , thereby changing the actual center frequency f ₁ and the actual gain gm _r of the filter circuit 10 .

After several comparisons and adjustments, the actual gain gm _r will be closer and closer to the target gain gm ₀ . For example, the processor 104 may digitally adjust the capacitance value of the at least one capacitor from 64 farads to 32 farads, 16 farads, 8 farads, and 4 farads in sequence. As the capacitance value of the at least one capacitor gradually decreases, the actual center frequency f ₁ and the actual gain gm _r of the filter circuit 10 also gradually increases. Taking the above practical application example, as the capacitance value of the at least one capacitor gradually decreases, the actual center frequency f ₁ can be gradually increased from 100MHz to 300MHz, and the actual gain gm _r at the default center frequency f ₀ can be from 0.75 gradually increased to 1.5.

Next, referring to FIG. 2B , when the processor 104 compares the actual gain gm _r with the target gain gm ₀ and obtains the result that the actual gain gm _r is equal to the target gain gm ₀ , the processor 104 no longer adjusts the filter circuit 10 The actual time constant τ ₁ . At this time, the corrected actual time constant τ ₁ and the actual center frequency f ₁ of the filter circuit 10 are exactly equal to the preset time constant τ ₀ and the default center frequency f ₀ in the original design. Taking the above practical application example as an example, after the filter circuit 10 is calibrated, the actual center frequency f ₁ may be 300 MHz, and the actual gain gm _r at the default center frequency f ₀ may be 1.5. It is worth noting that the capacitance value of the at least one capacitor is the set value required by the filter circuit 10 affected by process variations.

Referring to FIG. 3 , in other embodiments, the frequency response of the filter circuit 10 (indicated by a dotted line) is affected by process variations, so that the actual center frequency f ₁ is greater than the default center frequency f ₀ . At this time, the processor 104 compares the actual gain gm _r with the target gain gm ₀ , and still obtains the result that the actual gain gm _r is smaller than the target gain gm ₀ . Taking the above practical application example as an example, the actual center frequency f ₁ may be 500 MHz which is greater than 300 MHz, and the actual gain gm _r may be 0.75 which is less than 1.5. Similarly, the processor 104 can digitally increase the capacitance value of the at least one capacitor gradually (for example, from 4 Farads to 8 Farads, 16 Farads, 32 Farads, and 64 Farads in sequence), so that the filter The actual center frequency f ₁ of the circuit 10 gradually becomes smaller, and the actual gain gm _r of the filter circuit 10 gradually becomes larger. Taking the above practical application example, as the capacitance value of the at least one capacitor increases gradually, the actual center frequency f ₁ can be gradually reduced from 500MHz to 300MHz, and the actual gain gm _r at the default center frequency f ₀ can be from 0.75 gradually increased to 1.5. Next, when the processor 104 obtains the result that the actual gain gm _r is equal to the target gain gm ₀ (as shown in FIG. 2B ), the processor 104 no longer adjusts the actual time constant τ ₁ of the filter circuit 10 . At this time, the capacitance value of the at least one capacitor is the set value required by the filter circuit 10 affected by the process variation.

In some other embodiments, the processor 104 may adjust the capacitance value of the at least one capacitor through a digital algorithm (eg, a two-bit search algorithm).

Referring to FIG. 4 , in other embodiments, the filter circuit 10 may be a complex bandpass filter including a plurality of amplifiers A, a plurality of resistors R and a plurality of capacitors C. For the filter circuit 10 shown in FIG. 4 , the input signal V _IN generated by the signal generator 102 includes a first differential input signal (including the first input signal I _in ⁺ and the second input signal I _in ⁻ ) and the first differential input signal Two differential input signals (including the third input signal Q _in ⁺ and the fourth input signal Q _in ⁻ ), wherein the phase of the first differential input signal and the phase of the second differential input signal are different by 90 degrees. In addition, the output signal V _OUT output by the filter circuit 10 includes the first differential output signal (including the first output signal I _out ⁺ and the second output signal I _out ⁻ ) and the second differential output signal (including the third output signal) Q _out ⁺ and the fourth output signal Q _out ⁻ ). The description of the calibration device 100 for calibrating the filter circuit 10 shown in FIG. 4 is similar to the above-mentioned embodiment, so it is not repeated here.

Please refer to FIG. 5 , which is a flowchart of a calibration method 200 according to one embodiment of the present application. The calibration method 200 may be performed on the calibration device 100 as shown in FIG. 1 .

In step S210, the input signal V _IN is provided to the filter circuit 10 affected by the process, wherein the filter circuit 10 has an actual time constant τ ₁ . In step S220, the output signal V _OUT from the filter circuit 10 is received. In step S230, the actual gain gm _r is calculated according to the input signal V _IN and the output signal V _OUT .

In steps S240-S260, the actual gain gm _r is compared with the target gain gm ₀ (that is, the maximum gain value of the filter circuit 10 at the originally designed default center frequency f ₀ ) to obtain the comparison result, and according to the The comparison results determine whether the actual time constant τ ₁ of the filter circuit 10 should be adjusted. Specifically, in step S240, it is compared whether the actual gain gm _r is equal to the target gain gm ₀ . If the comparison result shows "No", then go to step S250 to adjust the actual time constant τ ₁ of the filter circuit 10 .

After adjusting the actual time constant τ ₁ of the filter circuit 10 , the procedure returns to step S210 to provide the input signal V _IN to the adjusted filter circuit 10 to execute steps S220 - S240 again. In short, as long as it is obtained in step S240 that the actual gain gm _r is not equal to the target gain gm ₀ , the process proceeds to step S250 to adjust the actual time constant τ ₁ of the filter circuit 10 , and steps S210 to S240 are performed again.

If the comparison result in step S240 shows "Yes", then go to step S260, do not adjust the actual time constant τ ₁ of the filter circuit 10 (the actual time constant τ ₁ at this time is equal to the default time originally designed by the filter circuit 10 ) constant τ ₀ ), and the calibration method 200 ends.

To sum up, the correction device 100 and the correction method 200 of the present invention adjust the filter circuit 10 by directly comparing the actual gain gm _r of the filter circuit 10 with the target gain gm ₀ to compensate for each of the filter circuits 10 . Variations due to process variations in components such as resistors, capacitors, or op amps. In this way, the filter circuit 10 can be corrected back to the originally designed setting values (ie, the default center frequency f ₀ , the default time constant τ ₀ and the target gain gm ₀ ) to facilitate signal demodulation.

Although the application content of the present invention has been disclosed above through specific embodiments, the multiple embodiments are not intended to limit the application content of the present invention. Those of ordinary skill in the art can apply for the application according to the present invention without departing from the concept and scope of the application content of the present invention. Modifications or adjustments to the technical solutions of the present application, all such changes may belong to the scope of patent protection sought by the present application. The defined range shall prevail.

Claims (10)

1. A calibration device, characterized in that the calibration device comprises:

a signal generator for providing an input signal to a filter circuit, wherein the filter circuit has an actual time constant and is configured to receive the input signal to output an output signal; and

and the processor is used for calculating actual gain according to the output signal and the input signal, comparing the actual gain with a target gain to obtain a comparison result, and judging whether to adjust the actual time constant of the filter circuit according to the comparison result.

2. The calibration apparatus of claim 1, wherein the processor adjusts the actual time constant of the filter circuit to adjust the actual gain when the comparison shows that the actual gain is not equal to the target gain.

3. The correction device of claim 2, wherein the processor adjusts the capacitance value of at least one capacitor in the filter circuit or the resistance value of at least one resistor in the filter circuit by a digital algorithm to adjust the actual time constant of the filter circuit.

4. The calibration apparatus of claim 1, wherein the processor does not adjust the actual time constant of the filter circuit when the comparison result indicates that the actual gain is equal to the target gain.

5. The correction apparatus as claimed in claim 4, wherein said filter circuit is designed to have a preset time constant and a default center frequency, and to have said target gain at said default center frequency;

when the comparison result shows that the actual gain is equal to the target gain, the actual time constant of the filter circuit is equal to the preset time constant, and the frequency of the input signal is equal to the default center frequency of the filter circuit.

6. A correction method, characterized in that the correction method comprises:

providing an input signal to a filter circuit, wherein the filter circuit has an actual time constant;

receiving an output signal from the filter circuit;

calculating an actual gain according to the output signal and the input signal;

comparing the actual gain with the target gain to obtain a comparison result; and

and judging whether to adjust the actual time constant of the filter circuit according to the comparison result.

7. The calibration method of claim 6, wherein determining whether to adjust the actual time constant of the filter circuit according to the comparison comprises:

and when the comparison result shows that the actual gain is not equal to the target gain, adjusting the actual time constant of the filter circuit to adjust the actual gain.

8. The correction method of claim 7, wherein adjusting the actual time constant of the filter circuit comprises:

adjusting a capacitance value of at least one capacitor in the filter circuit or a resistance value of at least one resistor in the filter circuit by a digital algorithm.

9. The calibration method of claim 6, wherein determining whether to adjust the actual time constant of the filter circuit according to the comparison comprises:

and when the comparison result shows that the actual gain is equal to the target gain, not adjusting the actual time constant of the filter circuit.

10. The correction method of claim 9, wherein the filter circuit is designed to have a preset time constant and a default center frequency, and to have the target gain at the default center frequency;

when the comparison result shows that the actual gain is equal to the target gain, the actual time constant of the filter circuit is equal to the preset time constant, and the frequency of the input signal is equal to the default center frequency of the filter circuit.

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