CN114556315A - Efficient placement of memory - Google Patents

Abstract

An electronic device, comprising: a circuit board; a memory chip mounted on the circuit board; a memory controller for controlling the operation of the memory chip; a conductive pattern, comprising: a first control line for connecting a first terminal of the memory chip A first terminal connected to the memory chip, and a second control line for connecting from a second terminal of the memory controller to a second terminal of the memory chip, and a capacitive element for supplying a terminal voltage. The first control line is connected to the capacitive element, and the second control line is not connected to the capacitive element.

Description

Efficient placement of memory

Background technique

An electronic device with memory for driving an operating system is provided. The memory and controller are connected by wiring on the circuit board. In recent years, even when components previously arranged on a circuit board are removed, there is a need to secure additional space for wiring efficiency by removing components that do not affect the performance of electronic equipment.

Description of drawings

FIG. 1 is a block diagram illustrating an image forming apparatus according to an example;

FIG. 2 is a diagram illustrating an example of the print engine of FIG. 1;

3 is a diagram illustrating a configuration of an electronic device according to an example;

4 is a diagram illustrating an example of a circuit board of an electronic device;

5 is a diagram illustrating a connection form of control lines according to an example;

6 is a diagram illustrating a connection form of control lines according to an example;

FIG. 7 is an eye diagram for a case where the terminal voltage is not supplied by being spaced apart by more than a predetermined length, and

FIG. 8 is an eye diagram for the case where the arrangement is below a predetermined length and the terminal voltage is not supplied.

Detailed ways

Examples will be described with reference to the accompanying drawings. The examples described below can be modified and implemented in various different forms.

The terms "connected to" or "coupled to" used to indicate the connection or coupling of one element to another element includes instances where an element is "directly connected or coupled to" another element and an element is connected via another element or coupled to another element. Further, it should be understood that the term "comprising" means that other constituent elements may be further included rather than excluded unless otherwise specified.

In this specification, the term "image forming job" may refer to various image-related jobs (eg, printing, scanning, or facsimile) such as forming an image or generating an image file, storing the image file, and transmitting the image file. In addition, the term "job" may refer to an image forming job, and may also include a series of processes for executing the image forming job.

In addition, "electronic equipment" may be a device having a volatile memory, and may be a personal computer (PC), a notebook computer, a tablet PC, a smart phone, an image forming apparatus, a scanner, or the like.

Further, the term "image forming apparatus" may refer to a device that prints print data generated from a terminal device such as a computer on recording paper. Examples of such image forming apparatuses may include copying apparatuses, printers, facsimile machines, and multifunction peripherals (MFPs) having multiple functions of the above apparatuses in one unit.

Further, the term "print data" may refer to data that is converted into a printable format in a printer.

FIG. 1 is a block diagram illustrating an image forming apparatus according to an example.

1 , the electronic device 100 may include a communication device 110 , a display 120 , a manipulation input device 130 , a memory 140 , a print engine 150 and a processor 160 .

The communication device 110 may be formed to connect the electronic device 100 to external devices, and may communicate via a local area network (LAN) and the Internet as well as via a universal serial bus (USB) port or wireless communication (eg, Wi-Fi 802.11a/b/g /n, NFC, Bluetooth) port is connected to the user terminal device.

The communication device 110 may be connected to a user terminal device (not shown) and may receive print data from the user terminal device (not shown).

The display 120 may display various information provided by the electronic device 100 or may display a control menu for performing functions of the electronic device 100 . For example, the display 120 may display a user interface window for selecting various functions provided in the electronic device 100 . The display 120 may be a monitor such as a liquid crystal display (LCD), a cathode ray tube (CRT), or an organic light emitting diode (OLED), and may be implemented as a touch screen capable of simultaneously performing the function of manipulating the input device 130 .

The manipulation input device 130 may receive an input of a user's function selection and a control command for the corresponding function. Functions can include printing, copying, scanning, and fax transmission. The manipulation input device 130 as described above may be input through the control menu displayed on the display 120 .

The manipulation input device 130 may be implemented by a plurality of buttons, a keyboard and a mouse, and may also be implemented by a touch screen capable of simultaneously performing the functions of the display 120 .

At least one instruction related to the electronic device 100 may be stored in the memory 140 . For example, various programs (or software or machine-readable instructions) for operating the electronic device 100 may be stored in the memory 140 according to various examples of the present disclosure.

In addition, the memory 140 may store the received print data. Memory 140 may include volatile or nonvolatile memory. The nonvolatile memory can store programs as described above. The nonvolatile memory may be implemented as various storage devices such as a hard disk drive (HDD) or a solid state drive (SSD).

The volatile memory can be operated by loading a program stored in the nonvolatile memory when the processor 160 to be described later is operated. In the printing process of the print data, the volatile memory may temporarily store the received print data, or store the parsed data and binary data of the corresponding print data, and the like. The volatile memory configuration of the memory 140 will be described later with reference to FIG. 3 .

The print engine 150 may print the print data. The print engine 150 may form an image on a recording medium by various printing methods such as an electrophotographic method, an inkjet method, a thermal transfer method, or a thermal method. For example, the print engine 150 may print an image on a recording medium through a series of processes including exposure, development, transfer, and fixing. An example configuration of the print engine 150 will be described later with reference to FIG. 2 .

The processor 160 may control each component of the electronic device 100 . For example, the processor 160 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), a ROM, or the like, and may be executed based on a program stored in the ROM for loading an operating system stored in a nonvolatile memory into the A boot operation in the volatile memory, and various services provided by the electronic device 100 may be performed after the boot operation.

In addition, when the print data is received from the outside, the processor 160 may control the print engine 150 to perform printing on the received print data by performing operations such as parsing.

In FIG. 1, although electronic device 100 is depicted as including a print engine, other components may also be included. For example, the electronic device 100 may alternatively or additionally include a scanning unit for performing a scanning function or a fax transceiver for performing a fax transmission and/or reception function, or the like, according to functions supported by the electronic device 100 . In addition, when the electronic device 100 is implemented as a general-purpose PC, a smartphone, a tablet, or the like, the configuration of the above-described print engine 150 may be omitted.

FIG. 2 is a diagram illustrating an example of the print engine of FIG. 1 .

2 , the print engine 150 may include a photosensitive member 151 , a charger 152 , an exposure device 153 , a developer 154 , a transfer device 155 , and a fixer 158 .

The print engine 150 may further include a paper feeding device (not shown) for feeding the recording medium P (eg, paper). picture. An electrostatic latent image is formed on the photosensitive member 151 . The photosensitive member 151 may be called a photosensitive drum, a photosensitive belt, or the like depending on its shape.

The charger 152 can charge the surface of the photosensitive member 151 to a uniform potential. The charger 152 may be implemented in the form of a corona charger, a charging roller, or a charging brush, or the like.

The exposure device 153 may form an electrostatic latent image on the surface of the photosensitive member 151 by changing the surface potential of the photosensitive member 151 according to image information to be printed. As an example, the exposure device 153 may receive image information to be printed from a volatile memory, and irradiate the photosensitive member 151 with modulated light according to the received image information to form an electrostatic latent image. This type of exposure device 153 may be referred to as a light syringe or the like, and may use an LED as a light source.

The developer 154 may accommodate a developer therein, and develop the electrostatic latent image into a visible image by supplying the developer onto the electrostatic latent image. The developer 154 may include a developing roller 157 that supplies developer onto the electrostatic latent image. For example, the developer may be supplied from the developing roller 157 onto the electrostatic latent image formed on the photosensitive member 151 by the developing electric field formed between the developing roller 157 and the photosensitive member 151 .

The visible image formed on the photosensitive member 151 is transferred onto the recording medium P by a transfer device 155 or an intermediate transfer belt (not shown). For example, the transfer device 155 may transfer the visible image onto the recording medium by an electrostatic transfer method. The visible image is attached to the recording medium P by electrostatic attraction.

The fuser 158 may apply heat and/or pressure to the visible image on the recording medium P to fix the visible image to the recording medium P. FIG. A print job can be completed through such a series of processing.

The above-described developing device is used every time an image forming job is performed, and therefore, is taken out after being used for more than a predetermined time. In this case, the unit storing the developer (eg, developer 154 ) should be replaced with a new unit. Parts or constituent elements that can be replaced in the process of using the image forming apparatus are referred to as consumable units or replaceable units.

FIG. 3 is a diagram illustrating a configuration of an electronic device according to an example.

For example, FIG. 3 is a diagram illustrating a portion related to a volatile memory among the configuration of the processor of FIG. 1 . Accordingly, the configuration of FIG. 3 can be applied to the memory of FIG. 1 as well as to electronic devices having configurations different from those of the electronic device of FIG. 1 .

3 , the electronic device 200 may include a memory controller 210 , a conductive pattern 220 , a memory chip 230 and a capacitive element 250 .

The memory controller 210 may manage data transmitted to and received from the memory chip 230 . The memory controller 210 may be implemented as a separate IC separate from the CPU, and thus, reads and writes data to and from the memory chips according to the CPU's request, or may be a system-on-chip (SoC) that integrates CPU functions. When the memory controller 210 is an SoC integrated with a CPU function, the memory controller 210 may also perform the functions of the processor 160 described with reference to FIG. 1 .

The memory controller 210 may control the operation of the memory chip 230 (or base memory). For example, the memory controller 210 may be disposed on a circuit board on which the memory chip 230 is disposed, and may generate various signals and control signals for reading data stored in the memory chip 230 or writing data to the memory The chip 230 is transmitted or received through the conductive pattern 220 arranged on the circuit board.

Various signals may refer to command signals such as address group, bank address group, column access strobe (CAS), row address strobe (RAS) or write enable (WE), as well as command signals such as chip select (CS), transistor Control signals such as die (OTT), die termination (ODT), or clock enable (CKE).

In addition, the memory controller 210 may generate a control signal based on the operating frequency of the memory chip 230 and transmit the control signal to a control line. In this case, when the electronic device 200 includes a plurality of memory chips and the operating frequencies of the respective memory chips are different, the control signal may be generated based on the slowest operating frequency.

The conductive pattern 220 may be a conductive pattern for electrically connecting the memory controller 210 and the memory chip 230, and may be arranged on a circuit board. The conductive pattern 220 may include a plurality of control lines that transmit control signals.

Control lines may be arranged between the memory controller 210 and one memory chip 230, and may be sequentially connected to a plurality of memory chips in a flying-connect topology.

In addition, the conductive pattern 220 may further include data transmission/reception lines for transmitting and receiving various signals between the memory controller 210 and the memory chip 230 .

The memory chip 230 (or base memory) may be mounted on the circuit board. For example, the memory chip may be a memory chip supporting DDR3-1320 specification, DDR3-1333 specification, DDR3/4-1600 specification, DDR3/4-1866 specification, DDR3/4-2133 specification, DDR4-2666 specification and DDR4-3200 specification . The above specifications are examples only, and other memory chips supporting other sizes may be used.

Additionally, the electronic device 200 may include multiple memory chips. In this case, a plurality of memory chips may constitute a rank. Additionally, electronic device 200 may include multiple stages. For example, multiple memory chips can be configured as two, four, eight, sixteen, or thirty-two, and can be connected in 32-bit or 64-bit form.

Capacitive element 250 (or shunt capacitor) can improve the impedance characteristics of the control line so that the control signal transmitted through the control line does not invade the eye mask.

To this end, the capacitive element 250 may have a terminal voltage (ie, an intermediate voltage between the maximum voltage and the minimum voltage of the control signal). In this case, the terminal voltage may be used to "pre-charge" the control line (or transmission line) and may be half the magnitude of the drive voltage (Vdd) of the memory chip.

Since the capacitive element has a terminal voltage, the control signal has the effect of being able to quickly transition to a maximum voltage or a minimum voltage. The terminal voltage can be placed on the power plane, which is placed in the outermost layer of the circuit board.

In addition, the capacitive element 250 may be connected to one end of the control line (ie, the opposite terminal to the terminal connected to the memory controller) through a terminating resistor (Rtt). Meanwhile, when a plurality of control lines are included in the conductive pattern, the capacitive elements may be plural.

The capacitive element 250 may be arranged in the outermost layer of the circuit board and may be arranged in an outer area of the circuit board.

In the configuration of DDR3 and DD4 memory connections, each control line is connected to a capacitive element that provides a resistor and termination voltage. For example, since the resistive elements and capacitive elements for supplying the terminal voltage occupy a large area, the removal of the resistor and the terminal voltage may be considered for the efficiency of the wiring.

However, if the resistive and capacitive elements are removed together from the control lines, certain signal qualities may cause malfunction of the electronics due to signal reflection noise.

Therefore, the conditions for selecting the control line from which the resistor and the capacitive element at the end of the control line can be removed will be described below.

For example, in the case where the wiring length between the memory controller and the memory chip is less than a predetermined length, no failure occurs even if the series resistor and the terminal voltage are not provided. The predetermined length may be Equation 1 below.

[Equation 1]

Here, λ is the length of one cycle (eg, a wave corresponding to the operating frequency of the memory chip), C is the speed of light, and F is the operating frequency of the control signal. Meanwhile, when implemented, the risk factor may be managed using a length value reflecting a predetermined ratio (eg, 95%) in Equation 1 above.

In this regard, in the present disclosure, control lines satisfying the above conditions among control lines between the memory controller and the memory chip are not connected to capacitive elements, and control lines not satisfying the following conditions are connected to capacitive elements.

For example, a control line having a wiring length longer than a predetermined length between the memory controller and the first memory chip arranged first may be connected to the capacitive element, and a control line shorter than the predetermined length may not be connected to the capacitive element.

The wiring length refers to the distance between two ports connecting the control lines, and refers to the first memory disposed adjacent to the memory controller when a plurality of memory chips are connected in a fly by topology manner The distance between the port of the chip and the port of the memory controller.

Hereinafter, for convenience of description, when the terminal voltage is connected because the distance between the two ports is greater than or equal to a predetermined length, it is referred to as a first control line, and when the distance between the two ports is less than the predetermined length, it is referred to as a first control line. When the terminal voltage is not connected, it is called the second control line.

For example, the operating frequency of the clock signal is 933.333 MHz, and the predetermined length of the control line for transmitting and receiving the control signal operating at a multiple of the clock signal may be 160.71 mm. Accordingly, if the wiring length between the port where the memory controller transmits and receives the corresponding control signal and the port of the memory chip is 160.71 mm or more, the resistor and the terminal voltage are designed to be connected, and when the wiring length is less than 160.71 mm , the wiring can be designed so that the resistors and terminal voltages are not connected.

Meanwhile, when the plurality of memory chips of the electronic device 200 are connected in a flying-connection topology, the wiring length between the memory controller and the first memory chip arranged first among the plurality of memory chips may be compared with a predetermined length. Accordingly, a control line having a wiring length longer than a predetermined length between the memory controller and the first memory chip arranged first may be the first control line.

In addition, the second control line may be a control line having a wiring length shorter than a predetermined length between the memory controller and the first memory chip arranged first among the plurality of memory chips.

Since the predetermined length is affected by the operating frequency of the control signal, even with the same wiring length, the connection of the capacitive element may or may not be realized, depending on the operating frequency of control signal transmission and reception. This problem will be described later with reference to FIG. 5 .

Meanwhile, in the design process of the memory chip, based on the above-mentioned predetermined length value, wiring design may be performed so that the wiring length of as many control lines as possible is smaller than the predetermined length value corresponding to each control line.

As described above, the electronic device 200 according to the example does not supply the terminal voltage to the control line capable of normal operation even if the terminal voltage is not supplied. In other words, compared with the related art, the resistor and capacitor for supplying the terminal voltage can be omitted while maintaining the same performance, thereby reducing the manufacturing cost and securing additional space.

Meanwhile, in FIG. 3 , the memory chips are all arranged (or mounted) on the circuit board, but in implementation, the socket may be arranged on the circuit board, and the memory module arranged with the memory chip may also be mounted on the socket. form to achieve.

In this case, the above-mentioned first control wire may be connected to one of the plurality of terminals of the socket, and the second control wire may be connected to the other of the plurality of terminals of the socket. In this case, the above-mentioned predetermined length may be the distance between the memory controller and the memory chip on the memory module through the socket.

In addition, some memory chips can be directly mounted on the circuit board, and the remaining memory chips can be implemented in the form of socket connections.

Meanwhile, in FIG. 3, it is described that the terminal voltage is supplied to the control line to maintain the signal quality, and the resistance Rs may be connected to the control line when realized. In other words, it can be implemented in the form of damping resistors connected to the corresponding control lines without providing a terminal voltage for control lines longer than a predetermined length. A damping resistor may be connected in series between the memory controller and the memory chip (eg, the first memory chip).

FIG. 4 is a diagram illustrating an example of a circuit board of an electronic device.

4, the memory controller 210, the plurality of memory chips 230-1 and 230-2, the resistors 260 and the capacitive elements 250 may be arranged on a circuit board (or main board).

The circuit board is a printed circuit board (PCB) on which components such as the memory controller 210, the memory chip 230, and the like are mounted. The circuit board 105 may be a single-sided substrate or a double-sided substrate with conductive layers on both sides. As another example, the circuit board may be a multi-layer board including a power supply layer or a signal layer or the like in the circuit board.

The memory controller 210 , the plurality of memory chips 230 , the resistors 260 and the capacitive elements 250 may be arranged in predetermined areas of the circuit board 105 , respectively. The resistors and capacitive elements may be arranged in the outer area (or edge area) of the circuit board 105 .

Additionally, sockets (not shown) for connection to memory modules may be arranged on the circuit board.

The control lines 220-1 and 220-2 may be sequentially connected to the plurality of memory chips 230-1 and 230-2, respectively, from the output terminal of the memory controller 210. In other words, the control lines can connect multiple memory chips in a flying-connect topology.

For example, the first control line 220-1 may have a distance greater than a predetermined length between the port of the memory controller 210 and the first memory chip 230-1, and thus, one end of the first control line 220-1 may pass through a resistor Rtt260 is connected to the terminal voltage.

However, since the second control line 220-2 has a distance less than a predetermined length between the port of the memory controller 210 and the first memory chip 230-1, one end may be connected to the port of the memory controller 210, and may be sequentially Connected to the port of the first memory chip 230 - 1 and the port of the second memory chip 230 - 2 without being connected to the terminal voltage through the resistor Rtt 260 .

Therefore, some of the plurality of control lines do not need to be connected to the terminal voltages, that is, resistors and capacitive elements for supplying the terminal voltages to the corresponding control lines are not required, thereby reducing the manufacturing cost and ensuring the corresponding Space occupied by resistors and capacitive elements.

FIG. 5 is a diagram illustrating a connection form of control lines according to an example. For example, Figure 5 illustrates an example of a memory chip connected to a memory controller.

Referring to FIG. 5 , each of the memory controller and the memory chip may include a plurality of ports 211 , 212 , 231 and 232 . The conductive pattern may include a plurality of control lines A and B for connecting the above-mentioned plurality of ports. At least one of the plurality of control lines A and B may be a first control line 220-1, and the other may include a second control line 220-2.

For example, the memory controller and the memory chip may supply each of the first control signal and the second control signal having the same operating frequency to the A control line and the B control line having different wiring lengths. In such a case, when the wiring between the ports 211 and 231 of the A control line is longer than the distance according to Equation 1 (A>λ/8), as illustrated in FIG. 5, the A control line may be the first A control line 220-1 in which "resistor Rtt connected to terminal voltage Vtt" is connected to the terminal.

Conversely, when the wiring between the ports 212 and 232 of the B control line is shorter than the distance according to Equation 1 (B<λ/8), as illustrated in FIG. 5, the B control line may be unconnected to the terminal The second control line 220-2.

Meanwhile, as described above, the two control lines have different lengths so as to be the first control line and the second control line, respectively. However, even when the two control lines have the same length, they may become the first control line and the second control line.

For example, when the distance between the A control line and the B control line is 100mm or when the first control signal operates at three times the operating frequency (eg, 933.333Mhz) and the second control signal operates at one time the operating frequency, The predetermined length of the A control wire may be 53.57 mm, and the predetermined length of the B control wire may be 160.71 mm.

In other words, the A control line has a distance longer than a predetermined length (100 mm>53.57 mm), and may be the first control line 220-1 supplied with the terminal voltage. The B control line has a distance shorter than a predetermined length (100 mm<160.71 mm), and may be the second control line 220-2 not supplied with a terminal voltage.

FIG. 6 is a diagram illustrating a connection form of control lines according to an example. For example, FIG. 6 illustrates an example in which multiple memory chips are connected to memory controller 210 in a flying-connect topology.

6, the memory controller and the memory chip may include a plurality of ports 213, 214, 231-1, . . . , 231-n, 232-1, . . , 231-m. The conductive pattern may include a plurality of control lines A and B for connecting the above-mentioned plurality of ports. At least one of the plurality of control lines A and B may be a first control line 220-1, and the other may include a second control line 220-2.

For example, assume that the third control signal is supplied to the plurality of memory chips through the third port 213 of the memory controller and the fourth control signal is supplied to the plurality of memory chips through the fourth port 214 .

In this case, if the wiring length between the third port 213 of the memory controller and the port 231-1 of the first memory chip is longer than the distance according to Equation 1 above (A>λ/8), then A The control line may be a first control line 220-1 connected to a resistor connected at a terminal to a terminal voltage.

Conversely, if the wiring length between the fourth port 214 of the memory controller and the port 232-1 of the first memory chip is shorter than the distance according to Equation 1 above (B<λ/8), the B control line may be The second control line 220-2 is not connected to the terminal voltage at the terminal.

FIG. 7 is an eye diagram of a case where the terminal voltage is not supplied by being spaced apart by a predetermined length, and FIG. 8 is an eye diagram of the case where the terminal voltage is not supplied by being arranged below the predetermined length.

7, when the length of the control line is greater than or equal to a predetermined length, by touching the eye mask specification, a malfunction may occur in the system operation.

8, when the length of the control line is less than the predetermined length, even if the same terminal voltage is not supplied, since the mask specification is not touched, no malfunction occurs.

As described above, the electronic device according to the present disclosure may not implement or include a design for providing a terminal voltage when the wiring length of the control line satisfies a predetermined condition, thereby securing additional space and reducing material cost.

The foregoing examples are merely examples and should not be construed as limiting the present disclosure. The present disclosure can easily be applied to other types of devices. Furthermore, the descriptions of the examples of the present disclosure are intended to be illustrative, and not to limit the scope of the claims, and many substitutions, modifications and variations of the examples described herein are possible.

Claims (15)

1. An electronic device comprising: memory chip; a memory controller for controlling the operation of the memory chip; Capacitive elements to provide terminal voltages; and Conductive patterns, including: a first control line for connecting from a first terminal of the memory controller to a first terminal of the memory chip and to the capacitive element, and A second control line for connecting from the second terminal of the memory controller to the second terminal of the memory chip without connecting to the capacitive element. 2. The electronic device according to claim 1, wherein the wiring length of the first control line is longer than a predetermined length, and the wiring length of the second control line is shorter than the predetermined length. 3. The electronic device of claim 2, wherein the predetermined length is determined according to the following equation: C/(8*F) where C is the speed of light and F is the operating frequency of the control signal. 4. The electronic device of claim 1, wherein the first control line is connected to the capacitive element through a resistor. 5. The electronic device of claim 1, wherein the second control line is used to connect from the second terminal of the memory controller to the second terminal of the memory chip without connecting to the resistor. 6. The electronic device of claim 1, wherein, The electronic device includes a plurality of memory chips, the first control lines are sequentially connected from the first terminals of the memory controller to the first terminals of the plurality of memory chips, respectively, and The second control lines are sequentially connected from the second terminals of the memory controller to the second terminals of the plurality of memory chips, respectively. 7. The electronic device of claim 6, wherein, a wiring length of the first control line between the memory controller and a first memory chip among the plurality of memory chips is longer than the predetermined length, and A wiring length of the second control line between the memory controller and the first memory chip is shorter than the predetermined length. 8. The electronic device of claim 6, wherein the first control line and the second control line each transmit a control signal to control the plurality of memory chips. 9. The electronic device of claim 8, wherein the control signals comprise bank address groups, column access strobe signals, row address strobe signals, write enable signals, chip select signals, die termination signals or At least one of the clock enable signals. 10. The electronic device of claim 8, wherein the control signals are sequentially provided to the plurality of memory chips, respectively. 11. The electronic device of claim 6, wherein the plurality of memory chips is one of two memory chips, four memory chips, eight memory chips, sixteen memory chips, and thirty-two memory chips One. 12. The electronic device of claim 1, wherein, The electronic device includes a plurality of capacitive elements, the conductive pattern includes a plurality of first control lines, and Each of the plurality of first control lines is connected to a corresponding capacitive element among the plurality of capacitive elements. 13. The electronic device of claim 6, further comprising: a memory module on which the plurality of memory chips are disposed; and a circuit board provided with a socket including a plurality of terminals electrically connected to the memory module, and Wherein, the first control wire is connected to one terminal of the plurality of terminals of the socket, and the second control wire is connected to the other terminal of the plurality of terminals of the socket. 14. The electronic device of claim 1, wherein the terminal voltage is half of a driving voltage of the memory chip. 15. An image forming apparatus comprising: memory for storing image data; and a processor for performing control over the image forming apparatus to perform an image forming job with respect to the image data, and Wherein, the memory includes: memory chip; Capacitive elements to provide terminal voltages; and Conductive patterns, including: a first control line for connecting from a first terminal of the processor to a first terminal of the memory chip and to the capacitive element, and A second control line for connecting from the second terminal of the processor to the second terminal of the memory chip and not connecting to the capacitive element.

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