CN114556870B - Data synchronization method and device - Google Patents

Abstract

The embodiment of the application discloses a method and a device for data synchronization, wherein the method comprises the following steps: through using retimers with different numbers of lanes to stack together to form PCIe links with different widths, in order to maintain synchronous operation, interaction of synchronization information between the retimers is realized through pins, so as to synchronize the state of data transmitted inside each retimer in real time, that is, multiple retimers can perform real-time synchronous adjustment on the transmitted data while transmitting data, complying with the same adjustment rule sent by the pins, thereby achieving the purpose of merging physical lanes inside multiple retimers into a physical lane on one PCIe link.

Description

Method and device for data synchronization

technical field

The present application relates to the technical field of high-speed communication, and in particular to a data synchronization method and device.

Background technique

In modern computer systems, high-speed serial computer expansion bus standard (Peripheral Component Interface Express, PCIe) links are used to interconnect many different devices and computer systems. One of the characteristics of a PCIe link is that it can have different widths, for example: a PCIe link can have 1 lane (also called a physical lane), 2 lanes, 4 lanes, 8 lanes or 16 lanes ( It can also be called x1, x2, x4, x8 or x16) etc. respectively. The greater the number of channels, the overall data throughput of the communication increases proportionally. But one disadvantage of using a PCIe link is that the PCIe link has a relatively limited length so that data can be transmitted at a high speed. In order to achieve longer-distance high-speed transmission, a retimer (Retimer) was developed to allow the signals on each channel of the PCIe link to be retimed or resynchronized and re-driven, that is, signal relay through the retimer And filter out the jitter of the signal on the PCIe link.

Since PCIe links can have different types of lane counts like x1, x2, x4, x8, or x16, retimers for a given width are typically used. For example, if there is a retimer in the PCIe link, an 8-lane PCIe link corresponds to an 8-lane retimer, and a 16-lane PCIe link corresponds to a 16-lane retimer.

However, if the PCIe link needs more channels (for example, 32 channels), and the corresponding retimer in the PCIe link (for example, the retimer has only 8 channels) cannot meet the bandwidth requirement of the PCIe link, it is necessary to Replacing the retimer (for example, replacing it with a retimer with 32 channels) is very inconvenient and has poor flexibility, and a retimer with more channels will have a relatively more complicated structure and require more space. Large, which has limitations in some applications in space-constrained printed circuit boards.

Contents of the invention

The first aspect of the embodiment of the present application provides a data synchronization method and device for stacking multiple retimers to form a PCIe link with a larger number of channels to transmit data, that is, the multiple retimers are transmitting The data can comply with the same adjustment rules to carry out real-time synchronous adjustments to the transmitted data.

In view of this, the first aspect of the embodiment of the present application provides a device, which specifically includes:

The first retimer (also known as the master retimer) and the second retimer (also known as the slave retimer, which can be one or more) transmit signals to each other through pins. The first retimer The timer includes a first deviation processing module, and the second retimer includes a second deviation processing module. Firstly, the second retimer obtains the second time point when the data transmitted inside the second retimer (that is, the second transmission data) is transmitted to the second deviation processing module (the second retimer obtains the second time point of the second time point The steps can be triggered by a certain instruction, such as the instruction sent by the first retimer to the second retimer through the pin), and the second time point is sent to the first retimer through the pin, and the first retimer The timer determines a time point according to the first time point (that is, the time point when the first transmission data transmitted inside the first retimer is transmitted to the first deviation processing module) and the second time point sent by the second retimer. The target time point (the target time point is after the first time point and the second time point), and the target time point is synchronized to the second retimer through the pin, and finally, the first deviation processing module and the second deviation processing module At the target time point, the modules resend the received transmission data at the same time, so that the data transmission is synchronized.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer can adjust the data being transmitted on each channel within the multiple retimers in real time and synchronously based on the same target time point, that is, across The transmission of retimer data on each channel can be kept synchronous and continuous, thus meeting the requirement for higher bandwidth of the PCIe link without adding additional cost and complexity.

With reference to the first aspect of the present application, in the first implementation manner of the first aspect of the present application, the second deviation processing module is used to obtain the second time point when the second transmission data is transmitted to the second deviation processing module, and convert the first The step of synchronizing the second time point to the first deviation processing module through the first pin may be triggered by a trigger instruction (which may be called a first trigger instruction) sent by the first deviation processing module to the second deviation processing module through the first pin. When executed, the first trigger instruction is used to instruct the second deviation processing module to acquire the second time point and synchronize the second time point to the first deviation processing module through the first pin.

In the above-mentioned embodiments of the present application, it is explained that the second deviation processing module is triggered by the first trigger command sent by the first deviation processing module through the first pin to execute the step of obtaining the second time point, which has flexibility.

With reference to the first implementation manner of the first aspect of the present application, in the second implementation manner of the first aspect of the application, the above-mentioned first trigger instruction may be that the first transmission data acquired by the first deviation processing module is transmitted to the first The first moment of the deviation processing module.

In the above embodiments of the present application, it is very simple to explain that the first trigger instruction may also be the first point in time.

In combination with the first aspect of the present application and the first implementation manner to the second implementation manner of the first aspect of the application, in the third implementation manner of the first aspect of the application, the first retimer may also include a first Link negotiation state machine, the second retimer may also include a second link negotiation state machine. Wherein, the first link negotiation state machine and the second link negotiation state machine are used to perform link negotiation before the first deviation processing module determines the target time point.

In the above embodiments of the present application, it is stated that the two retimers included in the device need to perform link negotiation before being used for data alignment.

With reference to the third implementation manner of the first aspect of the embodiment of the present application, in the fourth implementation manner of the first aspect of the application, the first link negotiation state machine and the second link negotiation state machine are used to Before the deviation processing module determines the target time point, the link negotiation can be specifically performed: a second link negotiation state machine, which is specifically used to obtain the status of each physical channel in the second deviation processing module (such as which physical channels are transmitting parallel data streams) state, which physical channels have transmitted physical specific data streams, which physical channels have transmitted what kind of data streams, etc.), this state can be called the second state, and then the second link negotiation state machine is also used to use the first The two states are synchronized to the first link negotiation state machine through the second pin. Similarly, the first link negotiation state machine is specifically used to obtain the state of each physical channel in the first deviation processing module (may be referred to as the first State), after that, the first link negotiation state machine is used to determine the jump time according to the first state and the second state, and is used to further synchronize the jump time to the second link negotiation state through the second pin In this way, the first link negotiation state machine and the second link negotiation state machine are also used to simultaneously perform link negotiation at the jump moment. For example, the first link negotiation state machine may start timing after acquiring the second state, and after the timing reaches a specific duration, the first link negotiation state machine and the second link negotiation state machine simultaneously perform link negotiation.

In the above embodiments of the present application, how the first link negotiation state machine and the second link negotiation state machine in the two retimers in the device are used to transfer information through the second pin for link Road negotiation, with operability.

In combination with the fourth implementation manner of the first aspect of the embodiment of the present application, in the fifth implementation manner of the first aspect of the application, the second link negotiation state machine is specifically used to obtain the The second state of the channel, and the step of synchronizing the second state to the first link negotiation state machine can be the first state sent by the first link negotiation state machine to the second link negotiation state machine through the second pin The first state sent to the second link negotiation state machine via the second pin is used to instruct the second link negotiation state machine to execute the step of acquiring the second state.

In the above-mentioned embodiments of the present application, it is stated that the second link negotiation state machine is used to trigger the execution of the step of obtaining the second state by the first state sent by the first link negotiation state machine through the second pin, which is flexible. sex.

With reference to the fifth implementation of the first aspect of the embodiment of the present application, in the sixth implementation of the first aspect of the application, the first link negotiation state machine and the second link negotiation state machine are used to The way to perform link negotiation at the same time may be: the first link negotiation state machine, specifically used to perform link negotiation according to the first state and the second state at the determined jump moment; the second link negotiation state machine, specifically using Link negotiation is performed according to the first state and the second state at the same jumping moment. According to the definition of the PCIe protocol, as long as the same jump time is determined (that is, to ensure that the two link negotiation state machines work synchronously), the first link negotiation state machine and the second link negotiation state machine can be completely consistent at the same time. In this way, the two retimers can be combined into one link for link negotiation.

In the above-mentioned embodiments of the present application, both the first link negotiation state machine and the second link negotiation state machine are used to obtain the first state and the second state, so at the same jump moment, according to the jump defined by the PCIe protocol In the switching mode, the first link negotiation state machine and the second link negotiation state machine can be used to realize the fully synchronous switching mode, which is simple and convenient.

In combination with the first aspect of the present application and the first to sixth implementation manners of the first aspect of the present application, in the seventh implementation manner of the first aspect of the present application, the first retimer may further include a first cache device, the second retimer can also include a second buffer; wherein, the second buffer is used to determine the second character code ordered set (also referred to as SKP, a character of a physical layer defined in the PCIe protocol Code) data state (can be called the fourth state), and the fourth state is synchronized to the first buffer through the third pin, similarly, the first buffer is also used to obtain the state of the first SKP data ( It can be called the third state), and then the first buffer is used to determine the SKP addition and deletion rules according to the third state and the fourth state, and is used to further synchronize the determined SKP addition and deletion rules to the second cache through the third pin In this way, the first buffer and the second buffer are also used to respectively adjust the first transmission data and the second transmission data according to the same SKP addition and deletion rule.

In the above-mentioned embodiments of the present application, how the first buffer and the second buffer in the two retimers in the device are used to transmit information through the third pin to synchronize the frequency offset is described in detail, which is operable .

With reference to the seventh implementation manner of the first aspect of the present application, in the eighth implementation manner of the first aspect of the application, the second buffer is used to determine the fourth state of the second SKP data, and pass the fourth state through The step of synchronizing the third pin to the first buffer may be triggered by a trigger instruction (which may be referred to as a second trigger instruction) sent by the first buffer to the second buffer through the third pin. The second trigger instruction It is used to instruct the second buffer to execute the step of acquiring the fourth state and synchronizing the fourth state to the first buffer through the third pin.

In the above embodiments of the present application, it is stated that the second buffer is triggered by the second trigger instruction sent by the first buffer through the third pin to execute the step of acquiring the fourth state, which has flexibility.

With reference to the eighth implementation manner of the first aspect of the present application, in the ninth implementation manner of the first aspect of the application, the second trigger instruction may be the third state of the first SKP data acquired by the first buffer.

In the above embodiments of the present application, it is very simple to explain that the second trigger instruction can also be in the third state.

With reference to the seventh to ninth implementations of the first aspect of the present application, in the tenth implementation of the first aspect of the present application, the first buffer may include a first receiving buffer and a first sending buffer ; The second buffer may include a second receiving buffer and a second sending buffer.

In the above-mentioned embodiments of the present application, it is explained that the first buffer and the second buffer may include various types of buffers, which have flexibility.

In combination with the first aspect of the present application and the first to tenth implementation manners of the first aspect of the present application, in the eleventh implementation manner of the first aspect of the present application, the second retimer may be a retimer timer, or multiple retimers, which are not limited here.

In the above embodiments of the present application, the device is not limited to include only two retimers, but may also include more retimers to meet the requirements for various PCIe link widths.

The second aspect of the present application also provides a data synchronization method, which specifically includes:

First, the second retimer transmits the second transmission data in the second retimer to the second time point of the second deviation processing module in the second retimer through the first pin to synchronize to the first retimer; After that, the first retimer determines the target time point according to the obtained first time point and the second time point, and synchronizes the target time point to the second retimer through the first pin, wherein the first time point is The first transmission data in the first retimer is transmitted to the time point of the first deviation processing module in the first retimer; finally, the first deviation processing module and the second deviation processing module respectively send the first transmission at the target time point data and the second transmission data to achieve the purpose of synchronously aligning data.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer can adjust the data being transmitted on each channel within the multiple retimers in real time and synchronously based on the same target time point, that is, across The transmission of retimer data on each channel can be kept synchronous and continuous, thus meeting the requirement for higher bandwidth of the PCIe link without adding additional cost and complexity.

In combination with the second aspect of the present application, in the first implementation of the second aspect of the present application, the second deviation processing module in the second retimer acquires the second transmission data through the first pin of the second retimer The second time point is synchronized to before the first retimer, and the method may also include: the first retimer sends a first trigger instruction to the second retimer through the first pin, and the first trigger instruction is used for Instruct the second retimer to execute the step of obtaining the second time point.

In the above embodiments of the present application, it is explained that the second retimer is triggered by the first trigger instruction sent by the first retimer through the first pin to execute the step of obtaining the second time point, which has flexibility.

With reference to the first implementation manner of the second aspect of the present application, in the second implementation manner of the second aspect of the application, the above-mentioned first trigger instruction may be that the first transmission data acquired by the first retimer is transmitted to the first The first moment of the deviation processing module.

In the above embodiments of the present application, it is very simple to explain that the first trigger instruction may also be the first point in time.

In combination with the second aspect of the present application and the first to second implementation manners of the second aspect of the application, in the third implementation manner of the second aspect of the application, the first retimer and the second retiming Before performing data alignment (that is, before the first retimer determines the target time point according to the obtained first time point and the second time point), it is also necessary to send the states of the physical channels used to transmit data to the The first link negotiation state machine in the first retimer and the second link negotiation state machine in the second retimer make the first link negotiation state machine and the second link negotiation state machine in the first The deviation processing module performs link negotiation before determining the target time point.

In the above embodiments of the present application, it is stated that the two retimers included in the device need to perform link negotiation before data alignment.

In combination with the third implementation manner of the second aspect of the embodiment of the present application, in the fourth implementation manner of the second aspect of the application, the manner in which the first link negotiation state machine and the second link negotiation state machine perform link negotiation It may be that: the second retimer obtains the second state of the channels used to transmit the second transmission data (such as which physical channels are in the state of transmitting parallel data streams, which physical channels transmit specific physical data streams, which physical channels transmit what kind of data flow, etc.), and synchronize the second state to the first retimer through the second pin; after that, the first retimer determines the jump according to the obtained first state and second state Time, and synchronize the jump time to the second retimer through the second pin, wherein the first state is the state of the channel transmitting the first transmission data in the first retimer; finally, the first link negotiation The state machine and the second link negotiation state machine perform link negotiation at the jump moment. For example, the first link negotiation state machine may start timing after acquiring the second state, and after the timing reaches a specific duration, the first link negotiation state machine and the second link negotiation state machine simultaneously perform link negotiation.

In the above embodiments of the present application, how the first link negotiation state machine and the second link negotiation state machine in the two retimers in the device transmit information through the second pin for link negotiation in detail , is operable.

With reference to the fourth implementation manner of the second aspect of the embodiment of the present application, in the fifth implementation manner of the second aspect of the application, the second retimer obtains the second state of the channel for transmitting the second transmission data, and The second state is synchronized to before the first retimer through the second pin, and the method may further include: the first retimer sends the first state to the second link negotiation state machine through the second pin, and the first retimer sends the first state to the second link negotiation state machine through the second pin. A state is used to trigger the second retimer to execute the step of obtaining the second state, and the first state sent to the second link negotiation state machine via the second pin is used to instruct the second link negotiation state machine to obtain the second state Two state steps.

In the above embodiments of the present application, it is stated that the second link negotiation state machine is triggered by the first state sent by the first link negotiation state machine through the second pin to execute the step of obtaining the second state, which is flexible.

In combination with the fifth implementation of the second aspect of the embodiment of the present application, in the sixth implementation of the second aspect of the application, the first link negotiation state machine and the second link negotiation state machine simultaneously perform The link negotiation method may be: the first link negotiation state machine performs link negotiation according to the first state and the second state at the determined jump moment; the second link negotiation state machine also performs link negotiation according to the second state at the same jump moment. The first state and the second state carry out link negotiation. According to the definition of the PCIe protocol, as long as the same jump moment is determined (that is, the two link negotiation state machines are guaranteed to work synchronously), the first link negotiation state machine and the second link negotiation state machine The link negotiation state machine can simultaneously carry out completely consistent link negotiation methods, so as to achieve the purpose of merging two retimers into one link for link negotiation.

In the above-mentioned embodiments of the present application, both the first link negotiation state machine and the second link negotiation state machine obtain the first state and the second state, so at the same jump moment, the jump defined by the PCIe protocol In this way, the first link negotiation state machine and the second link negotiation state machine can realize a completely synchronous jump mode, which is simple and convenient.

In combination with the second aspect of the present application and the first to sixth implementation manners of the second aspect of the present application, in the seventh implementation manner of the first aspect of the present application, the second retimer obtains the second retimer The state of the second SKP data in the second buffer (may be referred to as the fourth state), and synchronize the fourth state to the first retimer through the third pin, similarly, the first retimer will also Obtain the state of the first SKP data (can be referred to as the third state, the third state is the state of the first SKP data in the first buffer in the first retimer), afterward, the first retimer is just according to The third state and the fourth state determine the SKP addition and deletion rules, and further synchronize the determined SKP addition and deletion rules to the second retimer through the third pin, so that the first retimer and the second retimer are based on the The same SKP addition and deletion rules adjust the first transmission data and the second transmission data respectively.

In the above embodiments of the present application, it is specifically described how the first register and the second register in the two retimers in the device transmit information through the third pin to process the frequency offset synchronously, which is operable.

With reference to the eighth implementation manner of the second aspect of the present application, in the ninth implementation manner of the second aspect of the application, the above-mentioned second trigger instruction may be the third state of the first SKP data acquired by the first buffer.

In the above embodiments of the present application, it is very simple to explain that the second trigger instruction can also be in the third state.

With reference to the seventh implementation mode to the ninth implementation mode of the second aspect of the present application, in the tenth implementation mode of the second aspect of the application, the first buffer may include a first receiving buffer and a first sending buffer ; The second buffer may include a second receiving buffer and a second sending buffer.

In the above-mentioned embodiments of the present application, it is explained that the first buffer and the second buffer may include various types of buffers, which have flexibility.

In combination with the second aspect of the present application and the first to tenth implementation manners of the second aspect of the application, in the eleventh implementation manner of the second aspect of the application, the second retimer may be a retiming timer, or multiple retimers, which are not limited here.

In the above embodiments of the present application, the device is not limited to include only two retimers, but may also include more retimers to meet the requirements for various PCIe link widths.

A third aspect of the embodiments of the present application provides an apparatus, which has a function of implementing the method of the second aspect or any possible implementation manner of the second aspect. This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware. The hardware or software includes one or more modules corresponding to the above functions.

It can be seen from the above technical solutions that the embodiments of the present application have the following advantages: the first retimer (also called the master retimer) and the second retimer (also called the slave retimer) can be one or Multiple) transmit signals to each other through pins, the first retimer includes a first deviation processing module, and the second retimer includes a second deviation processing module. Firstly, the second retimer obtains the second time point when the data transmitted inside the second retimer (that is, the second transmission data) is transmitted to the second deviation processing module (the second retimer obtains the second time point of the second time point The steps can be triggered by a certain instruction, such as the instruction sent by the first retimer to the second retimer through the pin), and the second time point is sent to the first retimer through the pin, and the first retimer The timer determines a time point according to the first time point (that is, the time point when the first transmission data transmitted inside the first retimer is transmitted to the first deviation processing module) and the second time point sent by the second retimer. The target time point (the target time point is after the first time point and the second time point), and the target time point is synchronized to the second retimer through the pin, and finally, the first deviation processing module and the second deviation processing module At the target time point, the modules resend the received transmission data at the same time, so that the data transmission is synchronized. In the embodiment of the present application, the first retimer and the second retimer can adjust the data being transmitted on each channel within the multiple retimers in real time and synchronously based on the same target time point, that is, across retimers The transmission of timer data on each channel can be kept synchronous and continuous, thus meeting the requirement for higher bandwidth of the PCIe link without adding additional cost and complexity.

Description of drawings

FIG. 1 is a schematic diagram of a PCIe link without a retimer;

Figure 2 is a schematic diagram of a PCIe link with a retimer;

FIG. 3 is a schematic diagram of a PCIe link with multiple retimers;

Fig. 4 is a schematic diagram of forming a complete PCIe link through a retimer between devices;

Fig. 5 is a schematic diagram of the internal structure of the retimer;

FIG. 6 is a schematic structural diagram of multiple channels formed inside the retimer;

Fig. 7 is the schematic diagram that various different types of PCIe links in the embodiment of the present application are connected by multiple retimers through pins to widen the link width;

8 is a schematic diagram of two retimers implementing data synchronization through pin synchronization information according to an embodiment of the present application;

FIG. 9 is a schematic diagram of the number of pins included in the first pin in the embodiment of the present application;

FIG. 10 is a schematic diagram of data transmission in a channel according to an embodiment of the present application;

FIG. 11 is a schematic diagram of implementing data alignment in the deviation processing module of the retimer according to the embodiment of the present application;

FIG. 12 is a schematic diagram of the pin signal of the embodiment of the present application;

FIG. 13 is a schematic diagram of a data synchronization method provided by an embodiment of the present application.

Detailed ways

The embodiment of the present application provides a data synchronization method and device, which are used to enable multiple retimers to be stacked into a PCIe link with a larger number of channels to transmit data, that is, the multiple retimers can transmit data when transmitting data Real-time synchronous adjustments are made to the transmitted data following the same adjustment rules.

Before introducing the embodiments of the present application, some system architectures, related structures and some concepts that may appear in the embodiments of the present application that may be involved in the embodiments of the present application are firstly introduced to help understand the present invention. It should be understood that the related system architecture, related structures, etc. described in this application only illustrate the parts related to the embodiment of the application, and the following descriptions and explanations of related concepts may be different from the description of the embodiment of the application. The specific situation is limited, but it does not mean that the application can only be limited to the specific situation, and there may be differences in the specific situations of different embodiments, which are not specifically limited here. Also in the present application, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring the application.

A retimer is a device similar to a physical layer chip. When a signal passes through the retimer, the internal clock of the retimer can reconstruct the signal so that the signal transmission energy increases, and then continues to transmit. That is to say, the retimer is a device with Clock Data Recover (CDR) inside. After the signal is recovered, the signal is then sent out through its internal physical channel, so that the signal jitter can be reduced.

Figure 1 shows a PCIe link without a retimer, device 1 and device 2 are coupled together via link A and link B (link A and link B are divided according to the direction of data transmission, in fact Integrated in a PCIe link, that is, link 1 and link 2 constitute a complete PCIe link between device 1 and device 2), and the data that needs to be exchanged between device 1 and device 2 passes through link A and link A. Route B achieves high-speed transmission. Since the PCIe link has a relatively limited length (in order to ensure high-speed transmission, the length of the PCIe link is limited), if the physical distance between device 1 and device 2 is too far, it will inevitably lead to a single PCIe link. The link is too long, which affects the data transmission efficiency. For this reason, a retimer is connected between device 1 and device 2, so that the data being transmitted on the PCIe link can be retimed or resynchronized and re-driven, as shown in Figure 2 with a retimer PCIe link, device 1 and device 2 are coupled to a retimer 01, which is coupled to device 1 through sub-link A01 and sub-link B02, and coupled to device through sub-link A02 and sub-link B01 2. These sub-links constitute a complete PCIe link for data exchange between device 1 and device 2. Moreover, these sub-links also follow the PCIe protocol, and the retimer 01 can be configured to operate with the protocol followed by the sub-links to realize data interaction between the device 1 and the device 2 . Similarly, in order to achieve longer-distance high-speed transmission, the PCIe link between device 1 and device 2 can also have two or more retimers, as shown in Figure 3, which shows that there are multiple retimers The PCIe link of the timer, these retimers are connected sequentially in a similar way in series (retimer 1, retimer 2, ..., retimer n in Figure 3, n≥2 ), connecting sub-links A1, sub-link A2, sub-link A3, ..., sub-chains of retimer 1, retimer 2, ..., retimer n Road An, sub-link An+1, sub-link B1, sub-link B2, ..., sub-link Bn-1, sub-link Bn, sub-link Bn+1 constitute equipment 1 and A complete PCIe link for data exchange between devices 2.

For further understanding, the following takes device 1 as a central processing unit (Central Processing Unit/Processor, CPU) board, and device 2 as an input/output (I/O) board as an example to illustrate the CPU board and I/O board in detail. How the O board forms a PCIe link through the retimer, please refer to Fig. 4, the CPU board 401 is connected with the I/O board 403 through the backplane 402, wherein, the retimer 4012 is placed in the CPU board 401 (the retimer can It is arranged inside the device, and it can also be arranged outside the device, which is not limited. Figure 4 shows that the retimer is set inside the CPU board), and is connected with the CPU4011 in the CPU board 401, so that the CPU4011 and the retimer 4012 Just form a sub-link 4013 of the whole PCIe link (for example, the sub-link of 16 lanes of PCIe), after that, the retimer 4012 is connected to the connector 404 on the backplane 402 again, and the connector 404 is connected with the The connector 405 is connected to form the entire PCIe sub-link 4021, and the connector 405 is further connected to the retimer 4031 inside the I/O board 403, and the retimer 4031 is connected to the CPU4032 inside the I/O board 403 to form a The sub-link 4033 of the entire PCIe. Due to the distance between CPU4011 and CPU4032 and the existence of connectors 404 and 405, data exchange between CPU4011 and CPU4032 cannot be performed directly. However, since two retimers are respectively arranged inside the CPU board 401 and the I/O board 403, the data interaction between the CPU4011 and the CPU4032 can be constituted by the sub-link 4013, the sub-link 4021, and the sub-link 4033. A complete PCIe link (for example, a 16-lane PCIe link) for high-speed transmission.

The above-mentioned Figures 2 to 4 introduce the application of the retimer in practice. The internal structure of the retimer is introduced below. As shown in Figure 5, it is a typical structure inside the retimer. The retimer The device includes a serializer/deserializer (Serializer and De-serializer, Serdes) 501, a buffer 502, a deviation processing module 503, a link negotiation state machine 504, a buffer 505, and a serializer/deserializer 506. The above-mentioned devices inside the retimer are described with the flow of the data stream: before the data stream is acquired by the serial/deserializer 501 (also called the receiving serializer/deserializer 501) in the retimer It is a serial data stream. After the serial/deserializer 501 obtains the serial data stream on the PCIe link, it will convert the serial data stream into a parallel data stream. The parallel data stream is passed through the serial/deserialization The channel (Lane, which may also be referred to as a physical channel) of the device 501 is used for transmission. The serial/deserializer 601 shown in FIG. , if N=1, it means that the retimer is a retimer with 2 physical channels (that is, a retimer of x2 type), and if N=7, it means that the retimer is a retimer with 8 physical channels A retimer (i.e. a retimer of x8 type), if N=15, it means that this retimer is a retimer with 16 physical channels (i.e. a retimer of x16 type), how many physical channel, the retimer is a retimer of the corresponding type (eg, x1, x2, x8, x16, etc.), which will not be described in detail here. It should be noted that the parallel data streams being transmitted on the physical channels inside the same retimer do not interact with each other, but the physical channels of the data streams being transmitted must maintain transmission synchronization. It should also be noted that all physical channels inside the retimer are not required to be used when transmitting data streams. For example, for an x16 type retimer, only 10 of them can be used when transmitting data. channel for data transfer.

After the serial/deserializer 501 processes the serial data stream into a parallel data stream, it will write the parallel data stream into the buffer 502 (also called the receive buffer 502), and the buffer 502 is a data path Each physical channel corresponds to a buffer. For example, if there are 8 physical channels in the serial/deserializer 501, then the buffer 502 refers to the set of buffers corresponding to each physical channel. (that is, there are 8 buffers), as shown in Figure 6, there are N+1 physical channels for transmitting data in the serial/deserializer 601, then the corresponding buffer 602 is buffer 10 to buffer 1N collection. Since the write clock of the buffer 502 is the clock recovered by the CDR in the serial/deserializer 501, and the read clock of the buffer 502 is the local working clock, that is, the read and write clock of the buffer 502 is an asynchronous clock, so it is written The parallel data streams entering the buffer 502 will have frequency offset. In order to eliminate the influence of frequency offset, after the buffer 502 receives the parallel data stream from the serializer/deserializer 501, it must first perform frequency offset processing, that is, to ensure that the receiving buffer corresponding to each physical channel that is transmitting data does not overflow (i.e. no data loss), the processing method is to ensure that the corresponding receiving buffer does not overflow through the character code (SKP, a character code of the physical layer) addition and deletion rules (for example, according to the preset rules in the corresponding receiving buffer delete SKP data).

After the buffer 502 performs frequency offset processing on the parallel data stream, the parallel data stream is further transmitted to the deviation processing module 503. Similarly, the deviation processing module 503 also has the same number of physical channels as the serial/deserializer 501 ( For example, the deviation processing module 603 in FIG. 6 has a total of N+1 physical channels from Lane0 to LaneN) for receiving the parallel data streams transmitted through the buffers included in the buffer 502, because the parallel data streams are composed of different The buffer corresponding to the physical channel is transmitted to the deviation processing module 503, then the parallel data streams transmitted through different buffers will cause each buffer received by the deviation processing module 503 to send The data are not synchronous (that is, what comes first and what comes later does not arrive strictly synchronously), and one of the functions of the deviation processing module 503 is to align the parallel data streams obtained on each internal physical channel.

It should be noted that before the deviation processing module 503 aligns the obtained data streams of each physical channel, it also needs to check the status of each physical channel (such as which physical channels are in the state of transmitting parallel data streams, which physical channels have transmitted The physical specific data flow, which physical channel transmits what kind of data flow, etc.) is sent to the link negotiation state machine (Link Training and Status State Machine, LTSSM) 504, and the link negotiation state machine 504 is based on the state of each physical channel Link negotiation is performed (the way of link negotiation is clearly defined in the PCIe protocol, which will not be repeated here). Afterwards, the link negotiation state machine 504 sends the negotiation result (such as negotiation success, negotiation failure, etc.) to the deviation processing module 503, and if the negotiation result is that the negotiation is successful, then in response to the negotiation result, the deviation processing module 503 will The parallel data streams on each physical channel obtained by the processor 502 are aligned, and then the aligned parallel data streams are further written into the buffer 505 (also referred to as the sending buffer 505).

Similar to the buffer 502, the buffer 505 is the transmission buffer of the data path, and each physical channel corresponds to a buffer. For example, if there are 8 physical channels in the serial/deserializer 501, the buffer 505 is Refers to the set of buffers corresponding to each physical channel. As shown in FIG. to the set of buffers 2N. Similarly, the parallel data stream obtained in the buffer 505 also has a frequency offset, so it also needs to perform frequency offset processing on the obtained parallel data stream, that is, to ensure that the sending buffer corresponding to each physical channel that is transmitting data Continuous flow (that is, no data loss), the processing method is also to ensure that the corresponding sending buffer is not flowing through the SKP addition and deletion rules (for example, add SKP data in the corresponding sending buffer according to the preset rules).

After the buffer 505 performs frequency offset processing on the parallel data stream, the parallel data stream will be further written into the serializer/deserializer 506 (also referred to as the sending serializer/deserializer 506), similarly, the serializer/deserializer The serializer 506 also has the same number of physical channels as the serializer/deserializer 501 (for example, there are N+1 physical channels from Lane0 to LaneN in the serializer/deserializer 506 in FIG. 6 ), the serializer/deserializer The deserializer 506 converts the acquired parallel data streams on each physical channel into serial data streams and then sends them out via the PCIe link.

It can be seen from the above that the transmission of the data stream inside the retimer is carried out through multiple physical channels, and the data transmitted between the physical channels does not interact, but the data transmitted on each physical channel inside the retimer needs to be synchronized . At present, the retimer can only synchronize the data transmitted on each physical channel within itself, and multiple retimers can only be connected in series (as shown in Figure 3) to extend the PCIe link. length. However, in practical applications, if the PCIe link requires more physical channels (for example, 32 channels), and the corresponding retimer in the PCIe link (for example, the retimer has only 8 channels) cannot meet the requirements of the PCIe link. If the bandwidth requirement is high, the retimer needs to be replaced (for example, replaced with a retimer with 32 channels). If more retimers are connected in a similar series-connected form in the PCIe link, the replacement will be more troublesome.

Based on this, the embodiment of the present application provides a device, the idea of which is to send synchronization information through the pins between multiple retimers, and then synchronize the state of the data transmitted inside each retimer in real time, so as to achieve The purpose of merging the physical channels inside multiple retimers into one physical channel on the PCIe link. For ease of understanding, please refer to Figure 7, assuming that each retimer in Figure 7 is a retimer with 4 physical channels, if the PCIe link only needs one retimer, such as the connection method in (a), then The PCIe link formed at this time is a x4-type PCIe link; as shown in (b), two retimers with 4 physical channels transmit synchronization information through pin 01 to implement x8-type PCIe Link; similarly, as shown in (c), four retimers with 4 physical channels respectively transmit synchronization information through pin 02, pin 03, and pin 04 to realize x16 type PCIe chain By adopting different numbers and different types of retimers to stack according to the implementation idea mentioned above, the existing PCIe link can be expanded into a PCIe link with various physical channels to meet user needs. It should be noted that, in the above implementation manner, the pin 01 , the pin 02 , the pin 03 or the pin 04 is a set of one or more pins, and is not limited to only one pin.

For ease of understanding, the following uses two retimers as an example to describe in detail how a device provided in the embodiment of the present application synchronizes data through pins. For details, please refer to Figure 8, where the data stream is transmitted from device 1 to device 2. For example, specifically explain the role played by different modules inside the first retimer and the second retimer in the synchronization process:

1. How the first retimer and the second retimer perform data alignment synchronously through the first pin.

In this embodiment of the application, the device for data synchronization may specifically include a first retimer and a second retimer, wherein the first retimer includes a first deviation processing module 803, a second retimer A second deviation processing module 703 is included, and the second deviation processing module 703 is used to obtain the time point ( can be referred to as the second time point), and synchronize the second time point to the first deviation processing module 803 through the first pin, similarly, the first deviation processing module 803 is also used to obtain The time point at which the data to be transmitted within (may be called the first transmission data) is transmitted to the first deviation processing module 803 (may be called the first time point), and then the first deviation processing module 803 is used to The time point and the second time point determine a target time point, the target time point is a time point after the first time point and the second time point, and further synchronize the target time point to the second time point through the first pin Deviation processing module 703, so that the first deviation processing module 703 and the second deviation processing module 803 can respectively send the first transmission data and the second transmission data when the target time point is reached, that is, the first deviation The processing module 803 and the second deviation processing module 703 align the data transmitted by each internal physical channel at the target time point and then perform data transmission synchronously.

It should be noted that, in some implementations of the present application, the second deviation processing module 703 is used to obtain the second time point when the second transmission data is transmitted to the second deviation processing module 703, and pass the second time point through the second time point The step of synchronizing a pin to the first deviation processing module 803 may be triggered by a trigger instruction (which may be referred to as a first trigger instruction) sent by the first deviation processing module 803 to the second deviation processing module 703 through the first pin, The first trigger instruction is used to instruct the second deviation processing module 703 to obtain the second time point and synchronize the second time point to the first deviation processing module 803 through the first pin; it can also be the second deviation processing Once the module acquires the second transmission data, it automatically determines the second time point when the second transmission data is transmitted to the second deviation processing module 703, and automatically synchronizes the second time point to the first deviation processing through the first pin Module 803 , specifically, the method of triggering the second deviation processing module 703 to obtain the second time point and send the second time point to the first deviation processing module 803 through the first pin is not limited.

It should also be noted that, in some embodiments of the present application, the above-mentioned first trigger instruction may be the first time point when the first transmission data acquired by the first deviation processing module 803 is transmitted to the first deviation processing module 803, or It may be a target information generated immediately after the first deviation processing module 803 obtains the first time point, and the target information is used to instruct the second deviation processing module 703 to obtain the second time point and send the first deviation processing module 803 Second, the specific form of the first trigger instruction is not limited here.

It should also be noted that, in some embodiments of the present application, there may be one or more first pins, and the first pin may also be a single-bit (bit) pin or a multi-bit pin. The feet are not limited here.

In order to facilitate the understanding of the above solution, the following takes the first pin including four pins for information synchronization as an example, and describes how the first deviation processing module 803 and the second deviation processing module 703 perform data alignment for synchronization. For a detailed schematic diagram, please refer to Referring to FIG. 9, the first pin includes pin 11, pin 12, pin 13, and pin 14, wherein the first deviation processing module 803 outputs two pins (ie, pin 11 and pin 12), and the first The second deviation processing module 703 obtains the information sent by the first deviation processing module 803 through pin 11 and pin 12, and the second deviation processing module 703 outputs two pins (ie, pin 13 and pin 14). The module 803 obtains the information sent by the second deviation processing module 703 through the pin 13 and the pin 14 . Because the deviation processing module inside the retimer performs data alignment in a specific time, the deviation processing module obtains the protocol-specific characters carried by each data being transmitted on the physical channel (the protocol-specific characters represent the data of each physical channel) The flags sent at the same time, such as the training sequence ordered set TS1/TS2, which are defined in the PCIe protocol, will not be described here), the deviation processing module performs data alignment according to the specific characters of the protocol, and then simultaneously aligns the data of each channel to transfer. Take a single retimer of type x4 as an example: as shown in Figure 10, each module (such as an offset processing module, buffer, etc.) in the retimer has 4 physical channels (such as the Lan0 to Lan4), when the data in each physical channel is sent by the receiving buffer, it will carry the protocol-specific character TS1 on the transmitted data at the same time when it is sent out. The protocol-specific character TS1 includes a COM and the following 15 8bits data. At the sending end (that is, the receiving buffer of the retimer), the 4 physical channels are COMs that are sent at the same time, and when the data on the 4 physical channels are transmitted to the deviation processing module, the situation shown in Figure 10 may appear, namely COM is not aligned, and there is a deviation in data between physical channels and physical channels (that is, the time when the data arrives at the deviation processing module is different), then the deviation processing is performed in the deviation processing module to align the data on each physical channel, as shown in the figure 11 shows the protocol-specific character TS1 carried by the aligned data. Afterwards, the deviation processing module can retransmit the aligned data to the next module in the retimer. Therefore, in the case of two retimers, when the first transmission data transmitted through each physical channel in the first retimer is transmitted to the first deviation processing module 803, there will also be a sequence difference, then when When the first deviation processing module 803 obtains the protocol-specific character (which may be referred to as the first protocol-specific character A1) carried in the first transmitted data in the physical channel, it will determine that the first protocol-specific character A1 is obtained Transmit to the time point 1 of the first deviation processing module 803, and synchronize the time point 1 to the second deviation processing module 703 through pin 11; when the first deviation processing module 803 obtains the last transmitted data in the physical channel When the protocol-specific character (can be referred to as the last protocol-specific character A2) is carried, it will be determined that the last protocol-specific character A2 is transmitted to the first deviation processing module 803 at the time point 2, and the time point 2 will be passed through The pin 12 is synchronized to the second deviation processing module 703 . Similarly,

When the second transmission data transmitted through each physical channel in the second retimer is transmitted to the second deviation processing module 703, there will also be a sequence difference, then when the second deviation processing module 703 obtains the first When the protocol-specific character (may be referred to as the first protocol-specific character B1) carried in the first transmitted data, it is determined that the time point 3 at which the first protocol-specific character B1 is transmitted to the second deviation processing module 703 is obtained, And this time point 3 is synchronized to the first deviation processing module 803 through the pin 13; when the second deviation processing module 703 obtains the protocol-specific character carried in the last transmitted data in the physical channel (which can be called the last protocol-specific character B2), it is determined that the time point 4 at which the last protocol-specific character B2 is transmitted to the second deviation processing module 703 is obtained, and the time point 4 is synchronized to the first deviation processing module 803 through the pin 14 . Afterwards, the first deviation processing module 803 can judge whether the time difference between time point 1, time point 2, time point 3, and time point 4 is within the standard time difference specified in the agreement (if the calculated time difference is greater than the standard time difference specified in the agreement, then Indicates that there is an error or delay in data transmission, and the data cannot be aligned at this time), if it is determined that the calculated time difference is less than the standard time difference, then the first deviation processing module 803 will determine a time point for data alignment (i.e. the target time point), And send the target time point to the second deviation processing module 703 through pin 11 or pin 12, and then, when the target time point is reached, the first deviation processing module 803 and the second deviation processing module 703 Align the data on the retimer, and then send the data on each physical channel at the target time point at the same time, so as to achieve the purpose of synchronous alignment of data in the two retimers.

It should be noted that the first pin may only include two pins, for example, it may only include pin 11 (or pin 12) and pin 13 (or pin 14), and the first deviation processing module 803 obtains Time point 1 and time point 2 can be synchronized to the second deviation processing module 703 through pin 11 (or pin 12). Similarly, time point 3 and time point 4 obtained by the second deviation processing module 703 are also both It can be synchronized to the first deviation processing module 803 through pin 13 (or pin 14). It should also be noted that the first pin can also include only one pin, and the first deviation processing module 803 and the second deviation processing module 703 can use this pin to divide time 1 and time 2 in a time-division multiplexing manner. , time 3, and time 4 are synchronized to each other, specifically, the number of pins included in the first pin and the specific manner of how to synchronize are not limited here.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer respectively obtain the time point when the data transmitted on each physical channel of the other party is transmitted to the respective internal deviation processing module through the first pin, and the The first retimer determines a target time point according to each time point, and further synchronizes the target time point to the second retimer, and when the target time point is reached, all physical channels across the retimer are started The data alignment operation completes the data alignment on the physical channel in all retimers.

2. How the first retimer and the second retimer perform link negotiation synchronously through the second pin.

In addition to the first retimer including the first deviation processing module 803 and the second retimer including the second deviation processing module 703, the first retimer may specifically include a first link negotiation state machine 804, a second Specifically, the retimer may also include a second link negotiation state machine 704 . It should be noted that, in some embodiments of the present application, before the first deviation processing module 803 and the second deviation processing module 703 perform data alignment, they also need to send the states of their respective physical channels for data transmission to the second A link negotiation state machine 804 and a second link negotiation state machine 704, the first link negotiation state machine 804 and the second link negotiation state machine 704 are used to determine the target time point before the first deviation processing module 803 Perform link negotiation.

The following describes how the first link negotiation state machine 804 and the second link negotiation state machine 704 perform link negotiation synchronously through the second pin: the second link negotiation state machine 704 is used to obtain the second deviation processing module The state of each physical channel in 703 (such as which physical channels are in the state of transmitting parallel data streams, which physical channels transmit specific physical data streams, which physical channels transmit what data streams, etc.), this state can be called the first Two states, and then the second link negotiation state machine 704 is also used to synchronize the second state to the first link negotiation state machine 804 through the second pin, similarly, the first link negotiation state machine 804 is also used After obtaining the state of each physical channel in the first deviation processing module 803 (which may be referred to as the first state), the first link negotiation state machine 804 is used to determine the jump time according to the first state and the second state , and is used to further synchronize the jump time to the second link negotiation state machine 704 through the second pin, so that the first link negotiation state machine 804 and the second link negotiation state machine 704 are also used for jumping Link negotiation is performed at the same time at all times. For example, the first link negotiation state machine 804 may start timing after acquiring the second state, and when the timing reaches a specific duration, the first link negotiation state machine 804 and the second link negotiation state machine 704 simultaneously perform link negotiation.

It should be noted that, in some embodiments of the present application, the second link negotiation state machine 704 is used to obtain the second state of each physical channel in the second deviation processing module 703, and synchronize the second state to the first The steps of the link negotiation state machine 804 can be executed by the first state trigger sent by the first link negotiation state machine 804 to the second link negotiation state machine 704 through the second pin, and sent to the second link negotiation state machine 704 through the second pin. The first state of the link negotiation state machine 704 is used to instruct the second link negotiation state machine 704 to execute the step of obtaining the second state.

It should also be noted that if the first link negotiation state machine 804 is also used to synchronize the first state to the second link negotiation state machine 704 through the second pin, since the link negotiation state machine in the retimer The way of link negotiation is clearly defined in the PCIe protocol, that is, the protocol clearly defines how to perform link negotiation according to the state of each different physical channel, so the first link negotiation state machine 804 and the second link negotiation state machine 804 The way that the link negotiation state machine 704 is used to perform link negotiation at the jump moment may be: the first link negotiation state machine 804 is used to perform link negotiation according to the first state and the second state at the determined jump moment The second link negotiation state machine 704 is used to carry out link negotiation according to the first state and the second state at the same jump moment, according to the definition of the PCIe protocol, as long as the same jump moment is determined (promptly guaranteeing two The link negotiation state machine works synchronously), the first link negotiation state machine 804 and the second link negotiation state machine 704 can carry out completely consistent link negotiation methods at the same time, so that the two retimers can be merged into one link The purpose of link negotiation.

It should be noted that, in some implementation manners of the present application, the second pin may be one pin, or may be multiple pins, which are not specifically limited here. If the second pin is a pin, take a single-bit pin as an example: the first link negotiation state machine 804 and the second link negotiation state machine 704 time-division multiplex the second pin, such as the first The link negotiation state machine 804 first uses the second pin to transmit information (such as sending the first state to the second link negotiation state machine 704), after the transmission is completed, the second pin is released, and the second link negotiation state The machine 704 uses the second pin to transmit information (such as sending the second state to the first link negotiation state machine 804). As shown in Figure 12, assuming that the pin signal (that is, the signal transmitted through the second pin, such as the first state and the second state) is generated at 1GHz in the retimer and transmitted at 100MHz on the second pin, then The state of each bit is valid for 10ns. In some embodiments of the present application, the pin level may be high by default (or the pin level may be low by default), and when the first retimer controls the pin level to be low, the first The retimer has the right to use this pin, which means that a transmission command starts. For example, a 4bit address can be transmitted first, representing the command type, and then a maximum of 16bit data is sent. When the data transmission is completed, the pin is set to High level, indicating that the transmission command is completed, and the first retimer hands over the right to use the pin to the second retimer. If the second pin is a plurality of pins, then the time-division multiplexing mode may not be used, and an independent synchronization signal may be used at this time. For example, the first link negotiation state machine 804 sends the second pin to The link negotiation state machine 704 transmits a synchronization signal, and the second link negotiation state machine 704 transmits a synchronization signal to the first link negotiation state machine 804 through another pin. Each group of synchronization signals can be a unit signal or a multi-bit signal, specifically There is no limit here.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer obtain the states (such as the first state and the second state) of each physical channel of the other party respectively through the second pin, and the first retimer The timer determines a jump time according to the states of all physical channels in the two retimers, and further synchronizes the jump time to the second retimer. When the jump time is reached, the first retimer The first link negotiation state machine 804 in the timer and the second link negotiation state machine 704 in the second retimer start all link negotiations across the retimers, so that the two retimers are merged into one chain The purpose of link negotiation.

3. How the first retimer and the second retimer process the frequency offset synchronously through the third pin.

The first retimer includes the first deviation processing module 803 and/or the first link negotiation state machine 804, and the second retimer includes the second deviation processing module 703 and/or the second link negotiation state machine In addition to step 704, the first retimer may specifically include a first buffer, and the second retimer may specifically include a second buffer. As shown in FIG. 8 , the first buffer may specifically include a receiving buffer 802 and a sending buffer 805 , and the second buffer may specifically include a receiving buffer 702 and a sending buffer 705 . It should be noted that, in some embodiments of the present application, when the data in each retimer is transmitted to its own internal buffer, the buffer also needs to perform frequency offset processing on the acquired data, that is, to ensure that each The receiving buffer corresponding to the physical channel transmitting data does not overflow (that is, no data is lost), and at the same time, it is necessary to ensure that the sending buffer corresponding to each physical channel that is transmitting data is continuously flowing (that is, no data is lost). The processing method is to ensure that the corresponding receiving buffer does not overflow and the corresponding sending buffer does not flow through the SKP addition and deletion rules (for example, add SKP data in the corresponding receiving buffer according to the preset rules, and add SKP data in the corresponding receiving buffer according to the preset rules. delete the SKP data in the send buffer).

It should be noted that how the buffer obtains SKP data and ensures that the data in the buffer does not overflow or continue to flow according to the SKP addition and deletion rules is existing (that is, how to deal with frequency offset), which will not be described here, and will be implemented in this application. In the example, it focuses on how the first retimer and the second retimer process the frequency deviation synchronously through the third pin. First, the second buffer is used to determine the state of the second SKP data (can be called the fourth state), and synchronize the fourth state to the first buffer through the third pin, similarly, the first buffer is also used for Obtain the state of the first SKP data (which can be called the third state), and then the first buffer is used to determine the SKP addition and deletion rules according to the third state and the fourth state, and is used to further determine through the third pin The SKP addition and deletion rules are synchronized to the second buffer, so that the first buffer and the second buffer are also used to respectively adjust the first transmission data and the second transmission data according to the same SKP addition and deletion rules.

For ease of understanding, the following uses Fig. 8 as an example to describe in detail how to process frequency offset synchronously: in order to ensure that the receiving buffer 802 in the first retimer and the receiving buffer 702 in the second retimer do not overflow, and also To ensure that the receiving buffers in the two retimers process the frequency offset synchronously, then the SKP addition and deletion rule can be that the receiving buffer 802 receives a group of SKP data, and then fixedly deletes a unit of SKP (that is, fixedly deletes an 8-bit SKP data, the agreement in PCIe has definition, do not go into details here), after receiving buffer 802 has determined described SKP addition and deletion rule, just can this SKP addition and deletion rule be synchronized to receiving buffer 702 by the 3rd pin, receiving buffer After the device 702 acquires the addition and deletion rule, it will also perform frequency offset processing synchronously with the receiving buffer 802 according to the addition and deletion rule. Similarly, in order to ensure that the transmission buffer 805 in the first retimer and the transmission buffer 705 in the second retimer are not interrupted, and to ensure that the transmission buffers in the two retimers process the frequency offset synchronously, Then the SKP addition and deletion rules can be that the first retimer and the second retimer monitor the waterline of the sending buffer 805 and the sending buffer 705 respectively, the waterline is divided into two levels, the first level adds a unit of SKP, and the second Add two units of SKP (adding two units of SKP can ensure that the frequency offset defined by the protocol is covered, and ensure that after adding SKP, the sending buffer will be in a non-empty state, so that there is data in the sending buffer, which can achieve continuous flow purpose), and no increase in other cases. After the sending buffer 805 has determined the SKP addition and deletion rules, it can synchronize the SKP addition and deletion rules to the sending buffer 705 through the third pin, and after the sending buffer 705 obtains the addition and deletion rules, it will also match The receiving buffer 805 performs frequency offset processing synchronously.

It should be noted that, in some embodiments of the present application, the second buffer is used to determine the fourth state of the second SKP data, and the step of synchronizing the fourth state to the first buffer through the third pin can be performed by The first buffer is triggered to be executed by a trigger instruction (which may be referred to as a second trigger instruction) sent to the second buffer by the third pin, and the second trigger instruction is used to instruct the second buffer to execute the acquisition of the fourth State and the step of synchronizing the fourth state to the first buffer through the third pin; it may also be that once the second buffer acquires the second SKP data, it automatically determines the fourth state of the second SKP data, and The fourth state is automatically synchronized to the first buffer through the third pin. Specifically, the method of triggering the second buffer to obtain the fourth state and sending the fourth state to the first buffer through the third pin is different. Do limited.

It should also be noted that, in some embodiments of the present application, the above-mentioned second trigger instruction may be the third state of the first SKP data obtained by the first buffer, or may be the third state obtained by the first buffer. A piece of target information is generated immediately thereafter, and the target information is used to instruct the second buffer to acquire the fourth state and send the fourth state to the first buffer. Specifically, the specific form of the second trigger instruction is not limited here.

It should also be noted that, in some embodiments of the present application, similar to the above-mentioned second pin, the third pin may also be one pin or multiple pins, specifically here No limit.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer obtain the status of the SKP data received by the respective buffers (such as the receiving buffer and the sending buffer) respectively through the third pin (such as, the third state and the fourth state), and determine a SKP addition and deletion rule by the first retimer according to the state of the SKP data received by the buffer in the two retimers, and further synchronize the SKP addition and deletion rule to the The second retimer, the first buffer in the first retimer and the second buffer in the second retimer adjust the respective transmission data according to the SKP addition and deletion rules at the same time, so as to achieve two retimers The purpose of combining them into one link for frequency offset processing.

It should be noted that the devices for data synchronization described in the above-mentioned embodiments are all described as including two retimers as an example. In some embodiments of the present application, the devices for data synchronization may also include More than two retimers, so as to achieve the purpose of synchronizing data in multiple retimers, that is, more retimers can be stacked in a similar manner to the above to achieve the purpose of expanding the width of the PCIe link .

In addition, the embodiment of the present application also provides a data synchronization method, as shown in FIG. 13 .

1301. The second retimer acquires a second time point.

Firstly, the second retimer will obtain the second time point when the second transmission data is transmitted to the second deviation processing module in the second retimer.

1302. The second retimer sends the second time point to the first retimer through the first pin.

Afterwards, the second retimer synchronizes the obtained second time point to the first retimer through the first pin.

1303. The first retimer determines the target time point through the first time point and the second time point.

After the first retimer obtains the first time point sent by the second retimer through the first pin, it can determine the target time point according to the first time point and the second time point obtained by itself in advance, wherein the first A time point is a time point when the first transmission data in the first retimer is transmitted to the first deviation processing module in the first retimer.

1304. The first retimer sends the target time point to the second retimer through the first pin.

After the first retimer determines the target time point, it will synchronize the target time point to the second retimer through the first pin. In this way, the target time point exists in both the first retimer and the second retimer.

1305. The second retimer sends the second transmission data at the target time point.

Finally, the second retimer sends the second transmission data at the target time point according to the acquired target time point.

1306. The first retimer sends the first transmission data at the target time point.

Similarly, the first retimer will also send the first transmission data at the target time point.

It should be noted that, in the above-mentioned embodiments of the present application, step 1305 and step 1306 occur simultaneously, that is, the first retimer and the second retimer are both internally transmitted first transmission data at the target time point And the second transmission data is sent, that is, the first retimer and the second retimer align the data transmitted on the respective physical channels at the target time point and then send them out.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer respectively obtain the time point when the data transmitted on each physical channel of the other party is transmitted to the respective internal deviation processing module through the first pin, and the The first retimer determines a target time point according to each time point, and further synchronizes the target time point to the second retimer, and when the target time point is reached, all physical channels across the retimer are started The data alignment operation completes the data alignment on the physical channel in all retimers.

Preferably, in some embodiments of the present application, the second retimer synchronizes the second time point when the second deviation processing module in the second retimer obtains the second transmission data through the first pin to the first Before the re-timer, the method may further include: the first re-timer sends a first trigger instruction to the second re-timer through the first pin, and the first trigger instruction is used to instruct the second re-timer to perform acquisition of the first re-timer. Step two. It can also be that once the second deviation processing module in the second retimer acquires the second transmission data, it automatically determines the second time point when the second transmission data is transmitted to the second deviation processing module, and then the second retimer Automatically synchronize the second time point to the first retimer through the first pin, specifically here to trigger the second retimer to obtain the second time point and send the first time point to the first retimer through the first pin The method of the second time point is not limited.

Preferably, in some embodiments of the present application, the above-mentioned first trigger instruction may be the first time point when the first transmission data acquired by the first retimer is transmitted to the first deviation processing module, or it may be the first time point when the first retimer A target information generated immediately after the timer obtains the first time point, the target information is used to instruct the second retimer to obtain the second time point and send the second time point to the first retimer, specifically here The specific form of the first trigger instruction is not limited.

It should be noted that, in some embodiments of the present application, before the first retimer and the second retimer perform data alignment (that is, before the first retimer obtains the first time point and the second time point according to point before determining the target time point), it is also necessary to send the states of the physical channels used to transmit data to the first link negotiation state machine in the first retimer and the second link in the second retimer respectively. The negotiation state machine is such that the first link negotiation state machine and the second link negotiation state machine perform link negotiation before the first deviation processing module determines the target time point.

Preferably, in some embodiments of the present application, the link negotiation method of the first link negotiation state machine and the second link negotiation state machine may be: the second retimer acquires The second state of the channel (such as which physical channels are in the state of transmitting parallel data streams, which physical channels transmit specific physical data streams, which physical channels transmit what kind of data streams, etc.), and pass the second state through the second The pin is synchronized to the first retimer; after that, the first retimer determines the jump time according to the acquired first state and the second state, and synchronizes the jump time to the second through the second pin The retimer, wherein, the first state is the state of the channel that transmits the first transmission data in the first retimer; finally, the first link negotiation state machine and the second link negotiation state machine perform link negotiate. For example, the first link negotiation state machine may start timing after acquiring the second state, and after the timing reaches a specific duration, the first link negotiation state machine and the second link negotiation state machine simultaneously perform link negotiation.

Preferably, in some embodiments of the present application, the second retimer obtains the second state of the channel used to transmit the second transmission data, and synchronizes the second state to the first retimer through the second pin. Before the timer, the method may further include: the first retimer sends a first state to the second link negotiation state machine through a second pin, and the first state is used to trigger the second retimer to perform acquisition of the second In the step of state, the first state sent to the second link negotiation state machine via the second pin is used to instruct the second link negotiation state machine to perform the step of acquiring the second state.

Preferably, if the first link negotiation state machine synchronizes the first state to the second link negotiation state machine through the second pin, because the link negotiation state machine in the retimer performs link negotiation in the PCIe protocol There are clear definitions in the protocol, that is, the protocol clearly defines how to perform link negotiation according to the state of each different physical channel, so the first link negotiation state machine and the second link negotiation state machine The way of performing link negotiation at the same time may be: the first link negotiation state machine performs link negotiation according to the first state and the second state at the determined jump moment; the second link negotiation state machine also performs the link negotiation at the same jump moment Carry out link negotiation according to the first state and the second state, according to the definition of the PCIe protocol, as long as the same jump moment is determined (that is, to ensure that the two link negotiation state machines work synchronously), the first link negotiation state machine and The second link negotiation state machine can simultaneously perform a completely consistent link negotiation mode, thereby achieving the purpose of merging two retimers into one link for link negotiation.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer obtain the states (such as the first state and the second state) of each physical channel of the other party respectively through the second pin, and the first retimer The timer determines a jump time according to the states of all physical channels in the two retimers, and further synchronizes the jump time to the second retimer. When the jump time is reached, the first retimer The first link negotiation state machine in the timer and the second link negotiation state machine in the second retimer start all link negotiations across retimers, so that two retimers can be merged into one link for The purpose of link negotiation.

It should also be noted that, in some embodiments of the present application, the first retimer and the second retimer also need to perform frequency offset processing on the data flowing through the buffers in each retimer, that is, to ensure that each The receiving buffer corresponding to the physical channel transmitting data does not overflow (that is, no data is lost), and at the same time, it is necessary to ensure that the sending buffer corresponding to each physical channel that is transmitting data is continuously flowing (that is, no data is lost). The processing method is to ensure that the corresponding receiving buffer does not overflow and the corresponding sending buffer does not flow through the SKP addition and deletion rules (for example, add SKP data in the corresponding receiving buffer according to the preset rules, and add SKP data in the corresponding receiving buffer according to the preset rules. delete the SKP data in the send buffer). First, the second retimer acquires the state of the second SKP data in the second buffer in the second retimer (which can be called the fourth state), and synchronizes the fourth state to the first retimer through the third pin. timer, similarly, the first retimer will also obtain the state of the first SKP data (can be referred to as the third state, and this third state is the first SKP data in the first buffer in the first retimer) state), after that, the first retimer determines the SKP addition and deletion rules according to the third state and the fourth state, and further synchronizes the determined SKP addition and deletion rules to the second retimer through the third pin, so that the first The retimer and the second retimer respectively adjust the first transmission data and the second transmission data according to the same SKP addition and deletion rule.

Preferably, in some embodiments of the present application, the fourth state of the second SKP data in the second buffer in the second retimer is determined in the second retimer, and the fourth state is passed through the third pin Before synchronizing to the first retimer, the method may further include: the first retimer may send a second trigger instruction to the second retimer through the third pin, and the second trigger instruction is used to indicate the second The retimer performs the steps of obtaining the fourth state. It can also be that once the second retimer acquires the second SKP data, it automatically determines the fourth state of the second SKP data, and automatically synchronizes the fourth state to the first retimer through the third pin, specifically Here, there is no limitation on the manner of triggering the second retimer to obtain the fourth state and sending the fourth state to the first retimer through the third pin.

Preferably, in some embodiments of the present application, the above-mentioned second trigger instruction may be the third state of the first SKP data obtained by the first retimer, or it may be after the first retimer obtains the third state A target information is generated immediately, and the target information is used to instruct the second retimer to obtain the fourth state and send the fourth state to the first retimer. Specifically, the specific form of the second trigger instruction is not limited here.

Preferably, in some embodiments of the present application, the first buffer may include a first receiving buffer and a first sending buffer; the second buffer may include a second receiving buffer and a second sending buffer.

It should also be noted that the data synchronization method described in the above embodiment includes two retimers as an example. In some embodiments of the present application, the data synchronization method may also include two retimers. The above retimers achieve the purpose of synchronizing data in multiple retimers, that is, more retimers can be stacked in a similar manner to the above to achieve the purpose of expanding the width of the PCIe link.

In the above-mentioned embodiments of the present application, the first retimer and the second retimer obtain the status of the SKP data received by the respective buffers (such as the receiving buffer and the sending buffer) respectively through the third pin (such as, the third state and the fourth state), and determine a SKP addition and deletion rule by the first retimer according to the state of the SKP data received by the buffer in the two retimers, and further synchronize the SKP addition and deletion rule to the The second retimer, the first buffer in the first retimer and the second buffer in the second retimer adjust the respective transmission data according to the SKP addition and deletion rules at the same time, so as to achieve two retimers The purpose of combining them into one link for frequency offset processing.

In the above embodiments, all or part of the implementation may be implemented by hardware, firmware or any combination thereof.

Claims (24)

1. A data synchronization device, characterized in that, comprising: A first retimer and a second retimer, wherein the first retimer includes a first deviation processing module, and the second retimer includes a second deviation processing module; The second deviation processing module is configured to obtain a second time point when the second transmission data is transmitted to the second deviation processing module, and synchronize the second time point to the first deviation through a first pin processing module; The first deviation processing module is configured to determine a target time point according to the acquired first time point and the second time point, and synchronize the target time point to the second time point through the first pin A deviation processing module, wherein the first time point is the time point when the first transmission data is transmitted to the first deviation processing module; The first deviation processing module and the second deviation processing module are further configured to respectively send the first transmission data and the second transmission data at the target time point. 2. The device according to claim 1, wherein the first deviation processing module is also used for: Sending a first trigger instruction to the second deviation processing module through the first pin, where the first trigger instruction is used to instruct the second deviation processing module to execute the step of acquiring the second time point. 3. The device according to claim 2, wherein the first trigger instruction comprises: The first time point acquired by the first deviation processing module. 4. The device according to any one of claims 1-3, characterized in that, The first retimer also includes a first link negotiation state machine, and the second retimer also includes a second link negotiation state machine; The first link negotiation state machine and the second link negotiation state machine are configured to perform link negotiation before the first deviation processing module determines the target time point. 5. The device according to claim 4, characterized in that, The second link negotiation state machine is specifically configured to obtain the second state of the channel used to transmit the second transmission data, and synchronize the second state to the first link through the second pin Negotiation state machine; The first link negotiation state machine is specifically configured to determine a jump time according to the acquired first state and the second state, and synchronize the jump time to the second pin through the second pin. Two link negotiation state machines, wherein the first state is the state of the channel for transmitting the first transmission data in the first retimer; The first link negotiation state machine and the second link negotiation state machine are also used to perform link negotiation at the jump moment. 6. The device according to claim 5, wherein the first link negotiation state machine is further used for: Send the first state to the second link negotiation state machine through the second pin, and the first state is used to trigger the second link negotiation state machine to perform the step of obtaining the second state . 7. The device of claim 6, wherein: The first link negotiation state machine is further configured to perform link negotiation according to the first state and the second state at the jump moment; The second link negotiation state machine is further configured to perform link negotiation according to the first state and the second state at the jump moment. 8. The device according to any one of claims 1-3, characterized in that, The first retimer also includes a first buffer, and the second retimer also includes a second buffer; The second buffer is used to determine the fourth state of the second character code ordered set SKP data, and synchronize the fourth state to the first buffer through the third pin; The first buffer is used to determine the SKP addition and deletion rules according to the third state and the fourth state, and synchronize the SKP addition and deletion rules to the second buffer through the third pin, wherein the The third state is the state of the first SKP data in the first buffer; The first buffer and the second buffer are further configured to respectively adjust the first transmission data and the second transmission data according to the SKP addition and deletion rules. 9. The device according to claim 8, wherein the first buffer is also used for: Sending a second trigger instruction to the second buffer through the third pin, where the second trigger instruction is used to instruct the second register to execute the step of acquiring the fourth state. 10. The device according to claim 9, wherein the second trigger instruction comprises: The third state acquired by the first buffer. 11. The apparatus of claim 8, wherein: The first buffer includes: a first receiving buffer and a first sending buffer; The second buffer includes: a second receiving buffer and a second sending buffer. 12. The device according to any one of claims 1-3, wherein the second retimer comprises: One or more retimers. 13. A method for data synchronization, comprising: The second retimer transmits the second transmission data in the second retimer to the second time point of the second deviation processing module in the second retimer through the first pin to synchronize to the first retiming device; The first retimer determines a target time point according to the obtained first time point and the second time point, and synchronizes the target time point to the second retimer through the first pin , wherein the first time point is the time point when the first transmission data in the first retimer is transmitted to the first deviation processing module in the first retimer; The first deviation processing module and the second deviation processing module respectively send the first transmission data and the second transmission data at the target time point. 14. The method according to claim 13, wherein the second deviation processing module in the second retimer obtains the first value of the second transmission data through the first pin of the second retimer. Before the second time point is synchronized to the first retimer, the method also includes: The first retimer sends a first trigger instruction to the second retimer through the first pin, and the first trigger instruction is used to instruct the second retimer to perform acquisition of the second Momentary steps. 15. The method according to claim 14, wherein the first trigger instruction comprises: The first time point acquired by the first retimer. 16. The method according to any one of claims 13-15, wherein before the first retimer determines the target time point according to the acquired first time point and the second time point, The method also includes: The first link negotiation state machine in the first retimer and the second link negotiation state machine in the second retimer perform link negotiation. 17. The method according to claim 16, wherein the first link negotiation state machine in the first retimer and the second link negotiation state machine in the second retimer perform link Road negotiation includes: The second retimer obtains a second state of a channel used to transmit the second transmission data, and synchronizes the second state to the first retimer through a second pin; The first retimer determines a jump time according to the obtained first state and the second state, and synchronizes the jump time to the second retimer through the second pin, wherein , the first state is the state of the channel for transmitting the first transmission data in the first retimer; The first link negotiation state machine and the second link negotiation state machine perform link negotiation at the jump moment. 18. The method according to claim 17, wherein the second re-timer acquires a second state of a channel for transmitting the second transmission data, and passes the second state through the Before the second pin is synchronized to the first retimer, the method further includes: The first retimer sends the first state to the second link negotiation state machine through the second pin, and the first state is used to trigger the second retimer to perform acquisition of the Steps for the second state. 19. The method according to claim 18, wherein the link negotiation performed by the first link negotiation state machine and the second link negotiation state machine at the jump moment comprises: The first link negotiation state machine performs link negotiation according to the first state and the second state at the jump moment; The second link negotiation state machine performs link negotiation according to the first state and the second state at the jump moment. 20. The method according to any one of claims 13-15, further comprising: The second retimer obtains the fourth state of the second character code SKP data in the second buffer in the second retimer, and synchronizes the fourth state to the first retimer through the third pin timer; The first retimer determines SKP addition and deletion rules according to the obtained third state and the fourth state, and synchronizes the SKP addition and deletion rules to the second retimer through the third pin, wherein , the third state is the state of the first SKP data in the first buffer in the first retimer; The first retimer and the second retimer respectively adjust the first transmission data and the second transmission data according to the SKP addition and deletion rules. 21. The method according to claim 20, characterized in that, the fourth state of the second character code SKP data in the second buffer in the second retimer is determined in the second retimer, and the Before the fourth state is synchronized to the first retimer through the third pin, the method also includes: The first retimer sends a second trigger instruction to the second retimer through the third pin, and the second trigger instruction is used to instruct the second retimer to perform acquisition of the fourth status steps. 22. The method according to claim 21, wherein the second trigger instruction comprises: The third state acquired by the first retimer. 23. The method of claim 20, wherein, The first buffer includes: a first receiving buffer and a first sending buffer; The second buffer includes: a second receiving buffer and a second sending buffer. 24. The method according to any one of claims 13-15, wherein the second retimer comprises: One or more retimers.

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