CN114551263A - Chip or chip module detection method and device - Google Patents

Abstract

The invention provides a method and a device for detecting a chip or a chip module, wherein the method comprises the following steps: determining the physical information of the chip or the chip module and/or determining the design information of the chip or the chip module; comparing the real object information with the design information, and/or verifying the design information; and judging the degree of autonomy and/or the degree of controllability of the chip or the chip module based on the comparison result and/or the verification result.

Description

Method and device for detecting chip or chip module

technical field

The present invention relates to the field of communication technologies, and in particular, to a detection method and device for a chip or a chip module.

Background technique

Chip design is the core and source of the chip industry chain, and its autonomous controllability plays a pivotal role in the autonomous controllability of the entire chip. The evaluation of the degree of autonomy and controllability in the chip design process is mostly graded according to the methods of completely independent design, partial independent design, and complete outsourcing. Forensics are mostly conducted through investigation and review.

The implementation plan of the relevant self-controllable rating is mostly carried out by means of investigation and review. The accuracy of this evaluation method depends on the authenticity, verifiability, completeness of the relevant materials, as well as the experience and level of experts. The degree of objectivity and comprehensiveness cannot be guaranteed.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present invention are expected to provide a detection method and apparatus for a chip or a chip module.

In order to achieve the above-mentioned purpose, the technical scheme of the embodiment of the present invention is realized as follows:

An embodiment of the present invention provides a method for detecting a chip or a chip module, the method comprising:

Determine the physical information of the chip or chip module, and/or determine the design information of the chip or chip module;

comparing the physical information with the design information, and/or verifying the design information;

Based on the comparison result and/or the verification result, the degree of autonomy and/or the degree of controllability of the chip or chip module is determined.

An embodiment of the present invention also provides a detection device for a chip or a chip module, the device comprising:

Information determination module, used to determine the physical information of the chip or chip module, and/or determine the design information of the chip or chip module;

an information processing module, configured to compare the physical information with the design information, and/or verify the design information;

The determination module is used to determine the autonomy and/or controllability of the chip or the chip module based on the comparison result and/or the verification result.

An embodiment of the present invention also provides a detection device for a chip or a chip module, the device includes: a processor and a memory for storing a computer program that can be run on the processor,

Wherein, the processor is configured to execute the steps of the above method when running the computer program.

The method and device for detecting a chip or a chip module provided by the embodiments of the present invention determine the physical information of the chip or the chip module, and/or determine the design information of the chip or the chip module; compare the physical information with the design information , and/or verify the design information; based on the comparison result and/or the verification result, determine the autonomy and/or controllability of the chip or chip module. It can be seen that the embodiments of the present invention provide a simple and objective detection basis for the evaluation of the autonomy and/or controllability of the chip or chip module, and improve the objectiveness of the evaluation of the autonomy and/or controllability of the chip or chip module It can be used as evidence for the authenticity, practicability and comprehensiveness of the chip or chip module's autonomy and/or controllability assessment and forensic materials, and can be used as the chip or chip module's autonomy and/or controllability. Strong support for evaluation.

Description of drawings

1 is a schematic flowchart of a detection method for a chip or a chip module according to an embodiment of the present invention;

2 is a schematic structural diagram of a detection device for a chip or a chip module according to an embodiment of the present invention;

3 is a schematic flowchart of the detection method described in the first embodiment of the present invention (for the sake of clarity, only the numbers of the operations are given in the figure);

Fig. 4 is a schematic flow chart of the detection method according to the second embodiment of the present invention (for the sake of clarity, only the number of each operation is given in the figure. In addition, the and/or relationships in 2.5 cannot be shown one by one in the figure, only the number of the operations is shown in the figure. One case - verify the second design information in clause 1.7 with the third design information in clause 1.8).

Detailed ways

The present invention will be described below with reference to the accompanying drawings and embodiments.

An embodiment of the present invention provides a method for detecting a chip or a chip module. As shown in FIG. 1 , the method includes:

Step 101: Determine the physical information of the chip or the chip module, and/or determine the design information of the chip or the chip module;

Step 102: Compare the physical information with the design information, and/or verify the design information;

Step 103: Based on the comparison result and/or the verification result, determine the degree of autonomy and/or the degree of controllability of the chip or the chip module.

The embodiments of the present invention provide a simple and objective detection basis for evaluating the autonomy and/or controllability of a chip or a chip module, and improve the objectivity, Practical and comprehensive, and can provide evidence for the authenticity of the forensic materials for the evaluation of the autonomy and/or controllability of the chip or chip module, and can be used as the basis for the evaluation of the autonomy and/or controllability of the chip or chip module. Strong support.

In this embodiment of the present invention, the chip includes but is not limited to one or more of the following:

A chip that encapsulates one or more dies (die is also known as die, die);

Unpackaged die.

In this embodiment of the present invention, the chip module includes but is not limited to one or more of the following:

A die within a chip that encapsulates one or more dies;

A functional module (also referred to as a functional unit, unit, etc.) in a die.

(It should be noted that from the perspective of classification, the chip and chip module here are a general term, including but not limited to integrated circuit IC, microsystem MEMS, microelectromechanical system, semiconductor device, discrete device, sensor, actuator, etc. category)

In this embodiment of the present invention, the physical information includes, but is not limited to, one or more of the following (it should be noted that: it can be selected according to the type of comparison required for determining the autonomy and/or controllability of the chip or chip module. The types of physical information make the selection of physical information more targeted):

The physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules, the physical connection relationship includes but is not limited to one or more of the following expressions: The physical connection relationship, the physical diagram describing the connection relationship, the table describing the physical connection relationship, the physical name of the pin describing the physical connection relationship, and the physical connection relationship expressed by the name;

The physical information of the packaging substrate, the physical information includes but is not limited to one or more of the following: physical packaging substrate, physical circuit or circuit diagram of packaging substrate, physical layout or layout of packaging substrate, physical wiring or wiring diagram of packaging substrate, packaging substrate Substrate physical circuit or circuit diagram;

Physical information of the chip or chip module, the physical information includes but is not limited to one or more of the following: physical chip or chip module, physical layout of chip or chip module, physical layout of chip or chip module, physical layout of chip or chip module Wiring or layout and wiring diagrams, physical circuits or circuit diagrams of chips or chip modules;

Wherein, the physical information includes, but is not limited to, one or more of the following physical information: all layers, some layers, and one layer, and the method for selecting layer numbers includes, but is not limited to, one or more of the following: randomly selected, according to rules Select and set; for one layer, the physical information includes but is not limited to one or more of the following physical information: the entire area, multiple partial areas, and a partial area, and the selection method of the area includes but is not limited to the following one or more. One or more: randomly selected, selected according to rules, set.

In this embodiment of the present invention, the method for obtaining the physical information includes but is not limited to one or more of the following:

Directly obtain one or more chips or chip modules to be tested and obtain physical information;

Randomly or according to rules, select one or more chips or chip modules to be tested and obtain physical information;

Obtain physical information directly through one or more of the following methods, including but not limited to: electronic computed tomography CT, X-ray, X-ray, radiation, ultrasound, non-destructive testing (also known as non-destructive testing); (such as: for a packaged the chip, directly obtain the information inside the chip through CT)

Uncover the packaged chip (referred to as uncover) and obtain physical information;

For the physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules is blocked, obtain through one or more methods including but not limited to the following Physical connection relationship: CT, X-ray, X-ray, radiation, ultrasound, nondestructive testing, delamination (also known as delamination, delamination, delamination), flat grinding, grinding, grinding, grinding, polishing, corrosion, engraving Etching, sectioning (also known as chip dissection), dissection, and staining; the situation where the physical connection relationship is blocked includes but is not limited to the physical connection relationship in the flip-chip welded chip being blocked; (for example: for flip-chip The soldered chip is flat-ground to the flip-chip interface, and the physical connection relationship is obtained at this interface)

Separating a chip or chip module from a packaging substrate, and/or separating a chip or chip module from other chips or chip modules, including, but not limited to, one or more of the following: breaking or removing or removing connections wire, corrode, etch, heat, de-layer, flat grind, grind, grind, grind, section, dissect, remove chips;

Obtain physical information of one or more layers by means including but not limited to one or more of the following: direct acquisition, through microscopy (including but not limited to one or more of the following: optical microscopy, electron microscopy) and/or microscopy Imaging instruments and/or CT and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or non-destructive testing Acquisition, delamination, flat grinding, grinding, lapping, grinding, polishing, etching, etching , sectioning, dissecting, staining, disconnecting or removing or removing connecting wires;

By microscope and/or microscopic imaging instrument and/or CT and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or nondestructive examination, in combination with photography or/and image acquisition or/and video recording , or, directly take pictures or/and image acquisition or/and video recording to obtain and record the physical images, images or videos corresponding to the physical information; the physical images, images or videos are one file, or multiple files, or multiple A whole file that is spliced or synthesized from several files;

Obtained by microscope and/or microscopic imaging instrument and/or CT and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or nondestructive testing, combined with visual observation, or direct visual observation Physical information and corresponding physical images and images.

In the embodiment of the present invention, obtaining or selecting a plurality of chips or chip modules to be tested and obtaining physical information, including but not limited to one or more of the following:

In order to obtain multiple samples, perform statistical analysis on the physical information, or/and the comparison between the physical information and the design information, or/and the autonomy and/or controllability of the chip or chip module, and obtain or select multiple samples of the same model. Chip or chip module, obtain the same physical information from each chip or chip module;

In the case of destructive operations or/and only part of the physical information can be obtained from one chip or chip module, obtain or select multiple chips or chip modules of the same type, and obtain from each chip or chip module Different physical information, or simultaneous acquisition of the same and different physical information;

In order to determine the autonomy and/or controllability of a chip composed of multiple chip modules, the multiple chip modules in the chip obtain their respective physical information, and carry out the determination of autonomy and/or controllability. Based on this As a result, the autonomy and/or controllability of the chip is determined.

In this embodiment of the present invention, the design information includes, but is not limited to, one or more of the following (it should be noted that: the type of comparison and/or the degree of control required to determine the autonomy and/or controllability of the chip or chip module may be determined according to the Or verify the type, select the type of design information, so that the selection of design information is more targeted):

The design connection relationship between the chip or chip module and the packaging substrate, and/or the design connection relationship between the chip or chip module and other chips or chip modules, the design connection relationship includes but is not limited to one or more of the following expressions: A design diagram describing the connection relationship, a table describing the design connection relationship, the pin design name describing the design connection relationship, and the design connection relationship expressed by the name; the design information includes but is not limited to one or more of the following design information: For all layers, some layers, and one layer, the selection methods of layer numbers include but are not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the design information includes but is not limited to the following one or more One or more kinds of design information: the entire area, multiple partial areas, one partial area, the selection method of the area includes but is not limited to one or more of the following: random selection, selection according to rules, setting; the design connection relationship Formats include, but are not limited to, one or more formats;

Design information of the packaging substrate, the design information including but not limited to one or more of the following: packaging substrate design circuit or circuit diagram, packaging substrate design layout or layout diagram, packaging substrate design wiring or wiring diagram, packaging substrate design circuit or Circuit diagram; the design information includes but is not limited to one or more of the following design information: all layers, some layers, and one layer, and the selection method of layer numbers includes but is not limited to one or more of the following: random selection, according to rules Select and set; for one of the layers, the design information includes but is not limited to one or more of the following design information: the entire area, multiple partial areas, and a partial area, and the selection method of the area includes but is not limited to the following one One or more: randomly selected, selected according to rules, and set; the format of the design information of the packaging substrate includes but is not limited to one or more formats;

The first design information of the chip or chip module, the first design information includes but is not limited to one or more of the following: chip or chip module design layout, chip or chip module design layout, chip or chip module design layout and wiring or Layout and wiring diagram; the first design information includes but is not limited to one or more of the following design information: all layers, some layers, one layer, and the selection method of layer numbers includes but is not limited to one or more of the following: random Select, select and set according to the rules; for one layer, the first design information includes but is not limited to one or more of the following design information: the entire area, multiple partial areas, a partial area, and the selection method of the area Including but not limited to one or more of the following: randomly selected, selected according to rules, and set; the first design information used for comparison is all or part of the design information in the first design information; used for The first design information for verification is all or part of the design information in the first design information; the first design information for comparison and the first design information for verification are the same or different designs Information (for example, it is determined that the first design information is a combination of all layer design information and part of layer or one layer design information, and part layer or one layer design information is a part of all layer design information; when the physical information of the chip or chip module is When a part of the layer or one layer of physical information is used, the first design information used for comparison is the design information of a part of the layer or one layer corresponding to the physical information; when the second design information is the second design information of the entire chip, The first design information used for verification is all layer design information, which is verified with the second design information); the formats of the first design information include but are not limited to one or more formats; the first design information used for comparison The design information format and the first design information format used for verification are the same or different formats;

Second design information of the chip or chip module, the second design information includes but is not limited to the schematic diagram and/or netlist of the chip or chip module, the schematic diagram and/or netlist includes but is not limited to one of the following or Various: schematic diagram, netlist corresponding to the schematic diagram, transistor-level netlist (it should be noted that transistor-level netlist refers to the description of the transistor level, in various forms, such as cdl netlist, scs netlist , spice netlist, etc.), the gate-level netlist for the final design of the digital chip or digital chip module, the gate-level netlist corresponding to the first design information of the digital chip or digital chip module; the second design information includes but is not limited to all or part of the design information; the second design information used for verification with the first design information is all or part of the design information in the second design information; the second design information used for verification with the third design information The design information is all or part of the design information in the second design information; the second design information used for verification with the fourth design information is all or part of the design information in the second design information ; The second design information used for verification with the first design information, the second design information used for verification with the third design information, and the second design information used for verification with the fourth design information, between any two are the same or different design information; the formats of the second design information include but are not limited to one or more formats; the format of the second design information used for verification with the first design information, The second design information format for verification and the second design information format for verification with the fourth design information are the same or different formats;

The third design information of the chip or chip module, the third design information includes but is not limited to the gate-level netlist formed by the register transfer level RTL code synthesis of the digital chip or the digital chip module; the third design information includes but is not limited to All or part of the design information; the third design information used for verification with the second design information is all or part of the design information in the third design information; the third design information used for verification with the fourth design information The third design information is all or part of the design information in the third design information; the third design information used for verification with the second design information, and the third design information used for verification with the fourth design information, are the same or different design information; the format of the third design information includes but is not limited to one or more formats; the third design information format used for verification with the second design information, and the format used for The third design information format for information verification, which is the same or a different format;

The fourth design information of the chip or chip module, the fourth design information includes but is not limited to the RTL code of the digital chip or the digital chip module; the fourth design information includes but is not limited to all or part of the design information; The fourth design information to be verified with the second design information is all or part of the design information in the fourth design information; the fourth design information to be verified with the third design information is the fourth design information All or part of the design information in the information; the fourth design information used for verification with the second design information and the fourth design information used for verification with the third design information are the same or different design information; The format of the fourth design information includes, but is not limited to, one or more formats; the fourth design information format used for verification with the second design information, and the fourth design information format used for verification with the third design information, are the same or a different format.

In this embodiment of the present invention, the comparison of the physical information with the design information includes but is not limited to one or more of the following:

Compare the physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules with the corresponding design connection relationship to check whether the two are consistent;

Compare the physical information of the packaging substrate with the design information of the corresponding packaging substrate to check whether the two are consistent;

Compare the physical information of the chip or chip module with the first design information of the corresponding chip or chip module, and check whether the two are consistent;

Described comparison includes but not limited to following one or more comparisons: all layers, some layers, one layer, the selection method of layer number includes but not limited to following one or more: randomly select, select according to rules, Setting; for one of the layers, the comparison includes but is not limited to the comparison of one or more of the following: the entire area, a plurality of partial areas, a partial area, and the selection method of the area includes but is not limited to one of the following or Various: random selection, selection according to rules, setting.

In an embodiment of the present invention, before the comparing the physical information with the design information, the method further includes:

Confirm the accuracy of the obtained design information.

In the embodiment of the present invention, the comparison method includes but is not limited to one or more of the following: automatic comparison by a detection device, manual comparison;

When the comparison method is automatic comparison by the detection device, it is necessary to judge whether the format of the physical information is a format that the detection device can recognize and/or use; when the format of the physical information is not recognized and/or used by the detection device. or the format used, the format of the physical information needs to be adjusted to a format that can be recognized and/or used by the detection device; the format of the physical information needs to be adjusted to a format that the detection device can recognize and/or use. methods, including but not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table describing the physical connection relationship;

When the comparison method is automatic comparison by the detection device, it is necessary to judge whether the format of the design information is a format that the detection device can recognize and/or use; when the format of the design information is not recognized and/or used by the detection device. or the format used, the format of the design information needs to be adjusted to a format that can be recognized and/or used by the detection device; the format of the design information needs to be adjusted to a format that can be recognized and/or used by the detection device. method, including but not limited to one or more of the following: transforming design information into design images, transforming design connection relationships into tables describing design connection relationships; the design images include but are not limited to saving design information as or/or and images converted into or/and recorded in image format;

The method for judging whether the format of the physical information and/or the design information is a format that the detection device can recognize and/or use includes, but is not limited to one or more of the following: human judgment;

The method for adjusting the format of the physical information and/or the design information to a format that can be recognized and/or used by the detection device includes, but is not limited to, one or more of the following: automatic adjustment by the detection device; Manual adjustment.

In the embodiment of the present invention, when the physical information is compared with the design information, the corresponding relationship between the physical information and the design information includes but is not limited to one or more of the following:

Correspondence of the same layer;

Correspondence of the same area;

Correspondence of the same position;

The corresponding relationship of the same position scale, the corresponding relationship of the same position scale includes but is not limited to one or more of the following: the position in the physical information and/or the physical image, and the position in the entire physical information and/or the physical image. The ratio of the distance between the points is the same as the ratio of the position in the design information and/or the design image, and the ratio of the distance between the points in the entire design information and/or the design image, then the physical information and/or Or the position of the physical image, and the design information and/or the position of the design image are in a corresponding relationship; the position in the physical information and/or the physical image, and the position in the design information and/or the design image, are After the information and/or the entire physical image and/or the entire design information and/or the entire design image are proportionally scaled, when the entire physical information and/or the entire physical image coincide with the entire design information and/or the entire design image, the positions will also coincide , then the physical information and/or the physical image position, and the design information and/or the design image position are in a corresponding relationship;

Correspondence of the same pin name.

In the embodiment of the present invention, when comparing the physical information or the physical image with the design information or the design image, the method further includes: splitting the physical information or the physical image and the corresponding design information or design image into one or multiple sections, the section of physical information or physical image, and the section of design information or design image maintain a corresponding relationship, carry out comparisons for each section separately, and analyze the results of this comparison based on the comparison results of each section;

Among them, the situation of splitting into one or more sections includes, but is not limited to, one or more of the following: physical information or physical images, and the comparison content with design information or design images are concentrated in one or more local areas, according to The concentrated area is divided into one or more sections; the physical information or physical images, and the content of the comparison with the design information or design images, the size of the graphics in different areas is greatly different, according to different graphic sizes or according to different size ranges, split it into one or more sections;

Among them, after splitting into plates, if there is no required comparison content in some plates, the comparison of this plate is omitted or not omitted, and when the comparison of this plate is omitted, the comprehensive analysis of the comparison results of each plate When the result of the second comparison is not included in this section (for example, the physical information or physical image, the comparison content with the design information or design image is concentrated in one or more local areas, and it is divided into two parts according to the concentrated area. For one or more sections, the part outside the concentrated local area has no comparison content, then this part of the section can be omitted from the comparison, and this part of the section will not be considered when analyzing the comparison results).

In the embodiment of the present invention, the physical information or the physical image is compared with the design information or the design image, and/or the physical information plate or the physical image plate is compared with the design information plate or the design image plate, and the comparison is performed. The comparison methods of comparison include but are not limited to one or more of the following: overall comparison, detailed comparison, sampling comparison;

The comparison content of the comparison includes but is not limited to one or more of the following: connection relationship, geometric shape, geometric shape feature;

The comparison fineness of the comparison is expressed by granularity, and the alignment fineness is related to the comparison method, method, content and purpose, and the granularity includes but is not limited to the accuracy of the comparison content. , the minimum limit of the granularity includes but is not limited to one or more of the following: the smallest graphic in the corresponding information and/or image, the smallest size in the corresponding information and/or image, the smallest in the corresponding information and/or image Area, according to the graphics set according to the corresponding information and/or image, according to the size set according to the corresponding information and/or image, according to the area set according to the corresponding information and/or image.

In the embodiment of the present invention, the physical information or the physical image is compared with the design information or the design image, and/or the physical information plate or the physical image plate is compared with the design information plate or the design image plate. Including but not limited to one or more of the following:

Adjust the resolution and/or resolution of the physical image and/or the design image and/or the physical image and/or the design image block for the physical image and/or the design image and/or the physical image block and/or the design image block to be compared or the number of pixels, on the basis of the adjustment results, compare the physical image and the design image, and/or the physical image plate and the design image plate;

When the comparison method is automatic comparison by the detection device, for the granularity of this planned comparison, according to the resolution of the physical image and/or the design image and/or the physical image block and/or the design image block, and / or the number of pixels contained in the physical image and/or design image and/or physical image plate and/or design image plate for the granularity of this planned comparison, as well as the comparison ability of the detection device, adjust the physical image and / or The resolution and/or the number of pixels of the design image and/or the physical image block and/or the design image block, based on the adjustment results, for the physical image and the design image, and/or the physical image block and the design image block, carry out Comparison;

The comparison capability of the detection device includes, but is not limited to: the minimum required by the detection device to complete the comparison under the granularity, for the actual image and/or the design image and/or the actual image plate and/or the design image plate respectively. resolution, and/or the minimum number of pixels to be included in the granularity;

The adjustment methods include, but are not limited to: for the granularity of this planned comparison, on the premise of ensuring the accuracy of the comparison, reducing the size of the physical image and/or design image and/or the physical image block and/or the design image block. Resolution and/or number of pixels to reduce the resolution of the physical image and/or design image and/or physical image tile and/or design image tile, and/or physical image and/or design image and/or physical image tile And/or the number of pixels included in the granularity in the design image plate is reduced, and is greater than or equal to the comparison capability of the detection device.

In the embodiment of the present invention, the overall comparison method is adopted, including but not limited to one or more of the following:

For the entire said physical information or physical image, compared with design information or design image, and/or for the entire said physical information block or physical image block, and design information block or design image block comparison;

The overall alignment includes but is not limited to one or more of the following: overall fine alignment, overall rough alignment;

During the overall fine comparison, the particle size of the comparison has reached the minimum limit;

In the overall rough comparison, the particle size of the comparison is greater than the minimum limit, and the comparison content is embodied in one or more of the following: connection relationship, chip area, chip outline, package substrate area, package substrate Outline, graphic overview, graphic distribution characteristics, module structure;

The applicable situations for the overall fine comparison of the entire physical information or physical image and design information or design images include, but are not limited to, one or more of the following: the time required to complete the overall fine comparison is less than or equal to the first preset time. Set a threshold; the number of pixels of the physical image is less than or equal to a second preset threshold; the number of pixels of the design image is less than or equal to a third preset threshold; the resolution of the physical image is less than or equal to a fourth preset threshold; the The resolution of the design image is less than or equal to the fifth preset threshold; the area of the physical information and/or the physical image and/or the design information and/or the design image is less than or equal to the sixth preset threshold; the physical information and/or the physical The area of the smallest graphic in the image and/or the design information and/or the design image is greater than or equal to a seventh preset threshold;

The applicable situations for the overall fine comparison of the entire physical information plate or the physical image plate and the design information plate or the design image plate include but are not limited to one or more of the following: required to complete the overall fine comparison of the plate The time is less than or equal to the eighth preset threshold; the number of pixels of the physical image block is less than or equal to the ninth preset threshold; the number of pixels of the design image block is less than or equal to the tenth preset threshold; the resolution of the physical image block is less than or equal to equal to the eleventh preset threshold; the resolution of the design image block is less than or equal to the twelfth preset threshold; the area of the physical information block and/or the physical image block and/or the design information block and/or the design image block less than or equal to the thirteenth preset threshold; the area of the smallest graphic in the physical information block and/or the physical image block and/or the design information block and/or the design image block is greater than or equal to the fourteenth preset threshold;

Applicable situations for the overall rough comparison of the entire physical information or physical image and design information or design images include but are not limited to one or more of the following: the time required to complete the overall fine comparison is greater than or equal to the first Fifteen preset thresholds; the number of pixels of the physical image is greater than or equal to the sixteenth preset threshold; the number of pixels of the design image is greater than or equal to the seventeenth preset threshold; the resolution of the physical image is greater than or equal to the eighteenth preset threshold preset threshold; the resolution of the design image is greater than or equal to the nineteenth preset threshold; the area of the physical information and/or the physical image and/or the design information and/or the design image is greater than or equal to the twentieth preset threshold; The area of the smallest graphic in the physical information and/or the physical image and/or the design information and/or the design image is less than or equal to the twenty-first preset threshold; the overall rough comparison is combined with the other comparison methods;

Applicable situations for the overall rough comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include but are not limited to one or more of the following: required to complete the overall fine comparison of the plate The time is greater than or equal to the twenty-second preset threshold; the number of pixels of the physical image block is greater than or equal to the twenty-third preset threshold; the number of pixels of the design image block is greater than or equal to the twenty-fourth preset threshold; The resolution of the physical image block is greater than or equal to the twenty-fifth preset threshold; the resolution of the design image block is greater than or equal to the twenty-sixth preset threshold; the physical information block and/or the physical image block and/or the design The area of the information panel and/or the design image panel is greater than or equal to the twenty-seventh preset threshold; the area of the smallest graphic in the physical information panel and/or the physical image panel and/or the design information panel and/or the design image panel is less than or equal to Equal to the twenty-eighth preset threshold; the overall rough alignment is combined with the other alignment methods.

In this embodiment of the present invention, the detailed comparison method is adopted, including but not limited to one or more of the following:

For the comparison of the physical information or physical image, and design information or design image, and/or the physical information plate or physical image plate, and the design information plate or design image plate comparison, for including but not limited to the following One or more areas, gradually reduce the comparison area and/or reduce the particle size, and carry out one or more comparisons: areas that fail the overall comparison, areas that are of interest or considered critical after the overall comparison is passed, Realize complex areas, functionally critical areas, and entire areas;

When performing one or more comparisons, the refinement limit is that the comparison area has been reduced to the smallest graphic and/or the smallest size in the corresponding information and/or image and/or information panel and/or image panel, and/or The particle size has reached the minimum limit, and the refinement comparison needs to reach the refinement limit or does not need to reach the refinement limit.

In this embodiment of the present invention, the sampling comparison method is adopted, including but not limited to one or more of the following:

Calculation and/or setting for the comparison of the physical information or physical image with the design information or the design image, and/or the comparison of the physical information plate or the physical image plate with the design information plate or the design image plate Area available for comparison (i.e. this area can be obtained by calculation, and/or set);

According to the area that can be used for comparison, select several sampling blocks from the physical information or physical image or physical information plate or physical image plate, and the sum of the areas of the several sampling blocks shall not exceed the area that can be used for comparison;

According to the area available for comparison, select several sampling blocks from the design information or design image or design information plate or design image plate, and the sum of the areas of the several sampling blocks shall not exceed the area available for comparison;

The sampling block selected from the physical information or the physical image or the physical information block or the physical image block maintains a corresponding relationship with the sampling block selected from the design information or the design image or the design information block or the design image block;

The selection methods of sampling blocks include, but are not limited to, one or more of the following: random sampling, sampling according to rules, allocation of the number of sampling blocks proportional to graphics density and/or complexity, and allocation of sampling blocks proportional to graphics density and/or complexity. area, set;

Compare the physical information or the physical image or the sampling blocks in the physical information plate or the physical image plate with the corresponding design information or design image or the sampling block in the design information plate or the design image plate;

Synthesize the comparison results of each sampling block to analyze the results of this sampling comparison;

The fine limit of the sampling comparison is that the granularity has reached the minimum limit, and the sampling comparison needs to reach the fine limit or does not need to reach the fine limit.

In this embodiment of the present invention, the area that can be used for comparison is calculated, including but not limited to one or more of the following:

For physical information or physical image or physical information plate or physical image plate, and design information or design image or design information plate or design image plate, according to the time required to complete the comparison per unit area, and the expected completion time of this comparison , calculate the area available for comparison;

The calculation method includes but is not limited to: area available for comparison = unit area * expected completion time of this comparison/time required to complete unit area comparison.

In this embodiment of the present invention, the method for obtaining the minimum shape and/or the minimum size and/or the minimum area includes, but is not limited to, one or more of the following:

Obtain the minimum size from the corresponding design information and/or physical information and/or design information block and/or physical information block, and the acquisition method includes but is not limited to acquiring one or more of the following information: minimum line width, feature Size, process, gate length, channel length;

Further analysis based on minimum size to obtain minimum figure and/or minimum area;

Identify the smallest graphic and/or smallest size and/or smallest area in the corresponding design image and/or physical image and/or design image tile and/or physical image tile.

In the embodiment of the present invention, under one or more circumstances including but not limited to the following, the method further includes adjusting the corresponding resolution and/or the number of pixels and then comparing:

Before starting the image comparison and/or after splitting the panels and/or during the overall comparison, adjust the resolution and/or the number of pixels of the physical image and/or design image and/or the physical image panel and/or the design image panel. Comparison;

Refinement and comparison After reducing the comparison area and/or reducing the granularity, for the area after the reduction and/or reducing the granularity, adjust the resolution and/or the number of pixels of the corresponding image before comparing;

After the sampling blocks are selected, for each sampling block, the resolution and/or the number of pixels of the corresponding images are adjusted and then compared.

In an embodiment of the present invention, the method further includes:

Adjust the comparison implementation algorithm for one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods, different comparison methods, and different work stages in the comparison.

In this embodiment of the present invention, the verification of the design information includes but is not limited to one or more of the following:

Verify the first design information of the chip or chip module and the corresponding second design information, and the verification method includes but is not limited to LVS inspection or verification;

Verifying the second design information of the chip or chip module and the corresponding third design information, and/or verifying the second design information of the chip or chip module and the corresponding fourth design information, the verification methods include but are not limited to formal verify;

The third design information of the chip or chip module is verified with the corresponding fourth design information, and the verification method includes but is not limited to formal verification.

In an embodiment of the present invention, before the verification of the design information, the method further includes:

Confirm the accuracy of the obtained design information.

In this embodiment of the present invention, the method for confirming the accuracy of the acquired design information includes but is not limited to one or more of the following:

For the acquired first design information for comparison and the acquired first design information for verification, it is confirmed that the design information of the overlapping part and/or the repeated part is the same and/or consistent; A method for the design information of the overlapping part and/or the repeated part to be the same and/or consistent, including but not limited to one or more of the following: combining the acquired first design information format for comparison with the acquired The format of the first design information for verification is unified, image comparison is performed for overlapping parts and/or repeating parts, graphic comparison is performed for overlapping parts and/or repeating parts, and similarity is performed for overlapping parts and/or repeating parts comparison, determine that the similarity is greater than or equal to the twenty-ninth preset threshold, and determine all or part of one of the acquired first design information for comparison and the acquired first design information for verification The information is obtained by extracting all or part of the information from another type of information, and/or all or part of the information of one type of information is obtained by extracting all or part of the information from another information format after conversion;

Unify the acquired first design information format for comparison and the acquired first design information format for verification; the method for unifying the two formats includes but is not limited to one or more of the following: One of the two formats is converted into another format, and both formats are converted into a third format; the third format refers to the obtained first design information format for comparison, obtained a format other than the first design information format used for verification;

For the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , for any and/or set one or more pairwise combinations within the combination, and/or between the three, confirm that the design information of the overlapping part and/or the repeated part is the same, and/or Keeping consistent; the method for confirming that the design information of the overlapping parts and/or repeating parts is the same and/or consistent, including but not limited to one or more of the following: unifying the format of the design information; for overlapping parts Perform image comparison with and/or repeated parts; perform graphic comparison with respect to overlapping parts and/or repeated parts; perform similarity comparison with respect to overlapping parts and/or repeated parts; determine that the similarity is greater than or equal to the thirtieth preset threshold ; Determine the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , in which all or part of one or more of the information is obtained by extracting all or part of the other Obtained by extracting all or part of the information from one or more information formats after conversion; the application scenarios of the method for confirming that the design information of the overlapping part and/or the repeated part is the same and/or consistent, including but not limited to : For the analog-digital hybrid chip, confirm that the gate-level netlist of the digital chip module in it is the same or consistent with the digital chip module part in the transistor-level netlist of the chip after the format is converted to the transistor-level netlist;

For the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , for any and/or set one or more pairwise combinations of the three, and/or between the three, unify the format of the design information; the method for unifying the format of the design information includes: However, it is not limited to one or more of the following: converting one format of the two formats into the other format for the combination of two-two combinations internally, and converting both formats for the internal-combination of two-two combinations The third format refers to the format other than the design information format in the combination, and the format is unified into one of the three formats for the combination of the three. For the three formats, the three formats are converted into the fourth format, and the fourth format for the three refers to formats other than the design information format among the three;

For the acquired third design information for verification with the second design information, and the acquired third design information for verification with the fourth design information, confirm that the overlapping and/or repeated design information therein is the same, and / or keep it consistent; the method for confirming that the design information of the overlapping portion and/or the repeating portion is the same and/or consistent, including but not limited to one or more of the following: The third design information format for design information verification is unified with the acquired third design information format used for verification with the fourth design information, and image comparison is performed for the overlapping portion and/or the repeated portion, and for the overlapping portion and/or Perform graphic comparison on the repeated part, perform similarity comparison on the overlapping part and/or the repeated part, determine that the similarity is greater than or equal to the thirty-first preset threshold, and determine the acquired third design for verification with the second design information Information and the obtained third design information for verification with the fourth design information, all or part of the information of one type of information is obtained by extracting all or part of the information from another type of information, and/or one of the information All or part of the information is obtained by extracting all or part of the information from another information format after conversion;

Unify the acquired third design information format for verification with the second design information and the acquired third design information format for verification with the fourth design information; the method for unifying the formats of the two includes but not It is limited to one or more of the following: converting one of the two formats into another format, and converting both formats into a third format; the third format refers to the The third design information format verified by the second design information, and the acquired format other than the third design information format verified by the fourth design information;

For the acquired fourth design information for verification with the second design information, and the acquired fourth design information for verification with the third design information, confirm that the overlapping part and/or the repeated part design information therein is the same, and / or keep it consistent; the method for confirming that the design information of the overlapping portion and/or the repeating portion is the same and/or consistent, including but not limited to one or more of the following: The fourth design information format for verification of the design information is unified with the obtained fourth design information format for verification with the third design information, and image comparison is performed for the overlapping portion and/or the repeated portion, and the overlapping portion and/or Perform graphic comparison on the repeated part, perform similarity comparison on the overlapping part and/or the repeated part, determine that the similarity is greater than or equal to the thirty-second preset threshold, and determine the acquired fourth design for verification with the second design information Information and the obtained fourth design information for verification with the third design information, all or part of the information of one type of information is obtained by extracting all or part of the information from another type of information, and/or one of the information All or part of the information is obtained by extracting all or part of the information from another information format after conversion;

Unify the acquired fourth design information format for verification with the second design information and the acquired fourth design information format for verification with the third design information; the method for unifying the formats of the two includes but not It is limited to one or more of the following: converting one of the two formats into another format, and converting both formats into a third format; the third format refers to the The fourth design information format verified by the second design information, and the acquired format other than the fourth design information format verified by the third design information;

Confirm that the gate-level netlist in the acquired second design information is a back-end netlist and/or a non-front-end netlist;

Confirm that the gate-level netlist in the acquired third design information is a front-end netlist and/or a non-back-end netlist;

The gate-level netlist in the confirmed second design information obtained is a back-end netlist and/or a non-front-end netlist, and/or the gate-level netlist in the third design information obtained is confirmed to be a front-end netlist, and/or non-backend netlist methods, including but not limited to one or more of the following: keyword retrieval; gate-level netlists in the acquired second design information and gates in the acquired third design information level netlist, compare the similarity, and/or determine that the similarity is less than or equal to the thirty-third preset threshold;

Confirm that the acquired RTL code is a register transfer level description and/or a non-other level description, and the other level description includes but is not limited to a gate level description;

The accuracy of the acquired design information is confirmed by the file suffix of the acquired design information.

In the embodiment of the present invention, when the design information is verified, the corresponding relationship between the design information includes but is not limited to one or more of the following: the corresponding relationship of the same module, the corresponding relationship of the same unit, the same The corresponding relationship of functions, the corresponding relationship of the same logic, the corresponding relationship of the same connection.

In the embodiment of the present invention, when the verification is carried out, the settings or/and conditions of the verification are confirmed, and the method for confirming the settings or/and conditions of the verification includes but is not limited to one or more of the following:

When the verification is LVS verification, the settings or/and conditions of the LVS verification are confirmed by analyzing the design information targeted for the LVS verification, or/and viewing the design description corresponding to the design information targeted by the LVS verification; /and conditions include, but are not limited to, one or more of the following: top-level design, top-level unit, top-level logic, top-level module;

When the verification is formal verification, confirm the settings or/and conditions of the formal verification by analyzing the design information targeted by the formal verification, or/and viewing the design description corresponding to the design information targeted by the formal verification; /and conditions include, but are not limited to, one or more of the following: top-level design, top-level unit, top-level logic, top-level module, and constant settings;

The top-level design and/or top-level cell and/or top-level logic and/or top-level module in the verification settings or/and conditions, related to the design information for which verification is aimed, is all or part of the design information of the chip or chip module; all The top-level design and/or top-level unit and/or top-level logic and/or top-level module of the verification setup are the application scenarios of the design information of the part of the chip, including but not limited to: for analog-digital hybrid chips, the formal verification setup or The top-level design and/or top-level unit and/or top-level logic and/or top-level module in the/and condition are digital chip modules in an analog-digital hybrid chip.

In the embodiment of the present invention, when the verification is carried out, one or more results or/and reports of the verification are comprehensively analyzed to determine whether the verification has passed; when the verification is formal verification, the verification result or And/and reports include, but are not limited to, one or more of the following: comparison point matching check results, verification results, verification reports.

In the embodiment of the present invention, the degree of autonomy and/or controllability of the chip or chip module is determined based on the comparison result and/or the verification result, including but not limited to one or more of the following:

According to the characteristics of the chip or chip module, determine the type of comparison and/or verification required to determine the degree of autonomy and/or controllability of the chip or chip module;

For the required comparison types and/or verification types, according to the degree of difficulty and/or criticality of the links represented by the various types, assign the corresponding comparisons and/or verification types score;

For each of the required comparisons and/or verifications, when actually carried out and passed, the chip or chip module obtains a score corresponding to the comparison and/or verification;

For each of the required comparisons and/or verifications, when the actual implementation fails or the actual implementation fails, the chip or chip module does not obtain the corresponding score for the comparison and/or verification;

Combining the results of various comparisons and/or verifications actually carried out, in the scores corresponding to various comparisons and/or verifications obtained by the chip or chip module, sort out invalid scores;

Among the scores corresponding to various comparisons and/or verifications obtained by the chip or chip module, the invalid scores are removed, the remaining scores are valid scores, the valid scores are summed, and the summation result is used as the final score of the chip or chip module;

According to the final score of the chip or chip module, the degree of autonomy and/or controllability of the chip or chip module is determined.

In the embodiment of the present invention, according to the results of various comparisons and/or verifications actually carried out, among the scores corresponding to various comparisons and/or verifications obtained by the chip or chip module, invalid points are sorted out. Values, including but not limited to one or more of the following:

When the comparison between the physical information of the chip or chip module and the corresponding first design information fails, the chip or chip module obtains the actual verification information for each of the required verifications when it is actually carried out and passed. The corresponding scores are all invalid scores;

When the verification of the first design information of the chip or chip module and the corresponding second design information fails, the verification of the second design information of the chip or chip module and the corresponding third design information is actually carried out and passed. The corresponding score obtained at the time is invalid score;

When the verification of the first design information of the chip or chip module and the corresponding second design information fails, the verification of the second design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed. The corresponding score obtained at the time is invalid score;

When the verification of the first design information of the chip or chip module and the corresponding second design information fails, the verification of the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed. The corresponding score obtained at the time is invalid score;

When the verification of the second design information of the chip or chip module and the corresponding third design information fails, and the verification of the second design information of the chip or chip module and the corresponding fourth design information fails, the The corresponding score obtained when the verification of the third design information of the chip or the chip module and the corresponding fourth design information is actually carried out and passed is an invalid score.

In this embodiment of the present invention, for a chip composed of one or more chip modules, the determination of the autonomy and/or controllability of the chip includes but is not limited to one or more of the following:

For each chip module in the chip, a corresponding weight is assigned according to the difficulty and/or criticality of each chip module. The score of the chip is the weighted sum of the scores of each chip module, based on the weighted sum. Determine the autonomy and/or controllability of the chip;

When assigning corresponding weights, it is necessary to ensure that when a chip with a given function is composed of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and/or degree of control are the same; The implementation methods with the same scores corresponding to the same degree of autonomy and/or the same degree of controllability include but are not limited to one or more of the following: normalization of weight distribution, under different schemes, the predetermined function of the chip. The sum of the weights of each chip module is the same, and when it is determined that each chip module has the highest degree of autonomy and/or controllability, the score of each chip module is the same, and the full score of each chip module is the same;

For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and/or repeat, and the sum of the physical information of each chip module is the physical information of the entire chip;

For each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and/or repeat, and the sum of the design information of each chip module is the design information of the entire chip;

The physical information of the respective chip modules maintains a corresponding relationship with the design information.

(One of the above-mentioned purposes of ensuring that the physical information of each chip module does not overlap and/or repeat, and/or ensuring that the design information of each chip module does not overlap and/or repeat is to avoid the same comparison content and/or Or the verification content is repeatedly scored. For example: in the case of including but not limited to one or more of the following, when determining the physical information of each chip module and/or determining the design information of each chip module, ensure that the physical object of each chip module is determined. Non-overlapping and/or non-repetitive information, and/or ensuring that the design information of each chip module is non-overlapping and/or non-repetitive: When multiple chip modules are placed on the same packaging substrate, the physical information for the packaging substrate is the same as the corresponding one. The design information is divided according to its relationship with each chip module to ensure that the physical information of the packaging substrates allocated to each chip module does not overlap, and the sum of the physical information is exactly the same as all physical information of the packaging substrate, ensuring that each chip module is allocated to the The design information of the package substrate does not overlap, and its sum is exactly all the design information of the package substrate; when there are connections between multiple chip modules, according to the physical connection relationship between the chip modules and the corresponding design connection relationship, according to its Divide the relationship with each chip module to ensure that the physical connection relationship between the chip modules assigned to each chip module does not overlap, and the sum of the physical connection relationships between the chip modules is exactly the same, to ensure that each chip module is connected. The design connection relationships between the assigned chip modules do not overlap, and their sum is exactly all the design connection relationships between the chip modules.)

In the embodiment of the present invention, when there are chip modules of the same type in the chip modules that make up the chip, the chip modules of the same type are regarded as a whole chip module for detection, and a score is calculated and assigned a Weight; the processing method for treating the chip modules of the same model as an overall chip module for detection includes, but is not limited to, one or more of the following:

Determining the sum of the physical information of the chip modules of the same model as the physical information of an integral chip module of the detection, and determining the sum of the design information of the chip modules of the same model as the detection of an integral chip module design information, and calculate the score for an overall chip module of the detection;

From the chip modules of the same model, randomly or according to a rule, select a chip module, and use its score as the score of an overall chip module of the detection;

For the chip modules of the same model, select all or part of the number of chip modules, respectively calculate the scores of the selected chip modules, and use the average value of the scores of the selected chip modules as an overall chip module for the detection. 's score.

In this embodiment of the present invention, the applicable scope of the method for determining the autonomy and/or controllability of a chip composed of one or more chip modules includes but is not limited to one or more of the following:

An analog-digital hybrid chip composed of a digital chip module and an analog chip module;

a multi-chip module MCM (ie, one of the chips) formed by packaging a plurality of bare chips (ie, one of the chip modules) together;

RF front-end module.

In order to implement the above method embodiments, the embodiments of the present invention further provide a detection device for a chip or a chip module. As shown in FIG. 2 , the device includes:

an information determination module 201, configured to determine the physical information of the chip or the chip module, and/or determine the design information of the chip or the chip module;

an information processing module 202, configured to compare the physical information with the design information, and/or verify the design information;

The determination module 203 is configured to determine the autonomy and/or controllability of the chip or the chip module based on the comparison result and/or the verification result.

In this embodiment of the present invention, the chip includes but is not limited to one or more of the following:

A chip that encapsulates one or more dies;

Unpackaged die.

In this embodiment of the present invention, the chip module includes but is not limited to one or more of the following:

A die within a chip that encapsulates one or more dies;

Functional modules in a die.

In this embodiment of the present invention, the physical information includes but is not limited to one or more of the following:

The physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules, the physical connection relationship includes but is not limited to one or more of the following expressions: The physical connection relationship, the physical diagram describing the connection relationship, the table describing the physical connection relationship, the physical name of the pin describing the physical connection relationship, and the physical connection relationship expressed by the name;

Physical information of the packaging substrate, the physical information includes but is not limited to one or more of the following: physical packaging substrate, physical circuit or circuit diagram of packaging substrate, physical layout or layout of packaging substrate, physical wiring or wiring diagram of packaging substrate, packaging substrate Substrate physical circuit or circuit diagram;

Physical information of the chip or chip module, the physical information includes but is not limited to one or more of the following: physical chip or chip module, physical layout of chip or chip module, physical layout of chip or chip module, physical layout of chip or chip module Wiring or layout and wiring diagrams, physical circuits or circuit diagrams of chips or chip modules;

Wherein, the physical information includes, but is not limited to, one or more of the following physical information: all layers, some layers, and one layer, and the method for selecting layer numbers includes, but is not limited to, one or more of the following: randomly selected, according to rules Select and set; for one layer, the physical information includes but is not limited to one or more of the following physical information: the entire area, multiple partial areas, and a partial area, and the selection method of the area includes but is not limited to the following one or more. One or more: randomly selected, selected according to rules, set.

In this embodiment of the present invention, the method for obtaining the physical information includes but is not limited to one or more of the following:

Directly obtain one or more chips or chip modules to be tested and obtain physical information;

Randomly or according to rules, select one or more chips or chip modules to be tested and obtain physical information;

Obtain physical information directly through one or more of the following methods, including but not limited to: CT, X-ray, X-ray, radiation, ultrasound, non-destructive testing;

Uncover the packaged chip and obtain physical information;

For the physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules is blocked, obtain through one or more methods including but not limited to the following Physical connection relationship: CT, X-ray, X-ray, radiation, ultrasound, non-destructive testing, delamination, flat grinding, grinding, grinding, polishing, polishing, corrosion, etching, sectioning, dissection, dyeing; the physical connection The situation where the relationship is blocked includes, but is not limited to, the physical connection relationship in the flip-chip soldered chip is blocked;

Separating a chip or chip module from a packaging substrate, and/or separating a chip or chip module from other chips or chip modules, including, but not limited to, one or more of the following: breaking or removing or removing connections wire, corrode, etch, heat, de-layer, flat grind, grind, grind, grind, section, dissect, remove chips;

Obtain physical information of one or more layers by means including but not limited to one or more of the following: direct acquisition, by microscope and/or microscopic imaging instrument and/or CT and/or X-ray and/or X-ray and/or or radiographic and/or ultrasonic and/or non-destructive testing to obtain, delaminate, flat grind, grind, grind, grind, polish, corrode, etch, section, dissect, stain, break or remove or remove connecting wires;

By microscope and/or microscopic imaging instrument and/or CT and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or nondestructive examination, in combination with photography or/and image acquisition or/and video recording , or, directly take pictures or/and image acquisition or/and video recording to obtain and record the physical images, images or videos corresponding to the physical information; the physical images, images or videos are one file, or multiple files, or multiple A whole file that is spliced or synthesized from several files;

Obtained by microscope and/or microscopic imaging instrument and/or CT and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or nondestructive testing, combined with visual observation, or direct visual observation Physical information and corresponding physical images and images.

In this embodiment of the present invention, the information determination module 201 obtains or selects multiple chips or chip modules to be tested and obtains physical information, including but not limited to one or more of the following:

In order to obtain multiple samples, perform statistical analysis on the physical information, or/and the comparison between the physical information and the design information, or/and the autonomy and/or controllability of the chip or chip module, and obtain or select multiple samples of the same model. Chip or chip module, obtain the same physical information from each chip or chip module;

In the case of destructive operations or/and only part of the physical information can be obtained from one chip or chip module, obtain or select multiple chips or chip modules of the same type, and obtain from each chip or chip module Different physical information, or simultaneous acquisition of the same and different physical information;

In order to determine the autonomy and/or controllability of a chip composed of multiple chip modules, the multiple chip modules in the chip obtain their respective physical information, and carry out the determination of autonomy and/or controllability. Based on this As a result, the autonomy and/or controllability of the chip is determined.

In this embodiment of the present invention, the design information includes but is not limited to one or more of the following:

The design connection relationship between the chip or chip module and the packaging substrate, and/or the design connection relationship between the chip or chip module and other chips or chip modules, the design connection relationship includes but is not limited to one or more of the following expressions: A design diagram describing the connection relationship, a table describing the design connection relationship, the pin design name describing the design connection relationship, and the design connection relationship expressed by the name; the design information includes but is not limited to one or more of the following design information: For all layers, some layers, and one layer, the selection methods of layer numbers include but are not limited to one or more of the following: random selection, selection according to rules, and setting; for one of the layers, the design information includes but is not limited to the following one or more One or more kinds of design information: the entire area, multiple partial areas, one partial area, the selection method of the area includes but is not limited to one or more of the following: random selection, selection according to rules, setting; the design connection relationship Formats include, but are not limited to, one or more formats;

Design information of the packaging substrate, the design information including but not limited to one or more of the following: packaging substrate design circuit or circuit diagram, packaging substrate design layout or layout diagram, packaging substrate design wiring or wiring diagram, packaging substrate design circuit or Circuit diagram; the design information includes but is not limited to one or more of the following design information: all layers, some layers, and one layer, and the selection method of layer numbers includes but is not limited to one or more of the following: random selection, according to rules Select and set; for one of the layers, the design information includes but is not limited to one or more of the following design information: the entire area, multiple partial areas, and a partial area, and the selection method of the area includes but is not limited to the following one One or more: randomly selected, selected according to rules, and set; the format of the design information of the packaging substrate includes but is not limited to one or more formats;

The first design information of the chip or chip module, the first design information includes but is not limited to one or more of the following: chip or chip module design layout, chip or chip module design layout, chip or chip module design layout and wiring or Layout and wiring diagram; the first design information includes but is not limited to one or more of the following design information: all layers, some layers, one layer, and the selection method of layer numbers includes but is not limited to one or more of the following: random Select, select and set according to the rules; for one layer, the first design information includes but is not limited to one or more of the following design information: the entire area, multiple partial areas, a partial area, and the selection method of the area Including but not limited to one or more of the following: randomly selected, selected according to rules, and set; the first design information used for comparison is all or part of the design information in the first design information; used for The first design information for verification is all or part of the design information in the first design information; the first design information for comparison and the first design information for verification are the same or different designs information; the format of the first design information includes but is not limited to one or more formats; the first design information format used for comparison and the first design information format used for verification are the same or different formats;

Second design information of the chip or chip module, the second design information includes but is not limited to the schematic diagram and/or netlist of the chip or chip module, the schematic diagram and/or netlist includes but is not limited to one of the following or Various: schematic diagram, netlist corresponding to schematic diagram, transistor-level netlist, gate-level netlist for final design of digital chip or digital chip module, gate-level netlist corresponding to the first design information of digital chip or digital chip module ; The second design information includes but is not limited to all or part of the design information; the second design information used for verification with the first design information is all or part of the design information in the second design information ; The second design information used for verification with the third design information is all or part of the design information in the second design information; the second design information used for verification with the fourth design information is the first design information in the second design information. All design information or part of the design information in the second design information; the second design information used for verification with the first design information, the second design information used for verification with the third design information, and the second design information used for verification with the fourth design information In the second design information, any two are the same or different design information; the format of the second design information includes but is not limited to one or more formats; the first design information used for verification with the first design information In the second design information format, the second design information format used for verification with the third design information, and the second design information format used for verification with the fourth design information, any two are the same or different formats;

The third design information of the chip or chip module, the third design information includes but is not limited to the gate-level netlist formed by the register transfer level RTL code synthesis of the digital chip or the digital chip module; the third design information includes but is not limited to All or part of the design information; the third design information used for verification with the second design information is all or part of the design information in the third design information; the third design information used for verification with the fourth design information The third design information is all or part of the design information in the third design information; the third design information used for verification with the second design information, and the third design information used for verification with the fourth design information, are the same or different design information; the format of the third design information includes but is not limited to one or more formats; the third design information format used for verification with the second design information, and the format used for The third design information format for information verification, which is the same or a different format;

The fourth design information of the chip or chip module, the fourth design information includes but is not limited to the RTL code of the digital chip or the digital chip module; the fourth design information includes but is not limited to all or part of the design information; The fourth design information to be verified with the second design information is all or part of the design information in the fourth design information; the fourth design information to be verified with the third design information is the fourth design information All or part of the design information in the information; the fourth design information used for verification with the second design information and the fourth design information used for verification with the third design information are the same or different design information; The format of the fourth design information includes, but is not limited to, one or more formats; the fourth design information format used for verification with the second design information, and the fourth design information format used for verification with the third design information, are the same or a different format.

In this embodiment of the present invention, the information processing module 202 compares the physical information with the design information, including but not limited to one or more of the following:

Compare the physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules with the corresponding design connection relationship to check whether the two are consistent;

Compare the physical information of the packaging substrate with the design information of the corresponding packaging substrate to check whether the two are consistent;

Compare the physical information of the chip or chip module with the first design information of the corresponding chip or chip module, and check whether the two are consistent;

Described comparison includes but not limited to following one or more comparisons: all layers, some layers, one layer, the selection method of layer number includes but not limited to following one or more: randomly select, select according to rules, Setting; for one of the layers, the comparison includes but is not limited to the comparison of one or more of the following: the entire area, a plurality of partial areas, a partial area, and the selection method of the area includes but is not limited to one of the following or Various: random selection, selection according to rules, setting.

In this embodiment of the present invention, before the information processing module 202 compares the physical information with the design information, the information determination module 201 is further configured to confirm the accuracy of the acquired design information.

In this embodiment of the present invention, the comparison method adopted by the information processing module 202 includes, but is not limited to, one or more of the following: automatic comparison through a detection device, and manual comparison;

When the comparison method is automatic comparison by the detection device, it is necessary to judge whether the format of the physical information is a format that the detection device can recognize and/or use; when the format of the physical information is not recognized and/or used by the detection device. or the format used, the format of the physical information needs to be adjusted to a format that can be recognized and/or used by the detection device; the format of the physical information needs to be adjusted to a format that the detection device can recognize and/or use. methods, including but not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table describing the physical connection relationship;

When the comparison method is automatic comparison by the detection device, it is necessary to judge whether the format of the design information is a format that the detection device can recognize and/or use; when the format of the design information is not recognized and/or used by the detection device. or the format used, the format of the design information needs to be adjusted to a format that can be recognized and/or used by the detection device; the format of the design information needs to be adjusted to a format that can be recognized and/or used by the detection device. method, including but not limited to one or more of the following: transforming design information into design images, transforming design connection relationships into tables describing design connection relationships; the design images include but are not limited to saving design information as or/or and images converted into or/and recorded in image format;

The method for judging whether the format of the physical information and/or the design information is a format that the detection device can recognize and/or use includes, but is not limited to one or more of the following: human judgment;

The method for adjusting the format of the physical information and/or the design information to a format that can be recognized and/or used by the detection device includes, but is not limited to, one or more of the following: automatic adjustment by the detection device; Manual adjustment.

In this embodiment of the present invention, when the information processing module 202 compares the physical information with the design information, the corresponding relationship between the physical information and the design information includes but is not limited to one or more of the following:

Correspondence of the same layer;

Correspondence of the same area;

Correspondence of the same position;

The corresponding relationship of the same position scale, the corresponding relationship of the same position scale includes but is not limited to one or more of the following: the position in the physical information and/or the physical image, and the position in the entire physical information and/or the physical image. The ratio of the distance between the points is the same as the ratio of the position in the design information and/or the design image, and the ratio of the distance between the points in the entire design information and/or the design image, then the physical information and/or Or the position of the physical image, and the design information and/or the position of the design image are in a corresponding relationship; the position in the physical information and/or the physical image, and the position in the design information and/or the design image, are After the information and/or the entire physical image and/or the entire design information and/or the entire design image are proportionally scaled, when the entire physical information and/or the entire physical image coincide with the entire design information and/or the entire design image, the positions will also coincide , then the physical information and/or the physical image position, and the design information and/or the design image position are in a corresponding relationship;

Correspondence of the same pin name.

In the embodiment of the present invention, when the information processing module 202 compares the physical information or the physical image with the design information or the design image, it is also used to: compare the physical information or the physical image with the corresponding design information or design image, Each section is divided into one or more sections, the section of physical information or physical image maintains a corresponding relationship with the section of design information or design image, and the comparison is carried out for each section, and the comparison results of each section are combined to analyze this comparison. the result of;

Among them, the situation of splitting into one or more sections includes, but is not limited to, one or more of the following: physical information or physical images, and the comparison content with design information or design images are concentrated in one or more local areas, according to The concentrated area is divided into one or more sections; the physical information or physical images, and the content of the comparison with the design information or design images, the size of the graphics in different areas is greatly different, according to different graphic sizes or according to different size ranges, split it into one or more sections;

Among them, after splitting into plates, if there is no required comparison content in some plates, the comparison of this plate is omitted or not omitted, and when the comparison of this plate is omitted, the comprehensive analysis of the comparison results of each plate This section is not included in the results of the second comparison.

In the embodiment of the present invention, the information processing module 202 compares the physical information or the physical image with the design information or the design image, and/or compares the physical information block or the physical image block with the design information block or the design image block. Comparison, the comparison methods of the comparison include but are not limited to one or more of the following: overall comparison, detailed comparison, sampling comparison;

The comparison content of the comparison includes but is not limited to one or more of the following: connection relationship, geometric shape, geometric shape feature;

The comparison fineness of the comparison is expressed by granularity, and the alignment fineness is related to the comparison method, method, content and purpose, and the granularity includes but is not limited to the accuracy of the comparison content. , the minimum limit of the granularity includes but is not limited to one or more of the following: the smallest graphic in the corresponding information and/or image, the smallest size in the corresponding information and/or image, the smallest in the corresponding information and/or image Area, according to the graphics set according to the corresponding information and/or image, according to the size set according to the corresponding information and/or image, according to the area set according to the corresponding information and/or image.

In the embodiment of the present invention, the information processing module 202 compares the physical information or the physical image with the design information or the design image, and/or compares the physical information block or the physical image block with the design information block or the design image block. Alignment is also used to perform but not limited to one or more of the following:

Adjust the resolution and/or resolution of the physical image and/or the design image and/or the physical image and/or the design image block for the physical image and/or the design image and/or the physical image block and/or the design image block to be compared or the number of pixels, on the basis of the adjustment results, compare the physical image and the design image, and/or the physical image plate and the design image plate;

When the comparison method is automatic comparison by the detection device, for the granularity of this planned comparison, according to the resolution of the physical image and/or the design image and/or the physical image block and/or the design image block, and / or the number of pixels contained in the physical image and/or design image and/or physical image plate and/or design image plate for the granularity of this planned comparison, as well as the comparison ability of the detection device, adjust the physical image and / or The resolution and/or the number of pixels of the design image and/or the physical image block and/or the design image block, based on the adjustment results, for the physical image and the design image, and/or the physical image block and the design image block, carry out Comparison;

The comparison capability of the detection device includes, but is not limited to: the minimum required by the detection device to complete the comparison under the granularity, for the actual image and/or the design image and/or the actual image plate and/or the design image plate respectively. resolution, and/or the minimum number of pixels to be included in the granularity;

The adjustment methods include, but are not limited to: for the granularity of this planned comparison, on the premise of ensuring the accuracy of the comparison, reducing the size of the physical image and/or the design image and/or the physical image plate and/or the design image plate. Resolution and/or number of pixels to reduce the resolution of the physical image and/or design image and/or physical image tile and/or design image tile, and/or physical image and/or design image and/or physical image tile And/or the number of pixels included in the granularity in the design image plate is reduced, and is greater than or equal to the comparison capability of the detection device.

In this embodiment of the present invention, the information processing module 202 adopts the overall comparison method, including but not limited to one or more of the following:

For the entire said physical information or physical image, compared with design information or design image, and/or for the entire said physical information block or physical image block, and design information block or design image block comparison;

The overall alignment includes but is not limited to one or more of the following: overall fine alignment, overall rough alignment;

During the overall fine comparison, the particle size of the comparison has reached the minimum limit;

In the overall rough comparison, the particle size of the comparison is greater than the minimum limit, and the comparison content is embodied in one or more of the following: connection relationship, chip area, chip outline, package substrate area, package substrate Outline, graphic overview, graphic distribution characteristics, module structure;

Applicable situations for the overall fine comparison of the entire physical information or physical image and design information or design images include, but are not limited to, one or more of the following: the time required to complete the overall fine comparison is less than or equal to the first preset time. Set a threshold; the number of pixels of the physical image is less than or equal to a second preset threshold; the number of pixels of the design image is less than or equal to a third preset threshold; the resolution of the physical image is less than or equal to a fourth preset threshold; the The resolution of the design image is less than or equal to the fifth preset threshold; the area of the physical information and/or the physical image and/or the design information and/or the design image is less than or equal to the sixth preset threshold; the physical information and/or the physical The area of the smallest graphic in the image and/or the design information and/or the design image is greater than or equal to a seventh preset threshold;

The applicable situations for the overall fine comparison of the entire physical information plate or the physical image plate and the design information plate or the design image plate include but are not limited to one or more of the following: required to complete the overall fine comparison of the plate The time is less than or equal to the eighth preset threshold; the number of pixels of the physical image block is less than or equal to the ninth preset threshold; the number of pixels of the design image block is less than or equal to the tenth preset threshold; the resolution of the physical image block is less than or equal to equal to the eleventh preset threshold; the resolution of the design image block is less than or equal to the twelfth preset threshold; the area of the physical information block and/or the physical image block and/or the design information block and/or the design image block less than or equal to the thirteenth preset threshold; the area of the smallest graphic in the physical information block and/or the physical image block and/or the design information block and/or the design image block is greater than or equal to the fourteenth preset threshold;

Applicable situations for the overall rough comparison of the entire physical information or physical image and design information or design images include but are not limited to one or more of the following: the time required to complete the overall fine comparison is greater than or equal to the first Fifteen preset thresholds; the number of pixels of the physical image is greater than or equal to the sixteenth preset threshold; the number of pixels of the design image is greater than or equal to the seventeenth preset threshold; the resolution of the physical image is greater than or equal to the eighteenth preset threshold preset threshold; the resolution of the design image is greater than or equal to the nineteenth preset threshold; the area of the physical information and/or the physical image and/or the design information and/or the design image is greater than or equal to the twentieth preset threshold; The area of the smallest graphic in the physical information and/or the physical image and/or the design information and/or the design image is less than or equal to the twenty-first preset threshold; the overall rough comparison is combined with the other comparison methods;

Applicable situations for the overall rough comparison of the entire physical information plate or physical image plate with the design information plate or design image plate include but are not limited to one or more of the following: required to complete the overall fine comparison of the plate The time is greater than or equal to the twenty-second preset threshold; the number of pixels of the physical image block is greater than or equal to the twenty-third preset threshold; the number of pixels of the design image block is greater than or equal to the twenty-fourth preset threshold; The resolution of the physical image block is greater than or equal to the twenty-fifth preset threshold; the resolution of the design image block is greater than or equal to the twenty-sixth preset threshold; the physical information block and/or the physical image block and/or the design The area of the information panel and/or the design image panel is greater than or equal to the twenty-seventh preset threshold; the area of the smallest graphic in the physical information panel and/or the physical image panel and/or the design information panel and/or the design image panel is less than or equal to Equal to the twenty-eighth preset threshold; the overall rough alignment is combined with the other alignment methods.

In this embodiment of the present invention, the information processing module 202 adopts the detailed comparison method, including but not limited to one or more of the following:

For the comparison of the physical information or physical image, and design information or design image, and/or the physical information plate or physical image plate, and the design information plate or design image plate comparison, for including but not limited to the following One or more areas, gradually reduce the comparison area and/or reduce the particle size, and carry out one or more comparisons: areas that fail the overall comparison, areas that are of interest or considered critical after the overall comparison is passed, Realize complex areas, functionally critical areas, and entire areas;

When performing one or more comparisons, the refinement limit is that the comparison area has been reduced to the smallest graphic and/or the smallest size in the corresponding information and/or image and/or information panel and/or image panel, and/or The particle size has reached the minimum limit, and the refinement comparison needs to reach the refinement limit or does not need to reach the refinement limit.

In this embodiment of the present invention, the information processing module 202 adopts the sampling comparison method, including but not limited to one or more of the following:

Calculation and/or setting for the comparison of the physical information or physical image with the design information or the design image, and/or the comparison of the physical information plate or the physical image plate with the design information plate or the design image plate area available for comparison;

According to the area that can be used for comparison, select several sampling blocks from the physical information or physical image or physical information plate or physical image plate, and the sum of the areas of the several sampling blocks shall not exceed the area that can be used for comparison;

According to the area available for comparison, select several sampling blocks from the design information or design image or design information plate or design image plate, and the sum of the areas of the several sampling blocks shall not exceed the area available for comparison;

The sampling block selected from the physical information or the physical image or the physical information block or the physical image block maintains a corresponding relationship with the sampling block selected from the design information or the design image or the design information block or the design image block;

The selection methods of sampling blocks include, but are not limited to, one or more of the following: random sampling, sampling according to rules, allocation of the number of sampling blocks proportional to graphics density and/or complexity, and allocation of sampling blocks proportional to graphics density and/or complexity. area, set;

Compare the physical information or the physical image or the sampling blocks in the physical information plate or the physical image plate with the corresponding design information or design image or the sampling block in the design information plate or the design image plate;

Synthesize the comparison results of each sampling block to analyze the results of this sampling comparison;

The fine limit of the sampling comparison is that the granularity has reached the minimum limit, and the sampling comparison needs to reach the fine limit or does not need to reach the fine limit.

In this embodiment of the present invention, the information processing module 202 calculates an area that can be used for comparison, including but not limited to one or more of the following:

For physical information or physical image or physical information plate or physical image plate, and design information or design image or design information plate or design image plate, according to the time required to complete the comparison per unit area, and the expected completion time of this comparison , calculate the area available for comparison;

The calculation method includes but is not limited to: area available for comparison = unit area * expected completion time of this comparison/time required to complete unit area comparison.

In this embodiment of the present invention, the method for obtaining the minimum shape and/or the minimum size and/or the minimum area includes, but is not limited to, one or more of the following:

Obtain the minimum size from the corresponding design information and/or physical information and/or design information block and/or physical information block, and the acquisition method includes but is not limited to acquiring one or more of the following information: minimum line width, feature Size, process, gate length, channel length;

Further analysis based on minimum size to obtain minimum figure and/or minimum area;

Identify the smallest graphic and/or smallest size and/or smallest area in the corresponding design image and/or physical image and/or design image tile and/or physical image tile.

In this embodiment of the present invention, under one or more situations including but not limited to the following, the information processing module 202 is further configured to adjust the corresponding resolution and/or the number of pixels before comparing:

Before starting the image comparison and/or after splitting the panels and/or during the overall comparison, adjust the resolution and/or the number of pixels of the physical image and/or design image and/or the physical image panel and/or the design image panel. Comparison;

Refinement and comparison After reducing the comparison area and/or reducing the granularity, for the area after the reduction and/or reducing the granularity, adjust the resolution and/or the number of pixels of the corresponding image before comparing;

After the sampling blocks are selected, for each sampling block, the resolution and/or the number of pixels of the corresponding images are adjusted and then compared.

In this embodiment of the present invention, the information processing module 202 is further configured to adjust the comparison implementation algorithm for one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison Comparison methods, different comparison methods, and different work stages in the comparison.

In this embodiment of the present invention, the information processing module 202 verifies the design information, including but not limited to one or more of the following:

Verify the first design information of the chip or chip module and the corresponding second design information, and the verification method includes but is not limited to LVS inspection or verification;

Verifying the second design information of the chip or chip module and the corresponding third design information, and/or verifying the second design information of the chip or chip module and the corresponding fourth design information, the verification methods include but are not limited to formal verify;

The third design information of the chip or chip module is verified with the corresponding fourth design information, and the verification method includes but is not limited to formal verification.

In this embodiment of the present invention, before the information processing module 202 verifies the design information, the information determination module 201 is further configured to confirm the accuracy of the acquired design information.

In this embodiment of the present invention, the method for the information determination module 201 to confirm the accuracy of the acquired design information includes but is not limited to one or more of the following:

For the acquired first design information for comparison and the acquired first design information for verification, it is confirmed that the design information of the overlapping part and/or the repeated part is the same and/or consistent; A method for the design information of the overlapping part and/or the repeated part to be the same and/or consistent, including but not limited to one or more of the following: combining the acquired first design information format for comparison with the acquired The format of the first design information for verification is unified, image comparison is performed for overlapping parts and/or repeating parts, graphic comparison is performed for overlapping parts and/or repeating parts, and similarity is performed for overlapping parts and/or repeating parts comparison, determine that the similarity is greater than or equal to the twenty-ninth preset threshold, and determine all or part of one of the acquired first design information for comparison and the acquired first design information for verification The information is obtained by extracting all or part of the information from another type of information, and/or all or part of the information of one type of information is obtained by extracting all or part of the information from another information format after conversion;

Unify the acquired first design information format for comparison and the acquired first design information format for verification; the method for unifying the two formats includes but is not limited to one or more of the following: One of the two formats is converted into another format, and both formats are converted into a third format; the third format refers to the obtained first design information format for comparison, obtained a format other than the first design information format used for verification;

For the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , for any and/or set one or more pairwise combinations within the combination, and/or between the three, confirm that the design information of the overlapping part and/or the repeated part is the same, and/or Keeping consistent; the method for confirming that the design information of the overlapping parts and/or repeating parts is the same and/or consistent, including but not limited to one or more of the following: unifying the format of the design information; for overlapping parts Perform image comparison with and/or repeated parts; perform graphic comparison with respect to overlapping parts and/or repeated parts; perform similarity comparison with respect to overlapping parts and/or repeated parts; determine that the similarity is greater than or equal to the thirtieth preset threshold ; Determine the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , in which all or part of one or more of the information is obtained by extracting all or part of the other Obtained by extracting all or part of the information from one or more information formats after conversion; the application scenarios of the method for confirming that the design information of the overlapping part and/or the repeated part is the same and/or consistent, including but not limited to : For the analog-digital hybrid chip, confirm that the gate-level netlist of the digital chip module is the same or consistent with the digital chip module part in the transistor-level netlist of the chip after the format is converted to the transistor-level netlist;

For the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , for any and/or set one or more pairwise combinations of the three, and/or between the three, unify the format of the design information; the method for unifying the format of the design information includes: However, it is not limited to one or more of the following: converting one format of the two formats into the other format for the combination of two-two combinations internally, and converting both formats for the internal-combination of two-two combinations The third format refers to the format other than the design information format in the combination, and the format is unified into one of the three formats for the combination of the three. For the three formats, the three formats are converted into the fourth format, and the fourth format for the three refers to formats other than the design information format among the three;

For the acquired third design information for verification with the second design information, and the acquired third design information for verification with the fourth design information, confirm that the overlapping and/or repeated design information therein is the same, and / or keep it consistent; the method for confirming that the design information of the overlapping portion and/or the repeating portion is the same and/or consistent, including but not limited to one or more of the following: The third design information format for design information verification is unified with the acquired third design information format used for verification with the fourth design information, and image comparison is performed for the overlapping portion and/or the repeated portion, and for the overlapping portion and/or Perform graphic comparison on the repeated part, perform similarity comparison on the overlapping part and/or the repeated part, determine that the similarity is greater than or equal to the thirty-first preset threshold, and determine the acquired third design for verification with the second design information Information and the obtained third design information for verification with the fourth design information, all or part of the information of one type of information is obtained by extracting all or part of the information from another type of information, and/or one of the information All or part of the information is obtained by extracting all or part of the information from another information format after conversion;

Unify the acquired third design information format for verification with the second design information and the acquired third design information format for verification with the fourth design information; the method for unifying the formats of the two includes but not It is limited to one or more of the following: converting one of the two formats into another format, and converting both formats into a third format; the third format refers to the The third design information format verified by the second design information, and the acquired format other than the third design information format verified by the fourth design information;

For the acquired fourth design information for verification with the second design information, and the acquired fourth design information for verification with the third design information, confirm that the overlapping part and/or the repeated part design information therein is the same, and / or keep it consistent; the method for confirming that the design information of the overlapping portion and/or the repeating portion is the same and/or consistent, including but not limited to one or more of the following: The fourth design information format for verification of the design information is unified with the obtained fourth design information format for verification with the third design information, and image comparison is performed for the overlapping portion and/or the repeated portion, and the overlapping portion and/or Perform graphic comparison on the repeated part, perform similarity comparison on the overlapping part and/or the repeated part, determine that the similarity is greater than or equal to the thirty-second preset threshold, and determine the acquired fourth design for verification with the second design information Information and the obtained fourth design information for verification with the third design information, all or part of the information of one type of information is obtained by extracting all or part of the information from another type of information, and/or one of the information All or part of the information is obtained by extracting all or part of the information from another information format after conversion;

Unify the acquired fourth design information format for verification with the second design information and the acquired fourth design information format for verification with the third design information; the method for unifying the formats of the two includes but not It is limited to one or more of the following: converting one of the two formats into another format, and converting both formats into a third format; the third format refers to the The fourth design information format verified by the second design information, and the acquired format other than the fourth design information format verified by the third design information;

Confirm that the gate-level netlist in the acquired second design information is a back-end netlist and/or a non-front-end netlist;

Confirm that the gate-level netlist in the acquired third design information is a front-end netlist and/or a non-back-end netlist;

The gate-level netlist in the confirmed second design information obtained is a back-end netlist and/or a non-front-end netlist, and/or the gate-level netlist in the third design information obtained is confirmed to be a front-end netlist, and/or non-backend netlist methods, including but not limited to one or more of the following: keyword retrieval; gate-level netlists in the acquired second design information and gates in the acquired third design information level netlist, compare the similarity, and/or determine that the similarity is less than or equal to the thirty-third preset threshold;

Confirm that the acquired RTL code is a register transfer level description and/or a non-other level description, and the other level description includes but is not limited to a gate level description;

The accuracy of the acquired design information is confirmed by the file suffix of the acquired design information.

In this embodiment of the present invention, when the information processing module 202 verifies the design information, the corresponding relationship between the design information includes but is not limited to one or more of the following: the corresponding relationship of the same module, the corresponding relationship of the same unit Correspondence, correspondence of the same function, correspondence of the same logic, correspondence of the same connection.

In this embodiment of the present invention, when the information processing module 202 performs the verification, it confirms the settings and/or conditions of the verification, and the method for confirming the settings and/or conditions of the verification includes but is not limited to one or more of the following :

When the verification is LVS verification, the settings or/and conditions of the LVS verification are confirmed by analyzing the design information targeted for the LVS verification, or/and viewing the design description corresponding to the design information targeted by the LVS verification; /and conditions include, but are not limited to, one or more of the following: top-level design, top-level unit, top-level logic, top-level module;

When the verification is formal verification, confirm the settings or/and conditions of the formal verification by analyzing the design information targeted by the formal verification, or/and viewing the design description corresponding to the design information targeted by the formal verification; /and conditions include, but are not limited to, one or more of the following: top-level design, top-level unit, top-level logic, top-level module, and constant settings;

The top-level design and/or top-level cell and/or top-level logic and/or top-level module in the verification settings or/and conditions, related to the design information for which verification is aimed, is all or part of the design information of the chip or chip module; all The top-level design and/or top-level unit and/or top-level logic and/or top-level module of the verification setup are the application scenarios of the design information of the part of the chip, including but not limited to: for analog-digital hybrid chips, the formal verification setup or The top-level design and/or top-level unit and/or top-level logic and/or top-level module in the/and condition are digital chip modules in an analog-digital hybrid chip.

In the embodiment of the present invention, when the information processing module 202 carries out the verification, it comprehensively analyzes one or more results or/and reports of the verification to determine whether the verification has passed; when the verification is formal verification, The verification results or/and reports include, but are not limited to, one or more of the following: comparison point matching check results, verification results, and verification reports.

In the embodiment of the present invention, the determination module 203 determines the autonomy and/or controllability of the chip or chip module based on the comparison result and/or the verification result, including but not limited to one or more of the following:

According to the characteristics of the chip or chip module, determine the type of comparison and/or verification required to determine the degree of autonomy and/or controllability of the chip or chip module;

For the required comparison types and/or verification types, according to the degree of difficulty and/or criticality of the links represented by the various types, assign the corresponding comparisons and/or verification types score;

For each of the required comparisons and/or verifications, when actually carried out and passed, the chip or chip module obtains a score corresponding to the comparison and/or verification;

For each of the required comparisons and/or verifications, when the actual implementation fails or the actual implementation fails, the chip or chip module does not obtain the corresponding score for the comparison and/or verification;

Combining the results of various comparisons and/or verifications actually carried out, in the scores corresponding to various comparisons and/or verifications obtained by the chip or chip module, sort out invalid scores;

Among the scores corresponding to various comparisons and/or verifications obtained by the chip or chip module, the invalid scores are removed, the remaining scores are valid scores, the valid scores are summed, and the summation result is used as the final score of the chip or chip module;

According to the final score of the chip or chip module, the degree of autonomy and/or controllability of the chip or chip module is determined.

In the embodiment of the present invention, the determination module 203 synthesizes the results of various comparisons and/or verifications actually carried out, and sorts out the scores corresponding to the various comparisons and/or verifications obtained by the chip or the chip module. Invalid scores, including but not limited to one or more of the following:

When the comparison between the physical information of the chip or chip module and the corresponding first design information fails, the chip or chip module obtains the actual verification information for each of the required verifications when it is actually carried out and passed. The corresponding scores are all invalid scores;

When the verification of the first design information of the chip or chip module and the corresponding second design information fails, the verification of the second design information of the chip or chip module and the corresponding third design information is actually carried out and passed. The corresponding score obtained at the time is invalid score;

When the verification of the first design information of the chip or chip module and the corresponding second design information fails, the verification of the second design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed. The corresponding score obtained at the time is invalid score;

When the verification of the first design information of the chip or chip module and the corresponding second design information fails, the verification of the third design information of the chip or chip module and the corresponding fourth design information is actually carried out and passed. The corresponding score obtained at the time is invalid score;

When the verification of the second design information of the chip or chip module and the corresponding third design information fails, and the verification of the second design information of the chip or chip module and the corresponding fourth design information fails, the The corresponding score obtained when the verification of the third design information of the chip or the chip module and the corresponding fourth design information is actually carried out and passed is an invalid score.

In this embodiment of the present invention, for a chip composed of one or more chip modules, the determination of the autonomy and/or controllability of the chip includes but is not limited to one or more of the following:

For each chip module in the chip, a corresponding weight is assigned according to the difficulty and/or criticality of each chip module. The score of the chip is the weighted sum of the scores of each chip module, based on the weighted sum. Determine the autonomy and/or controllability of the chip;

When assigning corresponding weights, it is necessary to ensure that when a chip with a given function is composed of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and/or degree of control are the same; The implementation methods with the same scores corresponding to the same degree of autonomy and/or the same degree of controllability include but are not limited to one or more of the following: normalization of weight distribution, under different schemes, the predetermined function of the chip. The sum of the weights of each chip module is the same, and when it is determined that each chip module has the highest degree of autonomy and/or controllability, the score of each chip module is the same, and the full score of each chip module is the same;

For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and/or repeat, and the sum of the physical information of each chip module is the physical information of the entire chip;

For each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and/or repeat, and the sum of the design information of each chip module is the design information of the entire chip;

The physical information of the respective chip modules maintains a corresponding relationship with the design information.

In the embodiment of the present invention, when there are chip modules of the same type in the chip modules that make up the chip, the chip modules of the same type are regarded as a whole chip module for detection, and a score is calculated and assigned a Weight; the processing method that the determination module 203 treats the chip modules of the same model as an overall chip module for detection includes but is not limited to one or more of the following:

Determining the sum of the physical information of the chip modules of the same model as the physical information of an integral chip module of the detection, and determining the sum of the design information of the chip modules of the same model as the detection of an integral chip module design information, and calculate the score for an overall chip module of the detection;

From the chip modules of the same model, randomly or according to a rule, select a chip module, and use its score as the score of an overall chip module of the detection;

For the chip modules of the same model, select all or part of the number of chip modules, respectively calculate the scores of the selected chip modules, and use the average value of the scores of the selected chip modules as an overall chip module for the detection. 's score.

In this embodiment of the present invention, the applicable scope of the method for determining the autonomy and/or controllability of a chip composed of one or more chip modules includes but is not limited to one or more of the following:

An analog-digital hybrid chip composed of a digital chip module and an analog chip module;

A multi-chip module MCM formed from multiple dies packaged together;

RF front-end module.

An embodiment of the present invention also provides a detection device for a chip or a chip module, the device includes: a processor and a memory for storing a computer program that can be run on the processor,

Wherein, when the processor is configured to run the computer program, execute:

Determine the physical information of the chip or chip module, and/or determine the design information of the chip or chip module;

comparing the physical information with the design information, and/or verifying the design information;

Based on the comparison result and/or the verification result, the degree of autonomy and/or the degree of controllability of the chip or chip module is determined.

In this embodiment of the present invention, when the processor is configured to run the computer program, it also executes the content described in the foregoing method embodiments, which will not be described in detail here.

It should be noted that: when the device provided in the above embodiment performs chip or chip module detection, only the division of the above program modules is used as an example for illustration. In practical applications, the above processing may be allocated to different program modules as required. , that is, dividing the internal structure of the device into different program modules to complete all or part of the processing described above. In addition, the apparatus provided in the above-mentioned embodiment and the corresponding method embodiment belong to the same concept, and the specific implementation process thereof is detailed in the method embodiment, which will not be repeated here.

The present invention will be described below with reference to scenario embodiments.

This embodiment provides a detection method for a chip or a chip module, which checks the autonomy and controllability of the chip by tracing the design process of the chip or the chip module, and comparing and verifying the outputs of each link of the chip or the chip module. Through comparison and/or verification, the total score is calculated according to certain rules and logic. The higher the obtained score, the higher the degree of autonomy and/or controllability of the chip design process, and the corresponding degree of autonomy and/or controllability. higher. This embodiment provides a simple and objective detection basis for the evaluation of the autonomy and/or controllability of the chip or chip module, and improves the objectivity and practical operation of the evaluation of the autonomy and/or controllability of the chip or chip module sex and comprehensiveness.

Scenario Example 1:

For a chip of a certain type that encapsulates a bare die and does not contain a digital module, an embodiment is provided, which can be performed according to the following processes including but not limited to (see Figure 3 for the flowchart. For the sake of clarity, only the number of each operation is given in the figure). ) to determine the autonomy and/or controllability of this chip:

1. Determine the physical information and design information of the chip:

1.1. Determine the physical connection relationship between the chip and the packaging substrate (a kind of physical information):

Determine the physical connection relationship between the chip (including the internal bare chip) and the packaging substrate. In this embodiment, it is determined as a physical diagram describing the connection relationship - Figure A;

It is assumed here that the physical connection relationships are concentrated in one layer, and the physical map of this layer represents the entire physical connection relationship. If the physical connection relationship has multiple layers, the connection relationship of all layers, some layers, or one of the layers can be recorded according to the actual situation, and a physical map describing the connection relationship can be obtained.

1.2. Determine the physical information of the package substrate (a kind of physical information):

Determine the physical information of the packaging substrate. In this embodiment, it is determined that it is the physical packaging substrate, and is recorded as the physical image of the packaging substrate - Figure Bi, Figure Bj (i, j are the selected layer numbers);

Determine the actual packaging substrate as the physical information of the packaging substrate. For the case where the packaging substrate circuit has multiple layers, select the i-layer and j-layer at random (or in other ways such as selection and setting according to the rules), and combine the microscope and photography. Record it as an image to get Figure Bi and Figure Bj;

Here, it is assumed that the circuit of the package substrate has multiple layers, and some layers (here, two layers, or other layers such as three layers, four layers, etc.) are selected as physical information and images are recorded. For the case where the circuit of the package substrate has multiple layers, it is also possible to select all layers as the physical information and record the image, or select one of the layers as the physical information and record the image. For the case where there is only one layer of the circuit of the package substrate, the image of this layer can be directly recorded.

1.3, determine the physical information of the chip (a kind of physical information):

Determine the physical information of the chip, in this embodiment, determine that it is the physical layout of the chip, and record it as the physical layout of the chip - Figure Cp, Figure Cq (p, q are selected layer numbers);

Determine the physical layout of the chip as the physical information of the chip. For the case where the chip layout has multiple layers, set (or select randomly, according to rules and other methods) p-layer and q-layer as the physical information, and combine the microscope and photography. way to record it as an image, and obtain the graph Cp and graph Cq;

Here, it is assumed that the chip layout has multiple layers, and some layers (here, two layers, or other layers such as three layers, four layers, etc.) are selected as physical information and images are recorded. For the case where the chip layout has multiple layers, you can also select all layers as the physical information and record the image, or select one of the layers as the physical information and record the image. For the case where there is only one layer of the chip layout, the image of this layer can be directly recorded.

1.4. Determine the design connection relationship between the chip and the package substrate (a type of design information):

Confirm the design connection relationship between the chip (including the internal bare chip) and the packaging substrate. In this embodiment, it is determined to be a design diagram describing the connection relationship - Figure a;

The selection of layer numbers in the design diagram describing the connection relationship corresponds to the physical diagram describing the connection relationship.

1.5. Determine the design information of the package substrate (a type of design information):

Determine the design information of the packaging substrate, which is determined as the packaging substrate design circuit diagram in this embodiment - Figure bi, Figure bj (i, j are the selected layer numbers);

The selection of the layer number in the design circuit diagram of the packaging substrate corresponds to the actual drawing of the packaging substrate.

1.6, determine the first design information of the chip (a type of design information):

Determine the first design information of the chip, which is determined to be the design layout of the chip in this embodiment - Figure c (full design layout of the chip), Figure cp, Figure cq (p, q are the selected layer numbers);

Figure c is the entire design layout of the chip, that is, the layout of the entire area of all layers, which is convenient for subsequent verification with the second design information, and is the first design information for verification; Figure cp and Figure cq are the p layer in the chip design layout The layout of layer , q is part of the layout of Figure c. The selection of the layer number corresponds to the physical layout of the chip, which is convenient for subsequent comparison with the physical layout of the chip, and is the first design information for comparison.

1.7, determine the second design information of the chip (a type of design information):

The second design information of the chip is determined. In this embodiment, the second design information is determined to be a schematic diagram of the chip.

2. Compare the physical information with the design information, and verify the design information:

2.1. Compare the physical connection relationship between the chip and the package substrate with the corresponding design connection relationship to check whether the two are consistent (one of the comparisons):

Compare whether the connection relationship between the pins in Figure A is consistent with the connection relationship between the pins in Figure a.

2.2. Compare the physical information of the packaging substrate with the design information of the corresponding packaging substrate to check whether the two are consistent (one of the comparisons):

Compare the graph Bi with the graph bi, and compare the graph Bj with the graph bj, and check whether the geometric shapes and geometric features of the lines in the graph are consistent.

2.3. Compare the physical information of the chip with the first design information of the corresponding chip, and check whether the two are consistent (one type of comparison):

Compare the graph Cp with the graph cp, compare the graph Cq with the graph cq, and check whether the geometric shapes and geometric features of the layout in the graph are consistent.

2.4, verify the first design information of the chip and the corresponding second design information (a kind of verification), and the verification methods include but are not limited to LVS inspection or verification:

The design layout of the chip (Figure c) and the schematic diagram of the chip are verified by LVS.

3. Based on the comparison results and verification results, determine the autonomy and/or controllability of the chip:

Based on the comparison results and verification results, determine the autonomy and/or controllability of the chip, including but not limited to one or more of the following:

According to the characteristics of the chip, determine the type of comparison and/or verification required to determine the degree of autonomy and/or controllability of the chip: In this embodiment, the type of comparison required is determined as: the type of comparison between the chip and the packaging substrate The physical connection relationship and the comparison with the corresponding design connection relationship (Item 2.1), the comparison between the physical information of the package substrate and the design information of the corresponding package substrate (Item 2.2), the physical information of the chip and the corresponding chip first. Comparison of design information (section 2.3); determine the type of verification required: verification of the first design information of the chip and the corresponding second design information (section 2.4);

For the required comparison types and/or verification types, according to the degree of difficulty and/or criticality of the links represented by the various types, assign the corresponding comparisons and/or verification types Score: In this embodiment, the corresponding scores are allocated for the following comparisons and verifications: the physical connection relationship between the chip and the package substrate, the comparison with the corresponding design connection relationship (Item 2.1), the physical information of the package substrate Comparison with the design information of the corresponding package substrate (2.2), comparison between the physical information of the chip and the first design information of the corresponding chip (2.3), the first design information of the chip and the corresponding second design information verification (Article 2.4);

For each of the required comparisons and/or verifications, when actually carried out and passed, the chip obtains a score corresponding to the comparison and/or verification; The chip does not obtain the corresponding score for this comparison and/or verification;

Combining the results of various comparisons and/or verifications actually carried out, among the scores corresponding to various comparisons and/or verifications obtained by the chip, sort out invalid scores;

Among the scores corresponding to various comparisons and verifications obtained by the chip, the invalid scores are removed, the remaining scores are valid scores, the valid scores are summed, and the summation result is used as the final score of the chip;

According to the final score of the chip, the autonomy and/or controllability of the chip is determined.

Scenario Example 2:

For a digital chip of a certain type that encapsulates a bare chip, an example is provided, which can include but not limited to the following process (see the flowchart in Figure 4, for the sake of clarity, only the number of each operation is given in the figure, in addition, in 2.5 and/or relationship, which cannot be shown in the figure, only one of them is shown - verify the second design information in Article 1.7 and the third design information in Article 1.8) to determine the autonomy of this chip and / or Controllability:

1. Determine the physical information and design information of the chip:

1.1. Determine the physical connection relationship between the chip and the packaging substrate (a kind of physical information):

Determine the physical connection relationship between the chip (including the internal bare chip) and the packaging substrate. In this embodiment, it is determined as a physical diagram describing the connection relationship - Figure A;

It is assumed here that the physical connection relationships are concentrated in one layer, and the physical map of this layer represents the entire physical connection relationship. If the physical connection relationship has multiple layers, the connection relationship of all layers, some layers, or one of the layers can be recorded according to the actual situation, and a physical map describing the connection relationship can be obtained.

1.2. Determine the physical information of the package substrate (a kind of physical information):

Determine the physical information of the packaging substrate. In this embodiment, it is determined that it is the physical packaging substrate, and is recorded as the physical image of the packaging substrate - Figure Bi, Figure Bj (i, j are the selected layer numbers);

Determine the actual packaging substrate as the physical information of the packaging substrate. For the case where the packaging substrate circuit has multiple layers, select the i-layer and j-layer at random (or in other ways such as selection and setting according to the rules), and combine the microscope and photography. Record it as an image to get Figure Bi and Figure Bj;

Here, it is assumed that the circuit of the package substrate has multiple layers, and some layers (here, two layers, or other layers such as three layers, four layers, etc.) are selected as physical information and images are recorded. For the case where the circuit of the package substrate has multiple layers, it is also possible to select all layers as the physical information and record the image, or select one of the layers as the physical information and record the image. For the case where there is only one layer of the circuit of the package substrate, the image of this layer can be directly recorded.

1.3, determine the physical information of the chip (a kind of physical information):

Determine the physical information of the chip, in this embodiment, determine that it is the physical layout of the chip, and record it as the physical layout of the chip - Figure Cp, Figure Cq (p, q are selected layer numbers);

Determine the physical layout of the chip as the physical information of the chip. For the case that the chip layout has multiple layers, set (or select randomly, according to rules, etc.) p-layer and q-layer as the physical information, and combine the microscope and photography. way to record it as an image, and obtain the graph Cp and graph Cq;

Here, it is assumed that the chip layout has multiple layers, and some layers (here, two layers, or other layers such as three layers, four layers, etc.) are selected as physical information and images are recorded. For the case where the chip layout has multiple layers, you can also select all layers as the physical information and record the image, or select one of the layers as the physical information and record the image. For the case where there is only one layer of the chip layout, the image of this layer can be directly recorded.

1.4. Determine the design connection relationship between the chip and the package substrate (a type of design information):

Confirm the design connection relationship between the chip (including the internal bare chip) and the packaging substrate. In this embodiment, it is determined to be a design diagram describing the connection relationship - Figure a;

The selection of layer numbers in the design diagram describing the connection relationship corresponds to the physical diagram describing the connection relationship.

1.5. Determine the design information of the package substrate (a type of design information):

Determine the design information of the packaging substrate, which is determined as the packaging substrate design circuit diagram in this embodiment - Figure bi, Figure bj (i, j are the selected layer numbers);

The selection of the layer number in the design circuit diagram of the packaging substrate corresponds to the actual drawing of the packaging substrate.

1.6, determine the first design information of the chip (a type of design information):

Determine the first design information of the chip, which is determined to be the design layout of the chip in this embodiment - Figure c (full design layout of the chip), Figure cp, Figure cq (p, q are the selected layer numbers);

Figure c is the entire design layout of the chip, that is, the layout of the entire area of all layers, which is convenient for subsequent verification with the second design information, and is the first design information for verification; Figure cp and Figure cq are the p layer in the chip design layout The layout of layer , q is part of the layout of Figure c. The selection of the layer number corresponds to the physical layout of the chip, which is convenient for subsequent comparison with the physical layout of the chip, and is the first design information for comparison.

1.7, determine the second design information of the chip (a type of design information):

Determine the second design information of the chip. In this embodiment, the second design information is determined to be the gate-level netlist for the final design of the chip (this example is taken as an example, in fact, it may also be the gate-level netlist corresponding to the first design information, etc. Other content).

It should be noted that the above determination that the second design information is the gate-level netlist for the final design of the chip is for the case where the LVS verification software can take the gate-level netlist format as input. If the LVS software cannot take the gate-level netlist format as input, You can do one or more of the following:

Convert the gate-level netlist of the final design of the chip into an input format acceptable to LVS software, such as the cdl netlist and other transistor-level netlist formats (confirm the accuracy of the acquired design information), and complete the gate-level design of the chip. The transistor-level netlist such as the netlist and the converted cdl netlist are used as the second design information, the former is used for verification with the third design information, and the latter is used for verification with the first design information;

Determine and obtain the gate-level netlist for the final design of the chip, obtain the transistor-level netlist such as the chip cdl netlist, and confirm that the converted format of the gate-level netlist is the same or consistent with the obtained cdl netlist and other transistor-level netlists ( Confirm the accuracy of the obtained design information), use the gate-level netlist of the chip to complete the final design, the chip cdl netlist and other transistor-level netlists as the second design information, the former is used to verify the third design information, and the latter is used Comes with the first design information verification.

1.8, determine the third design information of the chip (a type of design information):

The third design information of the chip is determined. In this embodiment, the third design information is determined to be a gate-level netlist formed by synthesis of the RTL code of the chip.

1.9, determine the fourth design information of the chip (a kind of design information):

The fourth design information of the chip is determined. In this embodiment, the fourth design information is determined to be the RTL code of the chip.

2. Compare the physical information with the design information, and verify the design information:

2.1. Compare the physical connection relationship between the chip and the package substrate with the corresponding design connection relationship to check whether the two are consistent (one of the comparisons):

Compare whether the connection relationship between the pins in Figure A is consistent with the connection relationship between the pins in Figure a.

2.2. Compare the physical information of the packaging substrate with the design information of the corresponding packaging substrate to check whether the two are consistent (one of the comparisons):

Compare the graph Bi with the graph bi, and compare the graph Bj with the graph bj, and check whether the geometric shapes and geometric features of the lines in the graph are consistent.

2.3. Compare the physical information of the chip with the first design information of the corresponding chip, and check whether the two are consistent (one type of comparison):

Compare the graph Cp with the graph cp, compare the graph Cq with the graph cq, and check whether the geometric shapes and geometric features of the layout in the graph are consistent.

2.4, verify the first design information of the chip and the corresponding second design information (a kind of verification), and the verification methods include but are not limited to LVS inspection or verification:

Perform LVS verification on the design layout of the chip (Figure c) and the gate-level netlist of the final design of the chip.

2.5, verify the second design information of the chip and the corresponding third design information, and/or verify the second design information of the chip and the corresponding fourth design information (a kind of verification), the verification method includes but does not Limited to formal verification:

In this embodiment, formal verification is performed on the gate-level netlist of the final design of the chip and the gate-level netlist formed by the synthesis of the RTL code of the chip, and/or the gate-level netlist of the final design of the chip and the RTL code of the chip are formally verified verify.

2.6, verify the third design information of the chip and the corresponding fourth design information (a kind of verification), and the verification methods include but are not limited to formal verification:

In this embodiment, formal verification is performed on the gate-level netlist formed by the synthesis of the chip RTL code and the RTL code of the chip.

3. Based on the comparison results and verification results, determine the autonomy and/or controllability of the chip:

Based on the comparison results and verification results, determine the autonomy and/or controllability of the chip, including but not limited to one or more of the following:

According to the characteristics of the chip, determine the type of comparison and/or verification required to determine the degree of autonomy and/or controllability of the chip: In this embodiment, the type of comparison required is determined as: the type of comparison between the chip and the packaging substrate The physical connection relationship and the comparison with the corresponding design connection relationship (Item 2.1), the comparison between the physical information of the package substrate and the design information of the corresponding package substrate (Item 2.2), the physical information of the chip and the corresponding chip first. Comparison of design information (item 2.3); determine the types of verification required: verification of the first design information of the chip and the corresponding second design information (item 2.4), the second design information of the chip and the corresponding third design information and/or the verification of the second design information of the chip and the corresponding fourth design information (Article 2.5), the verification of the third design information of the chip and the corresponding fourth design information (Article 2.6);

For the required comparison types and/or verification types, according to the degree of difficulty and/or criticality of the links represented by the various types, assign the corresponding comparisons and/or verification types Score: In this embodiment, the corresponding scores are allocated for the following comparisons and verifications: the physical connection relationship between the chip and the package substrate, the comparison with the corresponding design connection relationship (Item 2.1), the physical information of the package substrate Comparison with the design information of the corresponding package substrate (2.2), comparison between the physical information of the chip and the first design information of the corresponding chip (2.3), the first design information of the chip and the corresponding second design information verification (Item 2.4), verification of the second design information of the chip and the corresponding third design information, and/or verification of the second design information of the chip and the corresponding fourth design information (Article 2.5), the third design information of the chip Verification of design information and corresponding fourth design information (Article 2.6);

For each of the required comparisons and/or verifications, when actually carried out and passed, the chip obtains a score corresponding to the comparison and/or verification; The chip does not obtain the corresponding score for this comparison and/or verification;

Combining the results of various comparisons and/or verifications actually carried out, among the scores corresponding to various comparisons and/or verifications obtained by the chip, sort out invalid scores;

Among the scores corresponding to various comparisons and verifications obtained by the chip, the invalid scores are removed, the remaining scores are valid scores, the valid scores are summed, and the summation result is used as the final score of the chip;

According to the final score of the chip, the autonomy and/or controllability of the chip is determined.

Scenario Example 3:

For a certain type of analog-digital hybrid chip that encapsulates a bare chip, an embodiment (two methods) is provided, and the autonomy and/or controllability of the chip can be determined according to a process including but not limited to one or more of the following methods Spend:

method one:

The analog-digital hybrid chip is regarded as a chip composed of analog chip modules, digital chip modules and other chip modules:

For the analog chip modules and digital chip modules in the chip, the corresponding weights are allocated according to the difficulty and/or criticality of the realization of each chip module, and the score of the chip is the weighted sum of the scores of each chip module. The weighted sum value determines the autonomy and/or controllability of the chip;

When assigning corresponding weights, it is necessary to ensure that when a chip with a given function is composed of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and/or degree of control are the same; The implementation methods with the same scores corresponding to the same degree of autonomy and/or the same degree of controllability include but are not limited to one or more of the following: normalization of weight distribution, under different schemes, the predetermined function of the chip. The sum of the weights of each chip module is the same, and when it is determined that each chip module has the highest degree of autonomy and/or controllability, the score of each chip module is the same, and the full score of each chip module is the same: as in In this embodiment, the sum of the weights of the analog chip module and the digital chip module is set to 1, and the full score of each chip module is set to 100;

For the analog chip module and digital chip module in the analog-digital hybrid chip, according to the relationship between the module and the chip, the physical information and design information of the analog-digital hybrid chip are divided into the analog chip module and the digital chip module, so that the analog chip module, The physical information of the digital chip module does not overlap and/or repeat, and the sum of the physical information of each chip module is the physical information of the entire chip, so that the design information of the analog chip module and the digital chip module does not overlap and/or repeat. , and the sum of the design information of each chip module is the design information of the entire chip, and the physical information of each chip module maintains a corresponding relationship with the design information;

The score of the analog chip module is calculated with reference to Scenario Example 1 (the analog chip module is regarded as the chip in Scenario Score, the score of the chip is the weighted sum value of the scores of each chip module, and the degree of autonomy and/or controllability of the chip is determined based on the weighted sum value. Among them, it needs to be supplemented that the connection relationship (including physical connection relationship and design connection relationship) of scenario embodiment 1 and scenario embodiment 2 is only the physical connection relationship between the chip (chip module) and the packaging substrate, and this embodiment refers to Scenario Example 1 (the analog chip module is regarded as the chip in Scenario Example 1) calculates the score of the analog chip module, and calculates the score of the digital chip module with reference to Scenario Example 2 (the digital chip module is regarded as the chip in Scenario Example 2) When the connection relationship is used, the connection relationship between the analog chip module and the digital chip module should be supplemented, and the connection relationship between the analog chip module and the digital chip module should be reasonably divided into the analog chip module and the digital chip module. operate.

Method Two:

1. Determine the physical information and design information of the chip:

1.1. Determine the physical connection relationship between the chip and the packaging substrate (a kind of physical information):

Determine the physical connection relationship between the chip (including the internal bare chip) and the packaging substrate. In this embodiment, it is determined as a physical diagram describing the connection relationship - Figure A;

It is assumed here that the physical connection relationships are concentrated in one layer, and the physical map of this layer represents the entire physical connection relationship. If the physical connection relationship has multiple layers, the connection relationship of all layers, some layers, or one of the layers can be recorded according to the actual situation, and a physical map describing the connection relationship can be obtained.

1.2. Determine the physical information of the package substrate (a kind of physical information):

Determine the physical information of the packaging substrate. In this embodiment, it is determined that it is the physical packaging substrate, and is recorded as the physical image of the packaging substrate - Figure Bi, Figure Bj (i, j are the selected layer numbers);

Determine the actual packaging substrate as the physical information of the packaging substrate. For the case where the packaging substrate circuit has multiple layers, select the i-layer and j-layer at random (or in other ways such as selection and setting according to the rules), and combine the microscope and photography. Record it as an image to get Figure Bi and Figure Bj;

Here, it is assumed that the circuit of the package substrate has multiple layers, and some layers (here, two layers, or other layers such as three layers, four layers, etc.) are selected as physical information and images are recorded. For the case where the circuit of the package substrate has multiple layers, it is also possible to select all layers as the physical information and record the image, or select one of the layers as the physical information and record the image. For the case where there is only one layer of the circuit of the package substrate, the image of this layer can be directly recorded.

1.3, determine the physical information of the chip (a kind of physical information):

Determine the physical information of the chip, in this embodiment, determine that it is the physical layout of the chip, and record it as the physical layout of the chip - Figure Cp, Figure Cq (p, q are selected layer numbers);

Determine the physical layout of the chip as the physical information of the chip. For the case that the chip layout has multiple layers, set (or select randomly, according to rules, etc.) p-layer and q-layer as the physical information, and combine the microscope and photography. way to record it as an image, and obtain the graph Cp and graph Cq;

Here, it is assumed that the chip layout has multiple layers, and some layers (here, two layers, or other layers such as three layers, four layers, etc.) are selected as physical information and images are recorded. For the case where the chip layout has multiple layers, you can also select all layers as the physical information and record the image, or select one of the layers as the physical information and record the image. For the case where there is only one layer of the chip layout, the image of this layer can be directly recorded.

1.4. Determine the design connection relationship between the chip and the package substrate (a type of design information):

Confirm the design connection relationship between the chip (including the internal bare chip) and the packaging substrate. In this embodiment, it is determined to be a design diagram describing the connection relationship - Figure a;

The selection of layer numbers in the design diagram describing the connection relationship corresponds to the physical diagram describing the connection relationship.

1.5. Determine the design information of the package substrate (a type of design information):

Determine the design information of the packaging substrate, which is determined as the packaging substrate design circuit diagram in this embodiment - Figure bi, Figure bj (i, j are the selected layer numbers);

The selection of the layer number in the design circuit diagram of the packaging substrate corresponds to the actual drawing of the packaging substrate.

1.6, determine the first design information of the chip (a type of design information):

Determine the first design information of the chip, which is determined to be the design layout of the chip in this embodiment - Figure c (full design layout of the chip), Figure cp, Figure cq (p, q are the selected layer numbers);

Figure c is the entire design layout of the chip, that is, the layout of the entire area of all layers, which is convenient for subsequent verification with the second design information, and is the first design information for verification; Figure cp and Figure cq are the p layer in the chip design layout The layout of layer , q is part of the layout of Figure c. The selection of the layer number corresponds to the physical layout of the chip, which is convenient for subsequent comparison with the physical layout of the chip, and is the first design information for comparison.

1.7, determine the second design information of the chip (a type of design information):

Determine the second design information of the chip. In this embodiment, the second design information is determined to be the transistor-level netlist of the chip (such as the cdl netlist) and the gate-level netlist of the final design completed by the digital chip module in the chip (this embodiment uses this For example, it may actually be other content such as the gate-level netlist corresponding to the first design information).

Wherein, the transistor-level netlist of the chip (such as the cdl netlist) is used for verification with the first design information of the chip, and the gate-level netlist of the final design completed by the digital chip module is used for verification with the third design information, and/or verifying with the fourth design information;

Confirm the accuracy of the acquired design information before verification, including but not limited to: complete the gate-level netlist of the final design for the digital chip module, convert the format into the format of the chip transistor-level netlist, and compare the contents with the chip transistors. Similarity comparison is performed on the contents of the digital chip module in the level netlist, and the two should be identical and/or consistent and/or the similarity should be greater than or equal to a preset threshold.

(Or: determine the second design information of the chip, and determine that the second design information is the transistor-level netlist of the chip, the gate-level netlist of the digital chip module in the chip to complete the final design, and the schematic diagram of the analog chip module in the chip;

At this time, the netlist of the chip transistor level and the schematic diagram of the analog chip module in the chip are used to verify the first design information of the chip (the two can be verified with the first design information respectively, and the results of the two can be combined as the first design information. A result of verifying the design information and the second design information; when the schematic diagram of the analog chip module is verified, the layout side input can use Figure c as the LVS input, set the analog chip module as the top-level design and/or top-level unit and/or Top-level logic and/or top-level module, or, add analog chip module layout to the first design information as the first design information, as input on the layout side, at this time, the first design information should be supplemented to confirm the accuracy of the design information) , the gate-level netlist of the final design completed by the digital chip module is used for verification with the third design information, and/or verification with the fourth design information;

Confirm the accuracy of the acquired design information before verification, including but not limited to: complete the gate-level netlist of the final design for the digital chip module, convert the format into the format of the chip transistor-level netlist, and compare the contents with the chip transistors. The content of the digital chip module in the level netlist is compared for similarity, and the two should be the same and/or consistent and/or the similarity is greater than or equal to a preset threshold; for the schematic diagram of the analog chip module, the format is converted into The format of the chip transistor-level netlist, and the content in the chip transistor-level netlist is compared with the content of the analog chip module in the chip transistor-level netlist. The two should be the same and/or consistent and/or similar a preset threshold;

Other modules can also be independently verified with reference to the analog chip module, and then establish a connection with other design information through the confirmation of the accuracy of the design information, which will not be repeated here. )

1.8, determine the third design information of the chip (a kind of design information):

The third design information of the chip is determined. In this embodiment, the third design information is determined to be a gate-level netlist synthesized by the RTL code of the digital chip module in the chip.

1.9, determine the fourth design information of the chip (a kind of design information):

The fourth design information of the chip is determined. In this embodiment, the fourth design information is determined to be the RTL code of the digital chip module in the chip.

2. Compare the physical information with the design information, and verify the design information:

2.1. Compare the physical connection relationship between the chip and the package substrate with the corresponding design connection relationship to check whether the two are consistent (one of the comparisons):

Compare whether the connection relationship between the pins in Figure A is consistent with the connection relationship between the pins in Figure a.

2.2. Compare the physical information of the packaging substrate with the design information of the corresponding packaging substrate to check whether the two are consistent (one of the comparisons):

Compare the graph Bi with the graph bi, and compare the graph Bj with the graph bj, and check whether the geometric shapes and geometric features of the lines in the graph are consistent.

2.3. Compare the physical information of the chip with the first design information of the corresponding chip, and check whether the two are consistent (one type of comparison):

Compare the graph Cp with the graph cp, compare the graph Cq with the graph cq, and check whether the geometric shapes and geometric features of the layout in the graph are consistent.

2.4, verify the first design information of the chip and the corresponding second design information (a kind of verification), and the verification methods include but are not limited to LVS inspection or verification:

Perform LVS verification on the chip's design layout (Figure c) and the chip transistor-level netlist (such as the cdl netlist).

2.5, verify the second design information of the chip and the corresponding third design information, and/or verify the second design information of the chip and the corresponding fourth design information (a kind of verification), the verification method includes but does not Limited to formal verification:

In this embodiment, formal verification is performed on the gate-level netlist of the final design completed by the digital chip module in the chip and the gate-level netlist formed by the synthesis of the RTL code of the digital chip module in the chip, and/or the final design of the digital chip module in the chip is completed. The gate-level netlist is formally verified with the RTL code of the digital chip module in the chip.

2.6, verify the third design information of the chip and the corresponding fourth design information (a kind of verification), and the verification methods include but are not limited to formal verification:

In this embodiment, the gate-level netlist formed by synthesis of the RTL code of the digital chip module in the chip is formally verified with the RTL code of the digital chip module in the chip.

3. Based on the comparison results and verification results, determine the autonomy and/or controllability of the chip:

Based on the comparison results and verification results, determine the autonomy and/or controllability of the chip, including but not limited to one or more of the following:

According to the characteristics of the chip, determine the type of comparison and/or verification required to determine the degree of autonomy and/or controllability of the chip: In this embodiment, the type of comparison required is determined as: the type of comparison between the chip and the packaging substrate The physical connection relationship and the comparison with the corresponding design connection relationship (Item 2.1), the comparison between the physical information of the package substrate and the design information of the corresponding package substrate (Item 2.2), the physical information of the chip and the corresponding chip first. Comparison of design information (item 2.3); determine the types of verification required: verification of the first design information of the chip and the corresponding second design information (item 2.4), the second design information of the chip and the corresponding third design information and/or the verification of the second design information of the chip and the corresponding fourth design information (Article 2.5), the verification of the third design information of the chip and the corresponding fourth design information (Article 2.6);

For the required comparison types and/or verification types, according to the degree of difficulty and/or criticality of the links represented by the various types, assign the corresponding comparisons and/or verification types Score: In this embodiment, the corresponding scores are allocated for the following comparisons and verifications: the physical connection relationship between the chip and the package substrate, the comparison with the corresponding design connection relationship (Item 2.1), the physical information of the package substrate Comparison with the design information of the corresponding package substrate (2.2), comparison between the physical information of the chip and the first design information of the corresponding chip (2.3), the first design information of the chip and the corresponding second design information verification (Item 2.4), verification of the second design information of the chip and the corresponding third design information, and/or verification of the second design information of the chip and the corresponding fourth design information (Article 2.5), the third design information of the chip Verification of design information and corresponding fourth design information (Article 2.6);

For each of the required comparisons and/or verifications, when actually carried out and passed, the chip obtains a score corresponding to the comparison and/or verification; The chip does not obtain the corresponding score for this comparison and/or verification;

Combining the results of various comparisons and/or verifications actually carried out, among the scores corresponding to various comparisons and/or verifications obtained by the chip, sort out invalid scores;

Among the scores corresponding to various comparisons and verifications obtained by the chip, the invalid scores are removed, the remaining scores are valid scores, the valid scores are summed, and the summation result is used as the final score of the chip;

According to the final score of the chip, the autonomy and/or controllability of the chip is determined.

Scenario Example 4:

For a chip of a certain type that encapsulates n die (respectively called die 1, die 2... die n), each die is regarded as a chip module, then the chip of this type can be regarded as consisting of n chips The modules (respectively referred to as chip module 1, chip module 2...chip module n) are composed.

In order to determine the autonomy and/or controllability of this type of chip, one or more chips of this type are selected randomly or according to rules from one or more batches of this type of chip products (if a chip can obtain all its physical information) , select one chip, if there is a destructive operation when obtaining physical information, so that one chip is not enough to obtain all physical information, then select multiple chips), according to the following process to determine the chip module 1 and chip module 2 in this chip respectively. ...the autonomy and/or controllability of the chip module n, on which the autonomy and/or controllability of the chip are determined:

For a chip composed of one or more chip modules, the determination of the autonomy and/or controllability of the chip includes but is not limited to one or more of the following (in this embodiment, for the chip module 1, the chip Module 2... a chip composed of a chip module n, the determination of the autonomy and/or controllability of the chip includes but is not limited to one or more of the following):

For each chip module in the chip (in this embodiment, that is, chip module 1, chip module 2, ... The score is the weighted sum value of the scores of each chip module, and the autonomy and/or controllability of the chip is determined based on the weighted sum value;

The calculation of the score of each chip module may refer to scenario embodiment 1 (the chip module is regarded as a chip in scenario embodiment 1) and/or scenario embodiment 2 (chip module is regarded as scenario embodiment 2) according to the type of chip module chip) and/or scenario embodiment 3 (the chip module is regarded as the chip in scenario embodiment 3) and/or the present invention is carried out.

Among them, it needs to be supplemented that the connection relationship (including physical connection relationship and design connection relationship) of Scenario Example 1, Scenario Example 2, and Scenario Example 3 is only the chip (equivalent to the chip module in this embodiment) and the package. The physical connection relationship between the substrates, and when calculating the score of the chip module with reference to Scenario Example 1 and/or Scenario Example 2 and/or Scenario Example 3, the connection relationship needs to supplement the connection relationship between the chip modules as appropriate. (that is, the connection relationship between the chip module and other chip modules), and reasonably split it into each chip module, and then proceed according to the method in the scenario embodiment 1 and/or the scenario embodiment 2 and/or the scenario embodiment 3. Operation; the connection relationship needs to supplement the connection relationship between the chip modules as appropriate, that is, when there is a connection between one or more chip modules and one or more other chip modules.

When assigning corresponding weights, it is necessary to ensure that when a chip with a given function is composed of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and/or controllability are all the same; The implementation methods that have the same scores corresponding to the same degree of autonomy and/or the same degree of controllability include but are not limited to one or more of the following: normalization of weight distribution (for example, in this embodiment, chip module 1, chip module 2... The sum of the weights of the chip module n is 1), under different schemes, the sum of the weights of the chip modules of the chip with the predetermined function is the same, and it is determined that the autonomy and/or controllability of the chip modules are When the degree is the highest, the score of each chip module is the same, and the full score of each chip module is the same (for example, in this embodiment, the full score of chip module 1, chip module 2...chip module n are all 100);

For each chip module in the chip, when determining the physical information of each chip module, ensure that the physical information of each chip module does not overlap and/or repeat, and the sum of the physical information of each chip module is the physical information of the entire chip; For each chip module in the chip, when determining the design information of each chip module, ensure that the design information of each chip module does not overlap and/or repeat, and the sum of the design information of each chip module is the design information of the entire chip; The physical information of the respective chip modules maintains a corresponding relationship with the design information (for example, in this embodiment, when the chip module 1, the chip module 2...the chip module n are placed on the same packaging substrate, the physical information for the packaging substrate and the corresponding design information , according to its relationship with chip module 1, chip module 2...chip module n, to ensure that the physical information of the package substrates allocated to chip module 1, chip module 2...chip module n does not overlap, and the sum is exactly All physical information of the packaging substrate, ensure that the design information of the packaging substrates allocated to chip module 1, chip module 2... chip module n does not overlap, and the sum of the design information is exactly all the design information of the packaging substrate);

If some chip modules in chip module 1, chip module 2...chip module n are of the same model (for example, chip module 1 and chip module 2 are of the same model), the chip modules of the same model can be regarded as a whole for detection. The chip module calculates the score once and assigns a weight (that is, when assigning weights, the chip module 1 and chip module 2 are no longer assigned weights respectively, but are regarded as a whole and assigned a weight. The weights and the weights of chip modules other than chip module 1 and chip module 2 continue to meet the normalization requirements during allocation); the described chip modules of the same model are unified as a whole chip for detection The processing method of the module includes but is not limited to one or more of the following: determining the sum of the physical information of the chip modules of the same model as the physical information of an overall chip module of the detection (for example, the chip module 1, chip The sum of the physical information of the module 2 is determined as the physical information of an integral chip module), and the sum of the design information of the chip modules of the same model is determined as the design information of an integral chip module of the detection (for example, the chip module 1. The sum of the design information of the chip module 2 is determined as the design information of an overall chip module), and a score is calculated for an overall chip module of the detection; For the chip module, take its score as the score of an overall chip module of the detection (for example, take the score of chip module 1 as the score of an overall chip module); for the chip modules of the same model, select all numbers or parts from them For the number of chip modules, the scores of the selected chip modules are calculated respectively, and the average value of the scores of the selected chip modules is taken as the score of an entire chip module in the detection.

Scenario Example 5:

According to the results of various comparisons and/or verifications carried out in the comprehensive practice, among the scores corresponding to the various comparisons and/or verifications obtained by the chip or chip module, the invalid scores are sorted out, and the following examples are given. illustrate:

If, according to the characteristics of the chip or chip module, it is determined to determine the degree of autonomy and/or controllability of the chip or chip module, the required comparison types and/or verification types are as follows: The physical connection relationship, and/or the physical connection relationship between the chip or chip module and other chips or chip modules, the comparison with the corresponding design connection relationship (comparison 1), the physical information of the packaging substrate and the design of the corresponding packaging substrate The comparison of information (comparison 2), the comparison between the physical information of the chip or chip module and the first design information of the corresponding chip or chip module (comparison 3), the first design information of the chip or chip module and the corresponding The verification of the second design information (Verification 1), the verification of the second design information of the chip or chip module and the corresponding third design information, and/or the verification of the second design information of the chip or chip module and the corresponding fourth design information verification (verification 2), verification of the third design information of the chip or chip module and the corresponding fourth design information (verification 3);

Invalid scores are sorted out, including but not limited to one or more of the following:

When the comparison 3 fails, the corresponding scores obtained by the chip module when actually carrying out and passing each of the required verifications are invalid scores. In this embodiment, verification 1 and verification 2 are performed at this time. . The corresponding scores obtained when verification 3 is actually carried out and passed are invalid scores;

When verification 1 fails, the corresponding score obtained when the verification of the second design information of the chip or the chip module and the corresponding third design information in verification 2 is actually carried out and passed is an invalid score;

When verification 1 fails, the corresponding score obtained when the verification of the second design information of the chip or chip module and the corresponding fourth design information in verification 2 is actually carried out and passed is an invalid score;

When verification 1 fails, the corresponding score obtained when verification 3 is actually carried out and passed is invalid;

When the verification of the second design information of the chip or chip module and the corresponding third design information in Verification 2 fails, and the verification of the second design information of the chip or chip module and the corresponding fourth design information in Verification 2 fails , the corresponding score obtained when verification 3 is actually carried out and passed is invalid.

Scenario Example 6:

For the acquisition method of the physical information, the following examples are given (the acquisition methods of some physical information have been explained in the manual, and will not be repeated here):

Some examples of the acquisition of the physical connection relationship between the chip or chip module and the packaging substrate, and/or the physical connection relationship between the chip or chip module and other chips or chip modules:

For the case where the chip or chip module is connected with the packaging substrate by wire bonding, and/or the chip or chip module is connected with other chips or chip modules, and the connection relationship established by the wires is not blocked, the Obtain the physical connection relationship by combining microscope (and/or microscopic imaging instrument and/or CT and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or nondestructive testing, etc.) with photography; For the connection method using flip-chip bonding in the chip to connect the chip or chip module with the package substrate, and/or connect the chip or chip module with other chips or chip modules, the connection relationship established by flip-chip bonding is controlled by the chip and/or blocked by the chip module and/or the packaging substrate, etc., the physical connection relationship can be obtained by means of CT (and/or X-ray and/or X-ray and/or radiation and/or ultrasound and/or nondestructive testing, etc.). , or by flat grinding (and/or delayering and/or grinding and/or grinding and/or sanding and/or polishing and/or etching and/or etching and/or sectioning and/or dissection and/or staining and other forms) to expose the flip-chip interface (this interface represents the physical connection relationship), and then obtain the physical connection relationship through a combination of microscopes and other forms and photography, in which flat grinding can start from the chip and/or chip module side or from the package. Start from the substrate side, in this case, the chip and/or chip module and/or package substrate will be damaged. If you need to obtain other physical information from it, you need to select another one or more chips and/or chip modules to obtain (this is also to obtain or select one or more of the chips or chip modules to be tested and obtain physical information);

Some examples of separating chips or chip modules from packaging substrates, and/or separating chips or chip modules from other chips or chip modules: If multiple chip modules are on the same packaging substrate, other chip modules affect the chip module To obtain physical information, the chip module can be separated from the packaging substrate first, including but not limited to one or more of the following: disconnecting or removing or removing connecting wires, corrosion, etching, heating, de-layering, flat grinding, Grinding, grinding, grinding, sectioning, dissecting, removing chips;

Some examples of obtaining physical information of one or more layers: For the physical connection relationship and/or the physical information of the package substrate and/or the physical information of the chip or chip module, if the selected layer number corresponds to the surface layer, and the information If it is not blocked, you can directly obtain the physical information, and/or record it as an image through a combination of microscopes and other means; and/or flat grinding and/or grinding and/or grinding and/or grinding and/or polishing and/or corrosion and/or etching and/or sectioning and/or dissection and/or staining and/or breaking or Remove or remove connecting lines, etc.) to expose the layer, and then directly obtain physical information, and/or record it as an image through a combination of microscopes and other forms and photography.

Scenario Example 7:

Methods for the comparison include, but are not limited to, one or more of the following: automatic comparison by a detection device, manual comparison, and the following examples are illustrated:

When the comparison method is automatic comparison by the detection device, it is necessary to judge whether the format of the physical information is a format that the detection device can recognize and/or use; when the format of the physical information is not recognized and/or used by the detection device. or the format used, the format of the physical information needs to be adjusted to a format that can be recognized and/or used by the detection device; the format of the physical information needs to be adjusted to a format that the detection device can recognize and/or use. methods, including but not limited to one or more of the following: recording the physical information as a physical image, converting the physical connection relationship into a table describing the physical connection relationship;

When the comparison method is automatic comparison by the detection device, it is necessary to judge whether the format of the design information is a format that the detection device can recognize and/or use; when the format of the design information is not recognized and/or used by the detection device. or the format used, the format of the design information needs to be adjusted to a format that can be recognized and/or used by the detection device; the format of the design information needs to be adjusted to a format that can be recognized and/or used by the detection device. method, including but not limited to one or more of the following: transforming design information into design images, transforming design connection relationships into tables describing design connection relationships; the design images include but are not limited to saving design information as or/or and images converted into or/and recorded in image format;

For the method of adjusting the format of the design information to a format that the detection device can recognize and/or use, the following examples are given: when the physical connection relationship and/or the physical information of the packaging substrate and/or the chip or chip module When the physical information is recorded as a physical image, the design connection relationship and/or the design information of the packaging substrate and/or the first design information of the chip or chip module are in a format that the detection device cannot use for image comparison, such as vector format, The format of the design information is converted from a vector graphics format to an image format (converting the design information into a design image), and the detection device compares the physical image and the design image; for the physical connection relationship and design connection relationship, also There is a way to convert the respective connection relationships into tables, and then the detection device compares the two tables (a table describing the physical connection relationship, and a table describing the design connection relationship).

The method for judging whether the format of the physical information and/or the design information is a format that the detection device can recognize and/or use includes, but is not limited to one or more of the following: human judgment;

The method for adjusting the format of the physical information and/or the design information to a format that can be recognized and/or used by the detection device includes, but is not limited to, one or more of the following: automatic adjustment by the detection device; Manual adjustment.

Scenario Example 8:

In order to compare the physical image of the chip or chip module with the design image (it may also be the comparison of the image plate, or the comparison of other physical information and design information, which will not be repeated in this embodiment), the described The comparison method of the comparison adopts the combination of the overall comparison and the sampling comparison (it may also be the actual method, which will not be repeated in this embodiment), and the following examples are given to illustrate:

During the overall comparison, this embodiment performs a rough overall comparison, focusing on comparing whether the area, outline, module structure, etc. of the chip or chip module are consistent in the two images;

During sampling comparison, for image comparison, calculate and/or set the area that can be used for comparison; select several sampling blocks from the image according to the area that can be used for comparison, and the sum of the areas of several sampling blocks must not exceed the available area. For the comparison area; when the sampling block is selected, the sampling blocks in the two images maintain a corresponding relationship; the selection method of the sampling block includes but is not limited to one or more of the following: random sampling, sampling according to rules, proportional to the pattern density and / or the number of sampling blocks for complexity allocation, which is proportional to the area of the sampling block for graphics density and / or complexity allocation, set; compare the sampling blocks of the corresponding relationship in the two images; comprehensively analyze the comparison results of each sampling block The result of this sampling comparison;

Among them, one method of calculating the area that can be used for comparison is: according to the time required to complete the comparison per unit area and the expected completion time of this comparison, calculate the area that can be used for comparison; the area that can be used for comparison = unit area * expected time to complete this comparison / time required to complete the unit area comparison;

Analyze the results of this image comparison based on the results of the overall comparison and sampling comparison;

During the overall rough comparison, and/or after the sampling block is selected, the resolution and/or the number of pixels of the physical image and/or the design image can be adjusted for the actual image and/or the design image to be compared. Based on the comparison between the real image and the design image;

During the overall rough comparison and/or sampling comparison, the comparison implementation algorithm is adjusted for one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods , Different comparison methods, and different work stages in the comparison.

Scenario Example 9:

For comparing the physical information or the physical image with the design information or the design image (and/or comparing the physical information plate or the physical image plate with the design information plate or the design image plate, which will not be repeated in this embodiment), When the comparison method is automatic comparison through the detection device, for the granularity of the planned comparison this time, according to the resolution of the physical image and/or the design image, and/or the granularity of the planned comparison in the real object The number of pixels included in the image and/or the design image, and the comparison capability of the detection device, adjust the resolution and/or number of pixels of the real image and/or the design image, and based on the adjustment results, the real image and the design Compare the images with the following examples:

The comparison capability of the detection device includes but is not limited to: the detection device needs to complete the comparison under the granularity, the minimum resolution required for the actual image and/or the design image, and/or the granularity needs to include the minimum number of pixels;

The adjustment methods include, but are not limited to: reducing the resolution and/or the number of pixels of the physical image and/or the design image for the granularity of this planned comparison and ensuring the accuracy of the comparison, so that the physical image and the /or the resolution of the design image is reduced, and/or the number of pixels included in the particle size in the physical image and/or the design image is reduced, and is greater than or equal to the comparison capability of the detection device;

For example, in the overall rough comparison, the granularity of the rough comparison in this plan is determined to be 0.1mm (for example), and the resolution of the actual image and design image to be compared is used in this embodiment. The number of pixels is expressed in units, all of which are 20 million/inch (for example). The comparison capability of the detection device is: when the particle size is 0.1mm, the minimum resolution required for the physical image and the design image is 10,000/inch (for example). ), then an adjustment method is: reduce the resolution of the physical image and the design image, so that the resolution of the physical image and the design image is reduced (that is, less than 20 million/inch), and is greater than or equal to the comparison ability of the detection device ( That is, greater than or equal to 10,000/inch). Compare the adjusted real image with the design image.

Scenario Example 10:

For the method of confirming the accuracy of the acquired design information, the following examples are given:

One of the purposes of confirming the accuracy of the acquired design information is to confirm that the content and format of the acquired design information meet the requirements, to confirm that the acquired design information is indeed the design information of the chip, to maintain contact between the design information, etc. To give an example:

For the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , for any and/or set one or more pairwise combinations within the combination, and/or between the three, confirm that the design information of the overlapping part and/or the repeated part is the same, and/or Keeping consistent; the method for confirming that the design information of the overlapping parts and/or repeating parts is the same and/or consistent, including but not limited to one or more of the following: unifying the format of the design information; for overlapping parts Perform image comparison with and/or repeated parts; perform graphic comparison with respect to overlapping parts and/or repeated parts; perform similarity comparison with respect to overlapping parts and/or repeated parts; determine that the similarity is greater than or equal to the thirtieth preset threshold ; Determine the acquired second design information for verification with the first design information, the acquired second design information for verification with the third design information, and the acquired second design information for verification with the fourth design information , in which all or part of one or more of the information is obtained by extracting all or part of the other Obtained by extracting all or part of the information from one or more information formats after conversion; the application scenarios of the method for confirming that the design information of the overlapping part and/or the repeated part is the same and/or consistent, including but not limited to : For the analog-digital hybrid chip, confirm that the gate-level netlist of the digital chip module in it is the same or consistent with the digital chip module part in the transistor-level netlist of the chip after the format is converted to the transistor-level netlist;

For example: if the verification of the first design information and the second design information, the verification of the second design information and the third design information, the verification of the second design information and the fourth design information is used, then the verification of the first design information and the second design information is used. The second design information for verification of the design information (referred to as information 1 in this embodiment), the second design information for verification with the third design information (referred to as information 2 in this embodiment), and the third design information for verification with the fourth design information. 2. In the design information (referred to as information 3 in this embodiment), any two are the same or different design information, that is, the information 1 and the information 2 are the same or different design information, and the information 1 and the information 3 are the same or different design information. are the same or different design information, and the information 2 and information 3 are the same or different design information; the second design information format used for verification with the first design information, the format used for verification with the third design information Any two of the second design information format and the second design information format used for verification with the fourth design information are the same or different formats, that is, information 1 and information 2 are the same or different formats Format, information 1 and information 3 are in the same or different formats, and information 2 and information 3 are in the same or different formats.

Confirm the accuracy of the obtained design information, for the obtained information 1, information 2, and information 3, for any and/or set one or more combinations of the three, within the combination, and/or among the three Confirm that the design information of the overlapping part and/or repeated part is the same and/or consistent (if the acquired information 1, information 2, and information 3 are indeed the design information of the chip, then information 1, information 2, and information 3 are all or part of the second design information, and should meet this requirement); that is, one or more of the following: the acquired information 1, the overlapping part and/or repeated part of the information 2 have the same design information, and/or remain consistent; the overlapping and/or repeating portions of the acquired information 1 and information 3 are identical and/or consistent; the overlapping and/or repeating portions of the acquired information 2 and information 3 The design information is the same and/or consistent; the design information of the overlapping parts and/or repeated parts in the acquired information 1, information 2, and information 3 is the same and/or consistent; the description for the overlapping parts: as obtained Information 1 consists of three parts of information A and B, and acquired information 2 consists of B information, then the overlapping part and/or the repeated part is B information at this time, confirm the overlapping part in acquired information 1 and information 2 and / or the repeated part of the design information is the same and/or consistent, that is: confirm that the B information in the acquired information 1 is the same as the B information in the acquired information 2, and/or is consistent (that is, due to the acquired information 1 , The acquired information 2 all belong to the second design information, then the overlapping part and/or the repeated part B information should be the same and/or consistent).

A method for confirming that the design information of the overlapping parts and/or repeating parts is the same and/or consistent, including but not limited to one or more of the following: unifying the format of the design information; for overlapping parts and/or repeating parts Perform image comparison; perform graphic comparison for overlapping parts and/or repeating parts; perform similarity comparison for overlapping parts and/or repeating parts; determine that the similarity is greater than or equal to the thirtieth preset threshold; Among the second design information verified with the first design information, the acquired second design information used for verification with the third design information, and the acquired second design information used for verification with the fourth design information, one of All or part of the information or information is obtained by extracting all or part of the information from another type or types of information, and/or all or part of the information from one or more types of information is After the information format is converted, all or part of the information is extracted from it; an example is to confirm that the overlapping part and/or repeated part in the obtained information 1 and information 2 are the same and/or consistent, including but not limited to one of the following or Various: If the formats of the acquired information 1 and acquired information 2 are different (for example, one is a transistor-level netlist and the other is a gate-level netlist), unify the design information format (for example, both are unified into a transistor-level netlist) ; Carry out image comparison for overlapping part and/or repeating part; Carry out graphic comparison for overlapping part and/or repeating part; Carry out similarity comparison for overlapping part and/or repeating part (such as information 1 Compare the B information in the obtained information 2 with the B information in the obtained information 2); determine that the similarity is greater than or equal to a preset threshold (this embodiment is referred to as threshold 1, for example, threshold 1 is set to 95%, 100% and other values ); confirm that the information B in the acquired information 1 is obtained by extracting all the information from the acquired information 2 after the format conversion (eg, from a gate-level netlist to a transistor-level netlist)—that is, information B.

Similarly, it is confirmed that the design information of the overlapping part and/or the repeated part in the acquired information 1 and information 3 is the same and/or consistent, and the design information of the overlapping part and/or the repeated part in the acquired information 2 and information 3 is the same , and/or be consistent, the overlapping and/or repeated design information in the obtained information 1, information 2, and information 3 are the same, and/or the method to keep consistent is the same as the above-mentioned confirmation of the obtained information 1 and information 2. The overlapping part and/or repeated part design information is the same, and/or the example method is similar, and the preset thresholds set by the similarity are assumed to be named as threshold 2, threshold 3, and threshold 4, then threshold 1 , Threshold 2, Threshold 3, Threshold 4, and any two can be the same or different.

It should be noted that the above scenario embodiments are only a part of the protection scope of the present invention, and are not intended to limit the protection scope of the present invention, and other more embodiments will not be described again.

It can be seen that this embodiment provides a simple and objective detection basis for the evaluation of the chip or the chip module, improves the objectivity, practicality and comprehensiveness of the evaluation of the autonomy and/or controllability of the chip or the chip module. It can provide evidence for the authenticity of the forensic materials for the evaluation of the autonomy and/or controllability of the chip or chip module, and can be used as a strong support for the evaluation of the autonomy and/or controllability of the chip or chip module.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (34)

1. A method for testing a chip or chip module, the method comprising:

determining the physical information of the chip or the chip module and/or determining the design information of the chip or the chip module;

comparing the real object information with the design information, and/or verifying the design information;

and judging the autonomy and/or the controllability of the chip or the chip module based on the comparison result and/or the verification result.

2. The method of claim 1, wherein the chip includes, but is not limited to, one or more of:

a chip encapsulating one or more dies;

an unpackaged die.

3. The method of claim 1, wherein the chip module includes, but is not limited to, one or more of:

a die in a chip encapsulating one or more dies;

a functional module in the die.

4. The method of claim 1, wherein the physical information includes, but is not limited to, one or more of:

the physical connection relationship between the chip or the chip module and the package substrate, and/or the physical connection relationship between the chip or the chip module and other chips or chip modules, includes but is not limited to one or more of the following expressions: the connection relation real object, a real object diagram describing the connection relation, a table describing the connection relation of the real object, a pin real object name describing the connection relation of the real object and the connection relation of the real object expressed by the name;

Physical information of the package substrate, including but not limited to one or more of the following: a package substrate entity, a package substrate entity circuit or circuit diagram, a package substrate entity layout or layout diagram, a package substrate entity wiring or wiring diagram, a package substrate entity circuit or circuit diagram;

physical information of the chip or chip module, including but not limited to one or more of the following: a chip or chip module real object, a chip or chip module real object layout wiring or layout wiring diagram, a chip or chip module real object circuit or circuit diagram;

wherein the physical information includes, but is not limited to, one or more of the following physical information: all layers, part of layers and one layer, the selection method of the layer number comprises but is not limited to one or more of the following: randomly selecting, selecting according to rules, and setting; for one layer, the physical information includes, but is not limited to, physical information of one or more of the following: the method comprises the following steps of (1) selecting a whole area, a plurality of local areas and a local area, wherein the selection method of the area comprises one or more of the following methods: and (4) randomly selecting, selecting according to a rule and setting.

5. The method according to claim 1 or 4, wherein the physical information is obtained by any one or more of the following methods:

directly obtaining one or more chips or chip modules to be tested and obtaining physical information;

randomly or according to rules, selecting one or more chips or chip modules to be tested and acquiring physical information;

the physical information is directly obtained by one or more methods including but not limited to the following: CT, X-ray, radioactive ray, ultrasonic and nondestructive detection;

opening a cover of the packaged chip and acquiring physical information;

aiming at the situation that the physical connection relation between the chip or the chip module and the packaging substrate and/or the physical connection relation between the chip or the chip module and other chips or chip modules is blocked, the physical connection relation is obtained by one or more of the following modes: CT, X-ray, radioactive ray, ultrasonic, nondestructive detection, delamination, flat grinding, polishing, corrosion, etching, sectioning, dissection and dyeing; the situation that the physical connection relation is blocked includes but is not limited to that the physical connection relation in the flip chip is blocked;

Separating the chip or chip module from the package substrate, and/or separating the chip or chip module from other chips or chip modules, including but not limited to one or more of the following: disconnecting or removing the connecting line, corroding, etching, heating, removing a layer, flatly grinding, polishing, splitting, dissecting and taking down the chip;

acquiring physical information of one or more layers by one or more of the following methods including but not limited to: direct acquisition, acquisition by microscopy and/or microscopic imaging instruments and/or CT and/or X-rays and/or radiation and/or ultrasound and/or non-destructive inspection, delaminating, flat grinding, lapping, polishing, etching, sectioning, dissecting, staining, breaking or removing the connecting line;

acquiring and recording a real object image, an image or a video corresponding to the real object information by a microscope and/or a microscopic imaging instrument and/or a CT and/or X-ray and/or radioactive rays and/or ultrasound and/or nondestructive detection and combination with photographing or/and image acquisition or/and video recording or a direct photographing or/and image acquisition or/and video recording mode; the real object image, video or video is a file, or a plurality of files, or an integral file spliced or synthesized by a plurality of files;

And acquiring the object information and the corresponding object image and image by a microscope and/or a microscopic imaging instrument and/or CT and/or X-ray and/or radioactive ray and/or ultrasonic and/or nondestructive testing, combining with visual observation or directly using the visual observation.

6. The method of claim 5, wherein obtaining or selecting a plurality of chips or chip modules to be tested and obtaining physical information includes but is not limited to one or more of the following:

in order to obtain a plurality of samples, the real object information, or/and the comparison between the real object information and the design information, or/and the autonomy and/or the controllability of the chip or the chip module are subjected to statistical analysis, a plurality of chips or chip modules with the same model are obtained or selected, and the same real object information is obtained from each chip or chip module;

acquiring or selecting a plurality of chips or chip modules with the same type and acquiring different physical information from each chip or chip module or acquiring the same and different physical information simultaneously under the condition that the physical information is acquired in a destructive mode or/and only part of the physical information can be acquired from one chip or chip module;

in order to judge the degree of autonomy and/or the degree of controllability of a chip jointly formed by a plurality of chip modules, the plurality of chip modules in the chip respectively acquire respective physical information and carry out the judgment of the degree of autonomy and/or the degree of controllability, and the degree of autonomy and/or the degree of controllability of the chip are judged based on the result.

7. The method of claim 1, wherein the design information includes, but is not limited to, one or more of:

the design connection relationship between the chip or the chip module and the packaging substrate and/or the design connection relationship between the chip or the chip module and other chips or chip modules includes, but is not limited to, one or more of the following expressions: a design drawing for describing the connection relation, a table for describing the design connection relation, a pin design name for describing the design connection relation and the design connection relation expressed by the name; the design information includes, but is not limited to, design information for one or more of: all layers, part of layers and one layer, the selection method of the layer number comprises but is not limited to one or more of the following: randomly selecting, selecting according to rules, and setting; for one of the layers, the design information includes, but is not limited to, design information for one or more of: the method comprises the following steps of (1) selecting a whole area, a plurality of local areas and a local area, wherein the selection method of the area comprises one or more of the following methods: randomly selecting, selecting according to rules, and setting; the format of the design connection relationship includes, but is not limited to, one or more formats;

Design information for the package substrate, including, but not limited to, one or more of: a package substrate design circuit or circuit diagram, a package substrate design layout or layout diagram, a package substrate design wiring or wiring diagram, a package substrate design circuit or circuit diagram; the design information includes, but is not limited to, design information for one or more of: all layers, part of layers and one layer, the selection method of the layer number comprises but is not limited to one or more of the following: randomly selecting, selecting according to rules, and setting; for one of the layers, the design information includes, but is not limited to, design information for one or more of: the method comprises the following steps of (1) selecting a whole area, a plurality of local areas and a local area, wherein the selection method of the area comprises one or more of the following methods: randomly selecting, selecting according to rules and setting; the format of the design information of the package substrate includes, but is not limited to, one or more formats;

first design information for a chip or chip module, the first design information including, but not limited to, one or more of: a chip or chip module design layout, a chip or chip module design layout or layout; the first design information includes, but is not limited to, design information for one or more of: all layers, part of layers and one layer, the selection method of the layer number comprises but is not limited to one or more of the following: randomly selecting, selecting according to rules, and setting; for one of the layers, the first design information includes, but is not limited to, design information for one or more of: the method comprises the following steps of (1) selecting a whole area, a plurality of local areas and a local area, wherein the selection method of the area comprises one or more of the following methods: randomly selecting, selecting according to rules, and setting; the first design information used for comparison is all design information or part of design information in the first design information; first design information for verification is all or part of the design information in the first design information; the first design information used for comparison and the first design information used for verification are the same or different design information; the format of the first design information includes, but is not limited to, one or more formats; the first design information format used for comparison and the first design information format used for verification are the same or different formats;

Second design information of the chip or chip module, the second design information including but not limited to a schematic diagram and/or a netlist of the chip or chip module, the schematic diagram and/or netlist including but not limited to one or more of the following: the method comprises the following steps of (1) completing a final designed gate-level netlist, a digital chip or digital chip module and a gate-level netlist corresponding to first design information of the digital chip or digital chip module by a schematic diagram, a netlist corresponding to the schematic diagram, a transistor-level netlist, and the digital chip or digital chip module; the second design information includes, but is not limited to, all or part of the design information; the second design information used for verification with the first design information is all design information or part of design information in the second design information; the second design information used for verification with the third design information is all the design information or part of the design information in the second design information; the second design information used for verification with the fourth design information is all or part of the design information in the second design information; any two of the second design information used for verification with the first design information, the second design information used for verification with the third design information, and the second design information used for verification with the fourth design information are the same or different design information; the format of the second design information includes, but is not limited to, one or more formats; any two of the second design information format for verification with the first design information, the second design information format for verification with the third design information, and the second design information format for verification with the fourth design information are in the same or different formats;

Third design information of the chip or the chip module, wherein the third design information comprises but is not limited to a gate-level netlist formed by register transfer level RTL code synthesis of the digital chip or the digital chip module; the third design information includes, but is not limited to, all or part of the design information; third design information used for verification with the second design information is all design information or part of the design information in the third design information; third design information used for verification with fourth design information is all design information or part of design information in the third design information; the third design information used for verification with the second design information and the third design information used for verification with the fourth design information are the same or different design information; the format of the third design information includes, but is not limited to, one or more formats; a third design information format for verification with the second design information, and a third design information format for verification with the fourth design information are in the same format or different formats;

fourth design information for the chip or chip module, the fourth design information including but not limited to RTL code for the digital chip or digital chip module; the fourth design information includes, but is not limited to, all or part of the design information; the fourth design information used for verification with the second design information is all or part of the design information in the fourth design information; fourth design information used for verification with third design information is all design information or part of design information in the fourth design information; the fourth design information used for verification with the second design information and the fourth design information used for verification with the third design information are the same or different design information; the format of the fourth design information includes, but is not limited to, one or more formats; the fourth design information format for verification with the second design information and the fourth design information format for verification with the third design information are the same format or different formats.

8. The method of claim 1, 4 or 7, wherein the comparing the physical information with the design information includes but is not limited to one or more of the following:

comparing the physical connection relation between the chip or the chip module and the packaging substrate and/or the physical connection relation between the chip or the chip module and other chips or chip modules with the corresponding design connection relation, and checking whether the two are consistent;

comparing the physical information of the packaging substrate with the design information of the corresponding packaging substrate, and checking whether the physical information of the packaging substrate is consistent with the design information of the corresponding packaging substrate;

comparing the real object information of the chip or the chip module with the first design information of the corresponding chip or the chip module, and checking whether the real object information of the chip or the chip module is consistent with the first design information of the corresponding chip or the chip module;

the alignment includes, but is not limited to, alignment of one or more of: all layers, part of layers and one layer, the selection method of the layer number comprises but is not limited to one or more of the following: randomly selecting, selecting according to rules, and setting; for one of the layers, the alignment includes, but is not limited to, an alignment of one or more of: the method comprises the following steps of (1) selecting a whole area, a plurality of local areas and a local area, wherein the selection method of the area comprises one or more of the following methods: and (4) randomly selecting, selecting according to a rule and setting.

9. The method of claim 1, wherein before comparing the physical information with the design information, the method further comprises:

and confirming the accuracy of the acquired design information.

10. The method of claim 1, wherein the method of alignment comprises, but is not limited to, one or more of: automatic comparison is carried out through a detection device, and manual comparison is carried out;

when the comparison method is automatic comparison through a detection device, whether the format of the physical information is the format which can be identified and/or used by the detection device needs to be judged; when the format of the physical information is not the format that can be recognized and/or used by the detection device, the format of the physical information needs to be adjusted to the format that can be recognized and/or used by the detection device; the method for adjusting the format of the physical object information to the format that can be recognized and/or used by the detection device includes, but is not limited to, one or more of the following: recording the object information into an object image, and converting the object connection relation into a table describing the object connection relation;

when the comparison method is automatic comparison through a detection device, whether the format of the design information is the format which can be identified and/or used by the detection device needs to be judged; when the format of the design information is not the format that can be recognized and/or used by the detection device, the format of the design information needs to be adjusted to the format that can be recognized and/or used by the detection device; the method of adjusting the format of the design information to a format that can be recognized and/or used by the detection device includes, but is not limited to, one or more of the following: converting the design information into a design image and converting the design connection relation into a form describing the design connection relation; the design image includes but is not limited to an image in which the design information is saved or/and converted or/and recorded into an image format;

The method for judging whether the format of the physical information and/or the design information is the format that can be identified and/or used by the detection device includes, but is not limited to, one or more of the following: the judgment is automatically carried out through a detection device and is carried out manually;

the method for adjusting the format of the physical information and/or the design information to the format that can be recognized and/or used by the detection device includes, but is not limited to, one or more of the following: the automatic adjustment is realized through a detection device, and the manual adjustment is realized.

11. The method according to claim 1, wherein when the physical information is compared with the design information, the correspondence between the physical information and the design information includes but is not limited to one or more of the following:

correspondence of the same layer;

the corresponding relation of the same area;

corresponding relation of the same position;

the corresponding relationship of the same position proportion includes, but is not limited to, one or more of the following: the ratio of the position in the physical information and/or the physical image to the distance between each point in the whole physical information and/or the physical image is the same as the ratio of the position in the design information and/or the design image to the distance between each point in the whole design information and/or the design image, and then the physical information and/or the physical image position is in corresponding relation with the design information and/or the design image position; after the whole real object information and/or the whole real object image and/or the whole design information and/or the whole design image are scaled in equal proportion, when the whole real object information and/or the whole real object image and/or the whole design information and/or the whole design image are overlapped, the positions are also overlapped, and then the positions of the real object information and/or the real object image and the design information and/or the design image are in corresponding relation;

And the corresponding relation of the same pin names.

12. The method of claim 1, wherein when comparing the physical information or the physical image with the design information or the design image, the method further comprises: respectively splitting the physical information or the physical image and the corresponding design information or the design image into one or more plates, keeping the corresponding relation between the plates of the physical information or the physical image and the plates of the design information or the design image, respectively carrying out comparison aiming at each plate, and analyzing the comparison result of each plate by integrating the comparison result of each plate;

where splitting into one or more panels includes, but is not limited to, one or more of: the real object information or the real object image and the comparison content of the design information or the design image are concentrated in one or more local areas and are split into one or more plates according to the concentrated areas; the physical information or the physical image and the design information or the design image have large figure size difference in different areas, and are split into one or more plates according to different figure sizes or different size ranges;

after the plates are separated, if some plates have no needed comparison content, the comparison of the plates is omitted or not omitted, and when the comparison of the plates is omitted, the comparison results of all the plates are synthesized, and the comparison results are analyzed, and the comparison results are not included in the plates.

13. The method of claim 1, wherein the physical information or physical image is compared with the design information or design image, and/or the physical information plate or physical image plate is compared with the design information plate or design image plate, and the comparison manner includes but is not limited to one or more of the following: overall comparison, detailed comparison and sampling comparison;

the alignment content of the alignment includes, but is not limited to, one or more of the following: connection relationships, geometries, geometry characteristics;

the comparison fineness of the comparison is expressed by using granularity, the comparison fineness is related to a comparison method, a method, contents and purposes, the granularity comprises but is not limited to the accuracy of comparison of the comparison contents, and the minimum limit of the granularity comprises but is not limited to one or more of the following: a minimum figure in the corresponding information and/or image, a minimum size in the corresponding information and/or image, a minimum area in the corresponding information and/or image, a figure set according to the corresponding information and/or image, a size set according to the corresponding information and/or image, and an area set according to the corresponding information and/or image.

14. The method according to claim 1 or 10, wherein the comparing of the physical information or physical image with the design information or design image and/or the comparing of the physical information plate or physical image plate with the design information plate or design image plate further comprises but is not limited to one or more of the following:

adjusting the resolution and/or the number of pixels of the real object image and/or the design image and/or the real object image plate and/or the design image plate aiming at the real object image and/or the design image and/or the real object image plate and/or the design image plate to be compared, and comparing the real object image and the design image and/or the real object image plate and the design image plate on the basis of the adjustment result;

when the comparison method is automatic comparison through the detection device, aiming at the granularity of the planned comparison, the resolution and/or the number of pixels of the real object image and/or the design image and/or the real object image plate and/or the design image plate are/is adjusted according to the resolution of the real object image and/or the design image and/or the resolution of the real object image and/or the design image plate and/or the granularity of the planned comparison and the comparison capability of the detection device, and the comparison is carried out on the real object image and the design image and/or the real object image plate and the design image plate on the basis of the adjustment result;

The alignment capability of the detection device includes but is not limited to: the detection device is used for completing comparison under the granularity, aiming at the minimum resolution required by the object image and/or the design image and/or the object image plate and/or the design image plate respectively, and/or the minimum pixel number required to be contained by the granularity;

methods of such adjustments include, but are not limited to: aiming at the granularity of planned comparison, on the premise of ensuring accurate comparison, the resolution and/or the pixel number of the real object image and/or the design image and/or the real object image plate and/or the design image plate are reduced, so that the resolution of the real object image and/or the design image and/or the real object image plate and/or the design image plate is reduced, and/or the pixel number contained in the granularity of the real object image and/or the design image and/or the real object image plate and/or the design image plate is reduced, and is more than or equal to the comparison capacity of the detection device.

15. The method of claim 13, wherein the global alignment is used, including but not limited to one or more of the following:

comparing the whole real object information or the real object image with design information or a design image, and/or comparing the whole real object information plate or the real object image plate with a design information plate or a design image plate;

The global alignment includes, but is not limited to, one or more of the following: overall fine comparison and overall rough comparison;

when the whole fine alignment is carried out, the granularity of the alignment reaches the minimum limit;

and when the overall rough alignment is carried out, the granularity of the alignment is larger than the minimum limit, and the alignment content is embodied by including but not limited to one or more of the following: connection relation, chip area, chip outline, package substrate area, package substrate outline, graphic profile, graphic distribution characteristics and module structure;

the application cases of the overall fine comparison between the whole physical information or physical image and the design information or design image include, but are not limited to, one or more of the following: the time required for finishing the integral fine comparison is less than or equal to a first preset threshold; the pixel number of the real object image is less than or equal to a second preset threshold; the number of pixels of the design image is less than or equal to a third preset threshold; the resolution ratio of the object image is less than or equal to a fourth preset threshold; the resolution of the design image is less than or equal to a fifth preset threshold; the area of the real object information and/or the real object image and/or the design information and/or the design image is less than or equal to a sixth preset threshold; the area of the minimum graph in the physical information and/or the physical image and/or the design information and/or the design image is larger than or equal to a seventh preset threshold;

The application cases of the overall fine comparison between the whole real object information plate or real object image plate and the design information plate or design image plate include, but are not limited to, one or more of the following: the time required for finishing the whole fine comparison of the plate is less than or equal to an eighth preset threshold; the pixel number of the real object image plate is less than or equal to a ninth preset threshold; the number of pixels of the designed image plate is less than or equal to a tenth preset threshold; the resolution ratio of the real object image plate is less than or equal to an eleventh preset threshold; the resolution of the designed image plate is less than or equal to a twelfth preset threshold; the area of the real object information plate and/or the real object image plate and/or the design information plate and/or the design image plate is less than or equal to a thirteenth preset threshold; the area of the minimum graph in the physical information plate and/or the physical image plate and/or the design information plate and/or the design image plate is larger than or equal to a fourteenth preset threshold;

suitable cases for the whole physical information or physical image and the whole design information or design image to be roughly compared include, but are not limited to, one or more of the following: the time required for finishing the integral fine comparison is more than or equal to the fifteenth preset threshold; the pixel number of the real object image is more than or equal to a sixteenth preset threshold; the number of pixels of the design image is greater than or equal to a seventeenth preset threshold; the resolution ratio of the object image is greater than or equal to an eighteenth preset threshold; the resolution of the design image is greater than or equal to a nineteenth preset threshold; the area of the physical information and/or the physical image and/or the design information and/or the design image is larger than or equal to a twentieth preset threshold; the area of the minimum graph in the physical information and/or the physical image and/or the design information and/or the design image is less than or equal to a twenty-first preset threshold; the overall rough comparison is combined with the other comparison modes;

The application cases of the overall rough comparison between the whole physical information plate or physical image plate and the designed information plate or designed image plate include, but are not limited to, one or more of the following: the time required for completing the overall fine comparison of the plates is more than or equal to the twenty-second preset threshold; the number of pixels of the real object image plate is greater than or equal to a twenty-third preset threshold; the number of pixels of the designed image plate is greater than or equal to a twenty-fourth preset threshold; the resolution ratio of the real object image plate is greater than or equal to a twenty-fifth preset threshold; the resolution of the designed image plate is greater than or equal to a twenty-sixth preset threshold; the area of the real object information plate and/or the real object image plate and/or the design information plate and/or the design image plate is more than or equal to a twenty-seventh preset threshold; the area of the minimum graph in the real object information plate and/or the real object image plate and/or the design information plate and/or the design image plate is less than or equal to a twenty-eighth preset threshold; the overall rough alignment is combined with the other alignment methods.

16. The method of claim 13, wherein the refined alignment is adopted, including but not limited to one or more of the following:

Aiming at the comparison of the real object information or the real object image with the design information or the design image and/or the comparison of the real object information plate or the real object image plate with the design information plate or the design image plate, and aiming at one or more regions including but not limited to the following regions, gradually reducing the comparison region and/or reducing the granularity, carrying out one or more comparisons: regions which do not pass through the whole comparison, regions which are interested or considered as critical after the whole comparison passes through, regions which realize complexity, regions which are critical in function and the whole region;

when the one or more times of comparison is carried out, the refinement limit is that the comparison area is reduced to the minimum limit of the minimum graph and/or the minimum size and/or the minimum granularity of the corresponding information and/or the image and/or the information plate and/or the image plate, and the refinement limit is required to be reached or not to be reached by the refinement comparison.

17. The method of claim 13, wherein the sampling alignment is adopted, including but not limited to one or more of the following:

calculating and/or setting an area which can be used for comparison aiming at the comparison of the real object information or the real object image and the design information or the design image and/or the comparison of the real object information plate or the real object image plate and the design information plate or the design image plate;

Selecting a plurality of sampling blocks from the real object information or the real object image or the real object information plate or the real object image plate according to the area available for comparison, wherein the sum of the areas of the plurality of sampling blocks does not exceed the area available for comparison;

selecting a plurality of sampling blocks from design information or design images or design information plates or design image plates according to the areas available for comparison, wherein the sum of the areas of the sampling blocks is not more than the area available for comparison;

the sampling blocks selected from the physical information or the physical image or the physical information plate or the physical image plate keep corresponding relation with the sampling blocks selected from the design information or the design image or the design information plate or the design image plate;

the selection method of the sampling block includes but is not limited to one or more of the following: random sampling, wherein sampling is carried out according to a rule, the number of sampling blocks is distributed in direct proportion to the density and/or complexity of the graph, and the area of the sampling blocks is distributed in direct proportion to the density and/or complexity of the graph;

comparing the sampling blocks in the real object information or the real object image or the real object information plate or the real object image plate with the sampling blocks in the corresponding design information or design image or design information plate or design image plate;

Analyzing the sampling comparison result by synthesizing the comparison result of each sampling block;

the fine limit of the sampling comparison is that the granularity has reached the minimum limit, and the sampling comparison needs to reach or does not need to reach the fine limit.

18. The method of claim 1 or 17, wherein the area available for alignment is calculated, including but not limited to one or more of:

calculating the area available for comparison according to the time required for completing the comparison of unit area and the time expected to be completed by the comparison aiming at the real object information or the real object image or the real object information plate or the real object image plate and the design information or the design image or the design information plate or the design image plate;

the calculation methods include, but are not limited to: the area available for alignment is unit area/time expected to complete the alignment/time required to complete the unit area alignment.

19. The method according to claim 13 or 16, wherein the minimum pattern and/or minimum size and/or minimum area obtaining method includes, but is not limited to, one or more of the following:

obtaining the minimum size from the corresponding design information and/or physical information and/or design information plate and/or physical information plate, wherein the obtaining method includes but is not limited to obtaining one or more of the following information: minimum line width, feature size, process, gate length, channel length;

Further analyzing and obtaining a minimum graph and/or a minimum area based on the minimum size;

identifying a minimum figure and/or a minimum size and/or a minimum area in the corresponding design image and/or physical image and/or design image slab and/or physical image slab.

20. The method of claim 10, 12, 13, 15, 16, or 17, wherein the method further comprises adjusting the corresponding resolution and/or number of pixels for alignment under conditions including but not limited to one or more of:

before image comparison starts and/or after plates are split and/or during overall comparison, the resolution and/or the number of pixels of the real object image and/or the design image and/or the real object image plates and/or the design image plates are adjusted and then compared;

after the area is subjected to thinning, comparison and reduction and/or the granularity is reduced, aiming at the area subjected to thinning and/or reduction, the resolution and/or the pixel number of the corresponding image are adjusted and then compared;

after the sampling blocks are selected, the resolution and/or the pixel number of the corresponding image are adjusted and compared according to each sampling block.

21. The method of claim 1, or 10, or 12, or 13, or 15, or 16, or 17, further comprising:

The algorithm for implementing the alignment is adjusted for one or more of the following situations, including but not limited to: different comparison purposes, different comparison contents, different comparison methods, different comparison modes and different working stages in comparison.

22. The method according to claim 1 or 7, wherein the verifying the design information includes but is not limited to one or more of the following:

verifying the first design information of the chip or the chip module and the corresponding second design information, wherein the verification method comprises but is not limited to LVS (linear variable differential signal) inspection or verification;

verifying the second design information of the chip or the chip module with the corresponding third design information, and/or verifying the second design information of the chip or the chip module with the corresponding fourth design information, wherein the verification method comprises but is not limited to form verification;

and verifying the third design information of the chip or the chip module and the corresponding fourth design information, wherein the verification method comprises but is not limited to formal verification.

23. The method of claim 1, wherein before verifying the design information, the method further comprises:

and confirming the accuracy of the acquired design information.

24. The method of claim 1, or 7, or 9, or 23, wherein the method of confirming the accuracy of the acquired design information includes, but is not limited to, one or more of:

confirming that the design information of the overlapped part and/or the repeated part is the same and/or consistent with the acquired first design information for comparison and the acquired first design information for verification; the method for confirming that the design information of the overlapped part and/or the repeated part is the same and/or consistent includes but is not limited to one or more of the following: unifying the acquired first design information format for comparison with the acquired first design information format for verification, carrying out image comparison on an overlapped part and/or a repeated part, carrying out graph comparison on the overlapped part and/or the repeated part, carrying out similarity comparison on the overlapped part and/or the repeated part, determining that the similarity is more than or equal to a twenty-ninth preset threshold, and determining that all or part of information of one information is obtained by extracting all or part of information from another information and/or all or part of information of one information is obtained by extracting all or part of information from another information after the conversion of another information format in the acquired first design information for comparison and the acquired first design information for verification;

Unifying the acquired first design information format for comparison with the acquired first design information format for verification; the method for unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, and converting both the two formats into a third format; the third format is a format except the acquired first design information format for comparison and the acquired first design information format for verification;

confirming that the design information of the overlapped part and/or the repeated part is the same and/or consistent with the combination interior of one or more pairwise combinations arbitrarily and/or set in the acquired second design information for verifying the first design information, the acquired second design information for verifying the third design information and the acquired second design information for verifying the fourth design information; the method for confirming that the design information of the overlapped part and/or the repeated part is the same and/or is consistent includes but is not limited to one or more of the following: unifying the design information format; performing image comparison on the overlapped part and/or the repeated part; performing graph comparison on the overlapped part and/or the repeated part; performing similarity alignment for overlapping and/or repeated portions; determining that the similarity is greater than or equal to a thirtieth preset threshold; determining the second design information acquired for verification with the first design information, the second design information acquired for verification with the third design information, and the second design information acquired for verification with the fourth design information, wherein all or part of the information of one or more kinds of information is obtained by extracting all or part of the information from another kind of information or a plurality of kinds of information, and/or wherein all or part of the information of one or more kinds of information is obtained by converting another kind of information or a plurality of kinds of information and extracting all or part of the information from the converted information; application scenarios of the method for confirming that the design information of the overlapped part and/or the repeated part is the same and/or is consistent include, but are not limited to: for the analog-digital mixed chip, after the gate-level netlist of the digital chip module is confirmed to be converted into the transistor-level netlist in a format, the content of the gate-level netlist is the same as or keeps the same with that of the digital chip module in the chip-transistor-level netlist;

Unifying the design information formats of the obtained second design information for verifying the first design information, the obtained second design information for verifying the third design information and the obtained second design information for verifying the fourth design information, and optionally and/or in any one or more combinations of the three, the combination of the three and/or the combination of the three; the method for unifying the design information format includes but is not limited to one or more of the following: converting one format of two formats into another format between the combined interiors of two combinations, converting both formats into a third format between the combined interiors of two combinations, unifying the formats into one format of the three formats between the three combinations, converting the three formats into a fourth format between the three combinations, and converting the fourth format between the three formats into a format other than the design information format of the three combinations;

confirming that the overlapping part and/or the repeated part of the design information is the same and/or consistent with the third design information which is acquired for verification with the second design information and the third design information which is acquired for verification with the fourth design information; the method for confirming that the design information of the overlapped part and/or the repeated part is the same and/or is consistent includes but is not limited to one or more of the following: unifying the third design information format for verifying the third design information and the fourth design information format, performing image comparison on the overlapped part and/or the repeated part, performing graph comparison on the overlapped part and/or the repeated part, performing similarity comparison on the overlapped part and/or the repeated part, and determining that the similarity is more than or equal to a thirty-one preset threshold, determining all or part of the acquired third design information used for verification with the second design information and the acquired third design information used for verification with the fourth design information, wherein all or part of information of one information is obtained by extracting all or part of information from another information, and/or all or part of information of one information is obtained by extracting all or part of information from another information after being converted by another information format;

Unifying the third design information format obtained for verification with the second design information and the third design information format obtained for verification with the fourth design information; the method for unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, and converting both the two formats into a third format; the third format is a format other than the third design information format acquired for verification with the second design information and the third design information format acquired for verification with the fourth design information;

confirming that the overlapping part and/or the repeated part of the design information is the same and/or consistent with the acquired fourth design information for verification with the second design information and the acquired fourth design information for verification with the third design information; the method for confirming that the design information of the overlapped part and/or the repeated part is the same and/or is consistent includes but is not limited to one or more of the following: unifying the acquired fourth design information format for verification with the second design information and the acquired fourth design information format for verification with the third design information, performing image comparison on the overlapped part and/or the repeated part, performing graph comparison on the overlapped part and/or the repeated part, performing similarity comparison on the overlapped part and/or the repeated part, and determining that the similarity is more than or equal to a thirty-second preset threshold, determining all or part of the acquired fourth design information used for verification with the second design information and the acquired fourth design information used for verification with the third design information, wherein all or part of information of one information is obtained by extracting all or part of information from another information, and/or all or part of information of one information is obtained by extracting all or part of information from another information after being converted by another information format;

Unifying the obtained fourth design information format for verification with the second design information and the obtained fourth design information format for verification with the third design information; the method for unifying the formats of the two includes but is not limited to one or more of the following: converting one of the two formats into the other format, and converting both the two formats into a third format; the third format is a format other than the fourth design information format acquired for verification with the second design information, the fourth design information format acquired for verification with the third design information;

confirming that the gate-level netlist in the obtained second design information is a back-end netlist and/or a non-front-end netlist;

confirming that the gate-level netlist in the obtained third design information is a front-end netlist and/or a non-back-end netlist;

the method for confirming that the gate-level netlist in the obtained second design information is a back-end netlist and/or a non-front-end netlist and/or confirming that the gate-level netlist in the obtained third design information is a front-end netlist and/or a non-back-end netlist includes but is not limited to one or more of the following: searching keywords; comparing the similarity between the obtained gate-level netlist in the second design information and the obtained gate-level netlist in the third design information, and/or determining that the similarity is less than or equal to a thirty-third preset threshold;

Confirming the obtained RTL code as register transfer level description and/or non-other level description, wherein the other level description comprises but is not limited to gate level description;

and confirming the accuracy of the acquired design information through the file suffix name of the acquired design information.

25. The method according to claim 1 or 7, wherein when verifying the design information, the correspondence between the design information includes but is not limited to one or more of the following: the corresponding relation of the same modules, the corresponding relation of the same units, the corresponding relation of the same functions, the corresponding relation of the same logics and the corresponding relation of the same connections.

26. The method of claim 1 or 7, wherein the verification is performed by confirming the settings or/and conditions of the verification, and the method for confirming the settings or/and conditions of the verification includes but is not limited to one or more of the following:

when the verification is the LVS verification, the setting or/and the condition of the LVS verification is confirmed by analyzing the design information aiming at the LVS verification or/and checking the design description corresponding to the design information aiming at the LVS verification; the LVS verified settings or/and conditions include, but are not limited to, one or more of: the system comprises a top layer design, a top layer unit, a top layer logic and a top layer module;

When the verification is formal verification, confirming the setting or/and the condition of the formal verification by analyzing the design information of the formal verification target or/and checking the design description corresponding to the design information of the formal verification target; the settings or/and conditions for the formal verification include, but are not limited to, one or more of: top layer design, top layer unit, top layer logic, top layer module, constant setting;

verifying the top-level design and/or top-level cells and/or top-level logic and/or top-level modules in the settings or/and conditions, the top-level design and/or top-level cells and/or top-level logic and/or top-level modules being related to the design information targeted for verification and being all or part of the design information of the chip or chip module; the top-level design and/or top-level unit and/or top-level logic and/or top-level module of the verification setup are application scenarios of design information of a part of the chip, including but not limited to: for an analog-digital hybrid chip, a top-level design and/or a top-level unit and/or a top-level logic and/or a top-level module in a formal verification setting or/and condition are digital chip modules in the analog-digital hybrid chip.

27. The method according to claim 1 or 7, wherein, when the verification is carried out, one or more results or/and reports of the verification are comprehensively analyzed to judge whether the verification passes; when the verification is formal verification, the result or/and report of the verification includes, but is not limited to, one or more of the following: and comparing the point matching check result, the verification result and the verification report.

28. The method according to claim 1, 4 or 7, wherein the determining the autonomy and/or controllability of the chip or chip module based on the comparison result and/or verification result includes but is not limited to one or more of the following:

determining comparison types and/or verification types required for judging the degree of autonomy and/or the degree of controllability of the chip or the chip module according to the characteristics of the chip or the chip module;

aiming at the required comparison types and/or verification types, distributing respective corresponding scores of the various required comparisons and/or verifications according to the difficulty and/or the key degree of links represented by the various types;

for each of the required comparisons and/or verifications, the chip or the chip module obtains a score corresponding to the comparison and/or verification when the comparison and/or verification is actually carried out and passed;

for each of the required comparisons and/or verifications, the chip or chip module does not obtain a score corresponding to the comparison and/or verification when actual development fails or is not actually performed;

combing out invalid scores from scores corresponding to various comparisons and/or verifications obtained by the chip or the chip module by integrating various actually-developed comparison and/or verification results;

Removing invalid scores from the scores corresponding to various comparisons and/or verifications obtained by the chip or the chip module, taking the rest scores as valid scores, summing the valid scores, and taking the summed result as the final score of the chip or the chip module;

and judging the degree of autonomy and/or controllability of the chip or the chip module according to the final score of the chip or the chip module.

29. The method according to claim 28, wherein said combining the results of the various alignments and/or verifications actually carried out, and combing out invalid scores from the scores corresponding to the various alignments and/or verifications obtained by said chip or chip module, includes but is not limited to one or more of the following:

when the physical information of the chip or the chip module is not compared with the corresponding first design information, the corresponding score obtained by the chip or the chip module when each of the required verifications is actually carried out and passes is an invalid score;

when the first design information of the chip or the chip module and the corresponding second design information are not verified, the corresponding score obtained when the verification of the second design information of the chip or the chip module and the corresponding third design information is actually carried out and passed is an invalid score;

When the first design information of the chip or the chip module and the corresponding second design information do not pass the verification, the corresponding score obtained when the verification of the second design information of the chip or the chip module and the corresponding fourth design information is actually carried out and passes is an invalid score;

when the verification of the first design information and the corresponding second design information of the chip or the chip module fails, the corresponding score obtained when the verification of the third design information and the corresponding fourth design information of the chip or the chip module is actually carried out and passed is an invalid score;

when the second design information of the chip or the chip module and the corresponding third design information are not verified and the second design information of the chip or the chip module and the corresponding fourth design information are not verified, a corresponding score obtained when the verification of the third design information of the chip or the chip module and the corresponding fourth design information is actually carried out and passed is an invalid score.

30. The method of claim 1, 4 or 7, wherein for a chip consisting of one or more chip modules, the determination of the autonomy and/or controllability of the chip includes but is not limited to one or more of the following:

Aiming at each chip module in the chip, distributing corresponding weight according to the difficulty and/or the key degree realized by each chip module, wherein the score of the chip is a weighted sum value of the scores of each chip module, and judging the autonomy and/or the controllability of the chip based on the weighted sum value;

the distribution of the corresponding weight needs to ensure that when a chip with a given function consists of one or more chip modules under different schemes, the scores corresponding to the same degree of autonomy and/or controllability are the same; the implementation method for ensuring that the scores corresponding to the same degree of autonomy and/or controllability are the same includes but is not limited to one or more of the following: weight distribution normalization, namely under different schemes, the sum of the weights of all chip modules of the chip with the set function is the same, when the autonomy and/or the controllability of all chip modules are judged to be the highest, the scores of all chip modules are the same, and the full scores of all chip modules are the same;

aiming at each chip module in the chip, when the physical information of each chip module is determined, ensuring that the physical information of each chip module is not overlapped and/or repeated and the sum of the physical information of each chip module is the physical information of the whole chip;

Aiming at each chip module in the chip, when the design information of each chip module is determined, the design information of each chip module is ensured not to be overlapped and/or repeated, and the sum of the design information of each chip module is the design information of the whole chip;

the real object information and the design information of each chip module keep corresponding relation.

31. The method of claim 30, wherein when there are chip modules of the same type among the chip modules constituting the chip, the chip modules of the same type are collectively regarded as a whole chip module for detection, and a score is calculated once and a weight is assigned; the processing method for uniformly considering the chip modules of the same model as a whole chip module for detection includes but is not limited to one or more of the following:

determining the sum of the physical information of the chip modules with the same model as the physical information of the detected whole chip module, determining the sum of the design information of the chip modules with the same model as the design information of the detected whole chip module, and calculating a score for the detected whole chip module;

Randomly or according to rules, selecting a chip module from the chip modules with the same model, and taking the score of the chip module as the score of the detected whole chip module;

and selecting all or part of the chip modules according to the chip modules with the same model, respectively calculating the scores of the selected chip modules, and taking the average value of the scores of the selected chip modules as the score of the detected whole chip module.

32. The method of claim 30, wherein the method of determining the autonomy and/or controllability of a chip comprised of one or more chip modules is applicable to a range including, but not limited to, one or more of:

the analog-digital mixed chip is composed of a digital chip module and an analog chip module;

a multi-chip module MCM formed from a plurality of dies packaged together;

a radio frequency front end module.

33. An apparatus for testing a chip or chip module, the apparatus comprising:

the information determining module is used for determining the physical information of the chip or the chip module and/or determining the design information of the chip or the chip module;

the information processing module is used for comparing the physical information with the design information and/or verifying the design information;

And the judging module is used for judging the autonomy and/or the controllability of the chip or the chip module based on the comparison result and/or the verification result.

34. An apparatus for testing a chip or chip module, the apparatus comprising: a processor and a memory for storing a computer program capable of running on the processor,

wherein the processor is adapted to perform the steps of the method of any one of claims 1-32 when running the computer program.

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