Memory initialization method for supporting heterogeneous CPU in Qemu simulator
Technical Field
The invention relates to a memory initialization method for supporting heterogeneous CPUs in a Qemu simulator, which is used for a domestic AI acceleration card simulator and belongs to the technical field of computation.
Background
Qemu (full Quick Emulator) is a system-wide simulator and virtual machine monitor (Virtual Machine Monitor, VMM) that is open-source and plays an important role in hardware development and basic software development. The Qemu simulates virtual memory, and the core is to maintain a virtual machine physical address space, wherein the address space is convenient for Qemu management, memory is provided for a virtual machine side, display and export are convenient, and a memory view is provided for a platform side.
In current Qemu, the memory is initially designed mainly for a single architecture, and the memory is initialized and allocated for the CPU of the single architecture starting from 0. Therefore, the memory management of the existing Qemu simulator is performed for a single CPU architecture, and cannot support heterogeneous CPU operation, mainly the memory layout problem. From the Qemu perspective, the physical address of the memory range (memory_region) of the virtual machine under a single architecture is laid out from 0, and the physical address is increased according to the size, and in the heterogeneous mode, the memory range for heterogeneous CPUs is planned, and the two cannot have cross conflict.
Disclosure of Invention
The invention aims to provide a memory initialization method for supporting heterogeneous CPUs in a Qemu simulator, which aims to solve the problem of initializing memories at bottom layers of different types of CPUs when the same Qemu simulator simulates heterogeneous CPUs at the same time.
In order to achieve the above objective, the present invention provides a memory initialization method for supporting heterogeneous CPUs in a Qemu simulator, which aims at a heterogeneous model of x86+shenwei AI, and includes the following steps:
Step 1, initializing the memory of the X86CPU from the address 0 according to a Qemu default initialization mode, wherein the specific flow is as follows:
Step 11, analyzing the condition of the memory to be initialized according to the parameters in the pc_init1;
Step 12, calling the function cpu_exec_init_all to initialize the io and the memory_map_init respectively, wherein the io_mem_init is responsible for creating a memory area of the io, and the memory_map_init is used for creating two parts of memory address spaces of the address_space_memory and the system_memory;
step 13, calling pc_memory_init to initialize the memory needed in X86;
Step2, analyzing the use condition of the X86 and Shenwei architecture on the address range, wherein the memory range STARTs from sw_phys_addr_start (1 < < 59), and initializing the memory of the Shenwei AI processor, and the specific flow is as follows:
step 21, newly creating a memory area (MemoryRegion) type pointer ram;
Step 22, assigning a name airam-xx for each core group continuous segment storage control;
step 23, setting the address range of each continuous segment memory control;
step 24, calling a memory_region_allocation_system_memory function to allocate four continuous memory areas;
step 25, calling a function memory_region_add_display to add sub-regions to the four continuous memory regions newly created in step 24;
step 26, completing the allocation of the continuous memory;
step 27, designating a cross section name as ram_cross;
Step 28, setting an address range of cross section memory control;
Step 29, calling a memory_region_allocation_system_memory function to allocate a cross section memory area;
Step 210, calling a function memory_region_add_display to add a sub-region to the cross-section memory region created in step 29;
Step 211, completing the cross section memory allocation.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
The memory initialization method supporting heterogeneous CPUs in the Qemu simulator is oriented to the Qemu simulator with coexistence of X86 and Shenwei AI, the memories of CPUs of different architectures are isolated in a memory range isolation mode, and initialization is carried out in different modes, so that the memory initialization of the heterogeneous CPUs is realized, and a foundation is laid for realizing full-system simulation of the X86+AI accelerator card in the same Qemu simulation environment.
Detailed Description
The invention provides a memory initialization method for supporting heterogeneous CPU in Qemu simulator, which simulates two large memories, namely X86 memory and Shenwei AI memory (including cross section);
in the simulator, the X86 memory range (memory_region) begins from 0 address by adopting Qemu default allocation mode, and the memory on the card must be separated from the X86 memory and cannot collide with various IO addresses;
in order to support the operation of the X86 and Shenwei AI processors in the simulator, the initialization of the corresponding memories of the two CPUs are as follows:
the memory initialization of the X86CPU starts from address 0 and is performed according to the Qemu default initialization mode:
1) In pc_init1, firstly analyzing the condition of the memory to be initialized according to parameters (host_type, ram_size);
2) The method comprises the steps that the function cpu_exec_init_all calls io_mem_init and memory_map_init to initialize io and memory respectively;
3) io_mem_init is mainly responsible for creating the memory area of io (MemoryRegion);
4) memory_map_init is mainly used for creating two parts of memory address spaces, namely address_space_memory and system_memory;
5) Finally, the pc_memory_init is called to initialize the memory needed in X86.
After the memory of the X86CPU is initialized according to a default path, the memory of the Shenwei AI processor needs to be initialized, firstly, the use condition of the X86 and Shenwei architecture on the address range is analyzed, and finally, the memory range of Shenwei AI STARTs from SW_PHYS_ADDR_START (1 < < 59), and the on-card memory initialization flow is as follows:
1) Newly creating a memory area (MemoryRegion) type pointer ram;
2) Assigning a name airam-xx to each core group continuation segment store;
3) Setting the address range of each continuous segment memory control;
4) Calling a memory_region_allocation_system_memory function to allocate four continuous memory areas;
5) Calling a function memory_region_add_display to add sub-regions for the newly built four continuous memory regions, namely, associating with memory control;
6) Completing the allocation of the continuous section memory;
7) Designating the name of the cross section as ram_cross;
8) Setting an address range of the cross section memory control;
9) Calling a memory_region_allocation_system_memory function to allocate a cross-section memory area;
10 Calling a function memory_region_add_display to add a sub-region for the newly built cross-section memory region;
11 Completing the cross-section memory allocation.
Four continuous sections and one cross section are respectively distributed in the flow, and a section of memory is independently distributed in the cross section for facilitating the processing.
In order to facilitate a better understanding of the present invention, the terms used herein will be briefly explained below:
Qemu Quick Emulator, a full system simulator with a source;
The isomerism mainly means that the CPU adopts different instruction sets and the architecture design is different.
AI ARTIFICIAL INTELLIGENCE, artificial intelligence.
Accelerator card is a specially designed processor product for accelerating algorithm execution, and in the AI field, the accelerator card is generally connected with a server by adopting a PCIe interface.
Management core and main core under many-core architecture, the core of CPU having many processing cores specially responsible for management function is called management core, also called main core.
The core specially responsible for the operation function in the numerous processing cores owned by the cpu is called an operation core, also called a slave core.
When the memory initialization method supporting the heterogeneous CPU in the Qemu simulator is adopted, the Qemu simulator facing the coexistence of X86 and Shenwei AI isolates the CPU memories of different architectures in a memory range isolation mode and initializes the memories by different modes, so that the memory initialization of the heterogeneous CPU is realized, and a foundation is laid for realizing the full-system simulation of the X86+AI acceleration card in the same Qemu simulation environment.
The above embodiments are provided to illustrate the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.