CN114584085A - Amplifier circuit and electronic device - Google Patents

Abstract

The present application relates to the technical field of amplifiers, and discloses an amplifier circuit and an electronic device. The amplifier circuit includes a push-pull circuit and an amplifier circuit, wherein the push-pull circuit includes a first transistor, a second transistor, and a level shift circuit. The first end of a transistor is input with a power supply signal, and the second end of the first transistor is used for output; the first end of the second transistor is connected to the second end of the first transistor, and the second end of the second transistor is grounded; the level shift circuit , the first end of the level shift circuit is connected to the control end of the first transistor, and the second end of the level shift circuit is connected to the control end of the second transistor. The amplifying circuit is connected to the control terminal of the second transistor for generating an amplified signal under the action of the input signal, and inputting the amplified signal to the control terminal of the second transistor. In the above manner, the gain and amplification speed of the input signal processing by the amplifier circuit can be improved.

Description

Amplifier circuits, electronic equipment

technical field

The present application relates to the technical field of amplifiers, and in particular, to an amplifier circuit and an electronic device.

Background technique

In analog circuit chips, the amplifiers include single-tube amplifiers, such as Common Source amplifiers and Common Gate amplifiers; the types of multi-tube amplifiers include push-pull amplifiers, differential amplifiers, etc. Among them, the push-pull structure amplifier is due to its The structure is simple and the gain is large, and it has become a popular research direction.

In the current scheme, the optimal performance of the single-tube amplifier and the push-pull amplifier is not achieved, and the gain and speed are insufficient.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present application provides an amplifier circuit and an electronic device, which can improve the gain and amplification speed of the input signal processing by the amplifier circuit.

A technical solution adopted in the present application is to provide an amplifier circuit, the amplifier circuit includes a push-pull circuit, including: a first transistor, a first end of the first transistor is input with a power supply signal, and a second end of the first transistor is used for output; a second transistor, the first end of the second transistor is connected to the second end of the first transistor, and the second end of the second transistor is grounded; level shift circuit, the first end of the level shift circuit is connected to the control of the first transistor terminal, the second terminal of the level shift circuit is connected to the control terminal of the second transistor; the amplifier circuit is connected to the control terminal of the second transistor, and is used to generate an amplified signal under the action of the input signal, and input the amplified signal to the second transistor the control terminal.

Wherein, the level shift circuit includes: a third transistor, the first end of the third transistor is connected to the control end of the first transistor, the second end of the third transistor is connected to the control end of the second transistor; The first terminal is connected to the control terminal of the first transistor, and the second terminal of the fourth transistor is connected to the control terminal of the second transistor.

Wherein, the amplifier circuit further includes a constant current source, the first terminal of the constant current source is input with a power supply signal, and the second terminal of the constant current source is connected to the control terminal of the first transistor.

The amplifying circuit includes a sixth transistor and a seventh transistor; wherein the first end of the sixth transistor is connected to the second end of the seventh transistor, the second end of the sixth transistor is grounded, and the control end of the sixth transistor is used for inputting signals ; The first end of the seventh transistor is connected to the control end of the second transistor.

The amplifier circuit further includes a bias circuit; the first end of the bias circuit is input with a power supply signal, the second end of the bias circuit is connected to the control end of the fifth transistor, and the third end of the bias circuit is connected to the control end of the seventh transistor , the fourth terminal of the bias circuit is grounded.

The bias circuit includes an eighth transistor, a ninth transistor, a tenth transistor and a resistor; wherein the first end of the eighth transistor is input with a power supply signal, and the second end of the eighth transistor is connected to the control end of the eighth transistor and the ninth transistor The control terminal of the transistor; the first terminal of the ninth transistor is input with a power supply signal, the second terminal of the ninth transistor is connected to the control terminal of the seventh transistor; the first terminal of the resistor is connected to the eighth transistor, and the second terminal of the resistor is grounded; the tenth transistor is connected to the ground; The first end of the ninth transistor is connected to the second end of the ninth transistor; the second end of the tenth transistor is grounded, and the control end of the tenth transistor is connected to the third end of the bias circuit.

The amplifying circuit includes an eleventh transistor and a twelfth transistor; wherein the first end of the twelfth transistor is input with a power supply signal, the second end of the twelfth transistor is connected to the first end of the eleventh transistor, and the twelfth transistor is connected to the first end of the eleventh transistor. The control terminal of the transistor is used for inputting a signal, and the second terminal of the eleventh transistor is connected to the control terminal of the first transistor.

Wherein, the amplifier circuit further includes a first input voltage circuit; the first input voltage circuit includes: a thirteenth transistor, the first end of the thirteenth transistor inputs a power supply signal, and the second end of the thirteenth transistor is connected to the thirteenth transistor Control terminal; fourteenth transistor, the first terminal of the fourteenth transistor is connected to the second terminal of the thirteenth transistor, and the second terminal of the fourteenth transistor is connected to the control terminal of the fourteenth transistor and the first terminal of the level shift circuit The control terminal is used to provide the first reference voltage to the level shift circuit; the fifteenth transistor, the first terminal of the fifteenth transistor is connected to the second terminal of the fourteenth transistor, the second terminal of the fifteenth transistor is grounded, and the first terminal of the fifteenth transistor is connected to the ground. The control terminals of the fifteen transistors are used for receiving control signals.

Wherein, the amplifier circuit further includes a second input voltage circuit; the second input voltage circuit includes: a sixteenth transistor, the first end of the sixteenth transistor inputs a power supply signal, and the second end of the sixteenth transistor is connected to the level shift circuit The second control terminal is used to provide the second reference voltage to the level shift circuit; the seventeenth transistor, the first terminal of the seventeenth transistor and the control terminal are connected to the second terminal of the sixteenth transistor; the eighteenth transistor, the The first end of the eighteenth transistor is connected to the second end of the seventeenth transistor, the second end of the eighteenth transistor is grounded, and the control end of the eighteenth transistor is connected to the second end of the seventeenth transistor.

Another technical solution adopted in the present application is to provide an electronic device, the electronic device includes: an amplifier circuit, such as the amplifier circuit provided by the above solution; a controller connected to the amplifier circuit for inputting a signal to the amplifier circuit to The amplifier circuit is made to amplify the input signal.

The beneficial effects of the present application are: different from the situation in the prior art, an amplifier circuit of the present application includes: a push-pull circuit, including: a first transistor, a first end of the first transistor inputs a power supply signal, a first The second end of a transistor is used for output; for the second transistor, the first end of the second transistor is connected to the second end of the first transistor, and the second end of the second transistor is grounded; the level shift circuit, the first end of the level shift circuit One end is connected to the control end of the first transistor, the second end of the level shift circuit is connected to the control end of the second transistor; the amplifier circuit is connected to the control end of the second transistor, and is used to generate an amplified signal under the action of the input signal, and The amplified signal is input to the control terminal of the second transistor. In the above manner, by combining the push-pull circuit and the amplifier circuit, the input signal is amplified once in the amplifying circuit, and then is amplified twice by the push-pull circuit, which can improve the gain and amplifying speed of the input signal processing by the amplifier circuit.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

1 is a schematic structural diagram of an embodiment of an amplifier circuit provided by the present application;

FIG. 2 is a schematic structural diagram of an embodiment of the push-pull circuit in FIG. 1 provided by the present application;

3 is a schematic structural diagram of an embodiment of the amplifying circuit in FIG. 1 provided by the present application;

FIG. 4 is a schematic structural diagram of the amplifier circuit formed by the combination of FIG. 2 and FIG. 3 provided by the present application;

5 is a schematic structural diagram of another embodiment of an amplifier circuit provided by the present application;

6 is a schematic structural diagram of another embodiment of an amplifier circuit provided by the present application;

7 is a schematic structural diagram of another embodiment of an amplifier circuit provided by the present application;

8 is a schematic structural diagram of another embodiment of an amplifier circuit provided by the present application;

FIG. 9 is a schematic structural diagram of an embodiment of an electronic device provided by the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all the structures related to the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The amplifier circuit can increase the output power of the signal. It obtains the energy source through the power supply to control the waveform of the output signal to be consistent with the input signal, but with a larger amplitude. In this regard, the amplifier circuit can also be regarded as an adjustable output power supply to obtain an output signal stronger than the input signal. The amplifier circuit is composed of transistors (or field effect transistors), capacitors, resistors and power supplies. The amplifying circuit enhances the weak electrical signal to the required voltage, current or power value through power conversion, that is, uses the amplification and control of the transistor (or field effect transistor) to convert the energy of the power supply into a proportional change in the input quantity. output.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of an embodiment of an amplifier circuit provided by the present application. The amplifier circuit 10 includes a push-pull circuit 11 and an amplifier circuit 12 .

The push-pull circuit 11 includes a first transistor M1 , a second transistor M2 and a level shift circuit 111 . The first terminal a1 of the first transistor M1 is input with a power supply signal, and the second terminal b1 of the first transistor M1 is used for output. The first end a2 of the second transistor M2 is connected to the second end b1 of the first transistor M1 , and the second end b2 of the second transistor M2 is grounded. The first terminal a3 of the level shift circuit 111 is connected to the control terminal c1 of the first transistor M1, and the second terminal b3 of the level shift circuit 111 is connected to the control terminal c2 of the second transistor M2.

The level shift circuit 111 includes a third transistor and a fourth transistor. The first end of the third transistor is connected to the control end of the first transistor, the second end of the third transistor is connected to the control end of the second transistor; the first end of the fourth transistor is connected to the control end of the first transistor, and the second end of the fourth transistor is connected to the control end of the first transistor. The two terminals are connected to the control terminal of the second transistor. Through the level shift circuit 111 composed of the third transistor and the fourth transistor, when the third transistor is a P-type MOS transistor and the fourth transistor is an N-type MOS transistor, the level shift can be realized in terms of large signals, so that the NMOS and The gate voltage value of PMOS is separated to realize separate control; it can also realize input and output level follow-up in terms of small signals, and AC short circuit, so that small signals can be amplified in the output stage.

Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of an embodiment of a push-pull circuit provided by the present application.

The push-pull circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4. In some embodiments, the above transistors are all MOS transistors, the source of the first transistor M1 is connected to the power supply, the drain of the first transistor M1 is connected to the drain of the second transistor M2, and the gate of the first transistor M1 is connected to the third The source of the transistor M3 and the drain of the fourth transistor M4. The source of the second transistor M2 is grounded, the drain of the second transistor M2 is connected to the drain of the first transistor M1, and the gate of the first transistor M1 is connected to the drain of the third transistor M3 and the source of the fourth transistor M4. The drain of the first transistor M1 and the drain of the second transistor M2 are connected to the output terminal OUT for outputting the amplified signal, and the output terminal OUT can be connected to the load. A control voltage is input to the gate of the third transistor M3 and the gate of the fourth transistor M4. The drain of the third transistor M3 is connected to the source of the fourth transistor M4, and the source of the third transistor M3 is connected to the drain of the fourth transistor M4. The third transistor M3 and the fourth transistor M4 form the level shift circuit 111 in FIG. 1 by virtue of the above connection relationship. The source of the third transistor M3 corresponds to the first end of the third transistor, and the drain of the third transistor M3 corresponds to the second end of the third transistor. The source of the fourth transistor M4 corresponds to the second terminal of the fourth transistor, and the drain of the fourth transistor M4 corresponds to the first terminal of the fourth transistor.

The amplifying circuit 12 is connected to the control terminal of the second transistor M2 for generating an amplified signal under the action of the input signal, and inputting the amplified signal to the control terminal of the second transistor M2.

Referring to FIG. 3 , FIG. 3 is a schematic structural diagram of an embodiment of an amplifying circuit provided by the present application.

The amplifying circuit 12 includes a sixth transistor M6 and a seventh transistor M7. The first end of the sixth transistor M6 is connected to the second end of the seventh transistor M7, the second end of the sixth transistor M6 is grounded, and the control end of the sixth transistor M6 is used for inputting signals; the first end of the seventh transistor M7 The control terminal of the second transistor M2 is connected. The input small signal can be amplified once in the sixth transistor M6 of the amplifying circuit 12, and then amplified again in the seventh transistor M7 to achieve two amplifications.

In some embodiments, the above transistors are all MOS transistors, and the gate of the sixth transistor M6 is used for receiving an input signal. When the voltage V _GS of the input signal at the gate is greater than the reference voltage, the sixth transistor M6 generates a current I ₁ . The gate of the seventh transistor M7 is used for receiving the control signal. When the voltage V _GS of the gate is greater than the reference voltage, since the sixth transistor M6 is turned on, the seventh transistor M7 is turned on to generate the current I ₂ .

Because the source of the sixth transistor M6 is grounded, the reference voltage is very small, so the input signal of the small signal will be greater than the reference voltage, and the sixth transistor M6 is turned on. Since the sixth transistor M6 has been turned on, the reference voltage of the seventh transistor M7 is also very small, so the gate of the seventh transistor M7 is input with a control signal to turn on the seventh transistor M7.

Combining FIG. 2 and FIG. 3 , a schematic structural diagram of the amplifier circuit shown in FIG. 4 can be obtained, wherein the drain of the seventh transistor M7 is connected to the gate of the second transistor M2 . Since the drain of the third transistor M3 and the source of the fourth transistor M4 are both connected to the gate of the second transistor M2, the drain of the third transistor M3, the source of the fourth transistor M4 and the drain of the seventh transistor M7 There will be a common point A. Since the source of the third transistor M3 and the drain of the fourth transistor M4 are both connected to the gate of the first transistor M1, a common point B exists.

In an application scenario, the common point B is also connected with a corresponding power supply loop. When the gate input voltage of the third transistor M3 is VCC-2V _GS , the gate input voltage of the fourth transistor M4 is 2V _GS , and the seventh transistor M4 has a gate input voltage of 2V GS . When the gate of M7 is connected to the voltage, and the gate of the sixth transistor M6 is connected to the input signal IN, if the voltage of the input signal IN is greater than the reference voltage of the sixth transistor M6, the sixth transistor M6 is turned on, and the voltage from the common point B to the common point A to the seventh transistor M7 to the sixth transistor M6 form a loop. At this time, the input signal is input from IN, the small signal is amplified once through the sixth transistor M6, and output from the drain of the sixth transistor M6, because the drain of the sixth transistor M6 and the source of the seventh transistor M7, and then through the seventh The transistor M7 is amplified once, and is output from the drain of the seventh transistor M7 to the G common point A, and then to the gate of the second transistor M2, and is amplified again in the second transistor M2. At this time, since the voltage of point A changes, point B changes correspondingly in the same direction, and the changed voltage is applied to the gate of the first transistor M1. Among them, from the input signal IN to point A is a cascode structure (Cascode), which has a high gain.

Specifically, when the input signal voltage gradually increases from 0, after the sixth transistor M6 is turned on, the potential of point A is quickly pulled down to a low level, and the second transistor M2 is turned off, and at the same time, point B is turned off. The potential and the potential of point A decrease in the same direction, are pulled down to a low level, the first transistor M1 is quickly turned on, and the drain of the first transistor M1 quickly outputs a high level; when the input signal voltage gradually decreases from a high level In small cases, when the sixth transistor M6 is turned off, the potential of point A is quickly pulled up to a high level, the second transistor M2 is turned on, and the drain of the second transistor M2 quickly outputs a low level, and at the same time, The potential of point B increases in the same direction as the potential of point A, and is pulled up to a high level, then the first transistor M1 is turned off.

In other embodiments, the transistors in the amplifier circuit may be bipolar transistors (BJTs) or field effect transistors (FETs, unipolar). The transistor has three poles (terminals); the three poles (terminals) of the bipolar transistor are the emitter (Emitter), the base (Base) and the collector (Collector) composed of N-type and P-type semiconductors respectively; The three poles (terminals) of the effect transistor are the source (Source), the gate (Gate) and the drain (Drain) respectively. The specific type should be replaced according to the actual needs of the arrester circuit.

Different from the situation in the prior art, an amplifier circuit of the present application includes: a push-pull circuit, including: a first transistor, a first end of the first transistor inputs a power supply signal, and a second end of the first transistor uses output; the second transistor, the first end of the second transistor is connected to the second end of the first transistor, the second end of the second transistor is grounded; the level shift circuit, the first end of the level shift circuit is connected to the first end of the first transistor The control terminal, the second terminal of the level shift circuit is connected to the control terminal of the second transistor; the amplifier circuit is connected to the control terminal of the second transistor, and is used to generate an amplified signal under the action of the input signal, and input the amplified signal to the second transistor. control terminal of the transistor. In the above manner, by combining the push-pull circuit and the amplifier circuit, the input signal is amplified once in the amplifying circuit, and then is amplified twice by the push-pull circuit, which can improve the gain and amplifying speed of the input signal processing by the amplifier circuit.

Referring to FIG. 5 , FIG. 5 is a schematic structural diagram of another embodiment of the amplifier circuit provided by the present application. The amplifier circuit 10 includes a first transistor M1, a second transistor M2, a level shift circuit 111, an amplifier circuit 12, a bias circuit 13, a first input voltage circuit 14, a second input voltage circuit 15, and a fifth transistor M5.

The level shift circuit 111 includes a third transistor M3 and a fourth transistor M4. The amplifying circuit 12 includes a sixth transistor M6 and a seventh transistor M7. The connection relationship between the transistors has been described in the above embodiments, and will not be repeated here.

In other embodiments, the fifth transistor M5 can be replaced with any kind of constant current source, wherein the first end of the constant current source is input with the power signal, and the second end of the constant current source is connected to the control end of the first transistor, which can Under the constant voltage provided by the first input voltage circuit 14 and the second input voltage circuit 15, a constant current is provided, so that both the third transistor M3 and the fourth transistor M4 in the level shift circuit 111 work in the saturated constant current source region, so as to realize level shift.

The first end of the bias circuit 13 is input with a power supply signal, the second end of the bias circuit 13 is connected to the control end of the fifth transistor M5, the third end of the bias circuit 13 is connected to the control end of the seventh transistor M7, and the bias circuit 13 is connected to the control end of the seventh transistor M7. The fourth terminal of the circuit 13 is grounded. The bias circuit 13 can provide a stable control terminal voltage to the control terminal of the fifth transistor M5 and the control terminal of the seventh transistor M7 under the action of the input voltage. Specifically, the bias circuit 13 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a resistor R1; the first end of the eighth transistor M8 is input with a power supply signal, and the second end of the eighth transistor M8 is connected to the eighth transistor The control terminal of M8 and the control terminal of the ninth transistor M9; the first terminal of the ninth transistor M9 inputs the power supply signal, the second terminal of the ninth transistor M9 is connected to the control terminal of the seventh transistor M7; the first terminal of the resistor R1 is connected to the eighth transistor M7. In the transistor M8, the second end of the resistor R1 is grounded; the first end of the tenth transistor M10 is connected to the second end of the ninth transistor M9; the second end of the tenth transistor M10 is grounded, and the control end of the tenth transistor M10 is connected to the bias circuit The third end of 13. The bias circuit 13 provides the control terminal input voltage for the seventh transistor M7 through the connection of the above-mentioned transistors, so that the seventh transistor M7 is in a conducting state, and further amplifies the input signal input from the sixth transistor M6, which is also used for the subsequent sixth transistor M6. An input voltage circuit 14 and a second input voltage circuit 15 provide voltages so that the first input voltage circuit 14 and the second input voltage circuit 15 work normally.

The first input voltage circuit 14 includes a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The first end of the thirteenth transistor M13 is input with a power supply signal, the second end of the thirteenth transistor M13 is connected to the control end of the thirteenth transistor M13; the first end of the fourteenth transistor M14 is connected to the second end of the thirteenth transistor M13 terminal, the second terminal of the fourteenth transistor M14 is connected to the control terminal of the fourteenth transistor M14 and the first control terminal of the level shift circuit 111 for providing the first reference voltage to the level shift circuit 111 . Specifically, the second terminal of the fourteenth transistor M14 is connected to the control terminal of the third transistor M3 in the level shift circuit 111, so as to provide the first reference voltage to the control terminal of the third transistor M3; The first end is connected to the second end of the fourteenth transistor M14, the second end of the fifteenth transistor M15 is grounded, and the control end of the fifteenth transistor M15 is connected to the second end of the ninth transistor. The first input voltage circuit 14 can provide a stable control end input voltage to the control end of the third transistor M3 during operation by being connected in the above manner. For example, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are all MOS transistors, and the voltage between the gate and the source of the thirteenth transistor M13 and the fourteenth transistor M14 is V _gs , and the power supply is VCC, then the input voltage of the control terminal of the third transistor M3 is VCC-2V _gs , and this input voltage is the first reference voltage.

The second input voltage circuit 15 includes a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The first terminal of the sixteenth transistor M16 is input with a power supply signal, and the second terminal of the sixteenth transistor M16 is connected to the second control terminal of the level shift circuit 111 for providing a second reference voltage to the level shift circuit 111 . Specifically, the second terminal of the sixteenth transistor M16 is connected to the control terminal of the fourth transistor M4 in the level shift circuit 111, so as to provide the second reference voltage to the control terminal of the fourth transistor M4; The first end and the control end are connected to the second end of the sixteenth transistor M16; the first end of the eighteenth transistor M18 is connected to the second end of the seventeenth transistor M17, the second end of the eighteenth transistor M18 is grounded, and the tenth transistor M18 is connected to the ground. The control terminals of the eight transistors M18 are connected to the second terminals of the seventeenth transistor M17. The second input voltage circuit 15 can provide a stable control end input voltage to the control end of the fourth transistor M4 during operation through the above-mentioned connection. For example, the sixteenth transistor M16, the seventeenth transistor M17 and the eighteenth transistor M18 are MOS transistors, and the voltage between the gate and the source of the seventeenth transistor M17 and the eighteenth transistor M18 is V _gs , and the power supply is VCC , then the input voltage of the control terminal of the fourth transistor is 2V _gs , and the input voltage is the second reference voltage.

The fifth transistor M5 is a MOS transistor. The fifth transistor M5 is a tail current load tube, which is used to realize a constant current under the control of the gate input voltage of the fifth transistor M5, thereby controlling the level shift circuit 111 connected to the drain of the fifth transistor M5 and A loop between the amplifier circuits 12 connected to the level shift circuit 111 . When the potential at point A increases, the current flowing through the fourth transistor M4 decreases, and the current flowing through the third transistor M3 increases, so the potential at point B increases. When the potential at point A drops, the current flowing through the fourth transistor M4 increases, and the current flowing through the third transistor M3 decreases, and the potential at point B drops. Therefore, the AC small signal short circuit at point A and point B is realized.

Since there are MOS transistors in the level shift circuit 111 , the amplifier circuit 12 , the fifth transistor M5 , the first input voltage circuit 14 and the second input voltage circuit 15 , the bias circuit 13 is used to shift the level shift circuit 111 , the amplifier circuit 12. The gate input voltage of the corresponding MOS transistors in the fifth transistor M5, the first input voltage circuit 14 and the second input voltage circuit 15.

Based on Figure 5, describe the working logic of the entire amplifier circuit:

Looking at the bias circuit 13 first, the source of the eighth transistor M8 in the bias circuit 13 is connected to the power supply VCC, and the drain is connected to the first end of the resistor R1 and the gate. The source of the ninth transistor M9 is connected to the power supply VCC, the drain is connected to the drain of the tenth transistor M10, and the gate is connected to the gate of the eighth transistor M8. The second end of the resistor R and the source of the tenth transistor M10 are grounded. The eighth transistor M8 and the ninth transistor M9 are P-type MOS transistors, and the tenth transistor M10 is an N-type MOS transistor. After the power VCC passes through the eighth transistor M8, it is pulled down to a low level by the resistor R1, the eighth transistor M8 is turned on, and the source-gate voltage difference generated on M8 is output to the source-gate of the ninth transistor M9, so that M9 Turning on generates a current, the current passes through the tenth transistor M10, and then generates a gate-source voltage difference.

Next, looking at the first input voltage circuit 14, the source of the thirteenth transistor M13 in the first input voltage circuit 14 is connected to the power supply VCC, the drain is connected to the gate, and the drain is connected to the source of the fourteenth transistor M14. The drain and gate of the fourteenth transistor M14 are connected to the drain of the fifteenth transistor M15, and the gate of the fourteenth transistor M14 is connected to the gate of the third transistor M3. The source of the fifteenth transistor M15 is grounded, the gate of the fifteenth transistor M15 is connected to the gate of the tenth transistor M10, and the drain of the ninth transistor M9 is connected. At this time, the gate-source voltage difference of the tenth transistor M10 is output to the fifteenth transistor M15, and the fifteenth transistor M15 is turned on. At this time, the first input voltage circuit 14 forms a loop. Then, the input voltage on the gate of the third transistor M3 is the voltage of the thirteenth transistor M13 and the fourteenth transistor M14 removed from the power supply VCC. The thirteenth transistor M13 and the fourteenth transistor M14 are P-type MOS transistors, and the fifteenth transistor M15 is an N-type MOS transistor.

Next, look at the second input voltage circuit 15. In the second input voltage circuit 15, the sixteenth transistor M16 is a P-type MOS transistor, and the seventeenth transistor M17 and the eighteenth transistor M18 are N-type MOS transistors. The source of the sixteenth transistor M16 in the second input voltage circuit 15 is connected to the power supply VCC, the drain of the sixteenth transistor M16 is connected to the drain of the seventeenth transistor M17 and the gate of the seventeenth transistor M17, the tenth The gates of the six transistors M16 are connected to the gates of the eighth transistor M8. The source of the seventeenth transistor M17 is connected to the drain of the eighteenth transistor M18, and is connected to the gate of the eighteenth transistor M18. The source of the eighteenth transistor M18 is grounded. The entire second input voltage circuit 15 forms a loop, and the voltage input to the gate of the fourth transistor M4 is the sum of the gate voltages of the seventeenth transistor M17 and the eighteenth transistor M18.

Next, look at the fifth transistor M5. The fifth transistor M5 is a P-type MOS transistor. The source of the fifth transistor M5 is connected to the power supply VCC, the drain of the fifth transistor M5 is connected to the gate of the first transistor M1 and the source of the third transistor M3 and the drain of the fourth transistor M4, and the gate of the fifth transistor M5 The electrode is connected to the gate of the eighth transistor M8.

In some embodiments, all the above transistors are MOS transistors, then the voltage between the gate and the source of the MOS transistor is V _GS , the corresponding gate input voltage of the third transistor M3 is VCC-2V _GS , the fourth The gate input voltage of transistor M4 is 2V _GS . Correspondingly in Figure 5, the large signal analysis, for point A, V _A = 2V _GS -V _GS,M4 , for point B, V _B =VCC-2V _GS +V _GS,M3 , because the gates of all MOS transistors and The voltages between the sources are all V _GS , then VA ₌ V _GS , and _VB =VCC-V _GS . Therefore, both the third transistor M3 and the fourth transistor M4 work in the saturated constant current source region.

Small signal analysis: when VA superimposes the voltage small signal _Δ >0, the V _GS of the fourth transistor M4 decreases, the current flowing through the fourth transistor M4 decreases, and the current flowing through the third transistor M3 increases, and V The voltage of _B increases by Δ. So point A and point B are AC short circuited.

The change of the input signal IN is to amplify once by the sixth transistor M6, then amplify once by the seventh transistor M7, and then synchronously pass through points A and B, and amplify again on the first transistor M1 and the second transistor M2.

In the above manner, the input signal IN is amplified in the amplifier circuit, then output to point A, and amplified again in the push-pull circuit, which can improve the gain and amplifying speed of the input signal processing by the amplifier circuit.

Referring to FIG. 6, the amplifier circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor Transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, seventeenth transistor M17, eighteenth transistor M18 and resistor R1.

Among them, the first transistor M1, the third transistor M3, the eighth transistor M8, the ninth transistor M9, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14 and the sixteenth transistor M16 is a P-type MOS transistor, and the second transistor M2, the fourth transistor M4, the seventh transistor M7, the tenth transistor M10, the fifteenth transistor M15, the seventeenth transistor M17 and the eighteenth transistor M18 are N-type MOS transistors.

The source of the first transistor M1 is connected to the power supply VCC, the drain is connected to the drain of the second transistor M2 and the output terminal OUT, and the gate is connected to the drain of the eleventh transistor M11, the source of the third transistor M3 and the fourth transistor M4 drain. The drain of the second transistor M2 is connected to the output terminal, the source is grounded, and the gate is connected to the drain of the seventh transistor M7, the drain of the third transistor M3 and the source of the fourth transistor M4. The gate of the third transistor M3 is connected to the gate of the fourteenth transistor M14. The gate of the fourth transistor M4 is connected to the gate of the seventeenth transistor M17. The gate of the seventh transistor M7 is connected to the drain of the ninth transistor M9, and the source is grounded. The source of the eighth transistor M8 is connected to the power supply VCC, the drain is connected to the first end of the resistor R1 and the gate, and the gate is connected to the gate of the ninth transistor M9. The other end of the resistor R1 is grounded.

The source of the ninth transistor M9 is connected to the power supply VCC, and the drain is connected to the drain of the tenth transistor M10. The gate of the tenth transistor M10 is connected to the drain of the ninth transistor M9 and the gate of the fifteenth transistor M15. The gate of the thirteenth transistor M13 is connected to the power supply VCC, and the drain is connected to the gate and the source of the fourteenth transistor M14. The drain of the fourteenth transistor M14 is connected to the gate and the drain of the fifteenth transistor M15. The source of the fifteenth transistor M15 is grounded. The source of the sixteenth transistor M16 is connected to the power supply VCC, the drain is connected to the drain of the seventeenth transistor M17, and the gate is connected to the gate of the eighth transistor M8. The drain of the seventeenth transistor M17 is connected to the gate, the source is connected to the drain of the eighteenth transistor M18, and the gate is connected to the gate of the fourth transistor M4. The source of the eighteenth transistor M18 is grounded, and the drain is connected to the gate. The source of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12, the drain is connected to the source of the third transistor M3, the drain of the fourth transistor M4 and the gate of the first transistor M1, and the gate is connected to the eighth transistor M1. gate of transistor M8. The source of the twelfth transistor M12 is connected to the power supply VCC, and the gate is used to receive the input signal IN.

At this time, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the resistor R1 constitute the bias circuit 13 as in the above embodiment, and the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 constitute Like the first input voltage circuit 14 in the above-described embodiment, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 constitute the second input voltage circuit 15 as in the above-described embodiment. The eleventh transistor M11 and the twelfth transistor M12 constitute the amplifying circuit 12 as in the above embodiment, and the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 constitute the push-pull as in the above embodiment circuit 11. The third transistor M3 and the fourth transistor M4 constitute the level shift circuit 111 in the push-pull circuit as in the above-mentioned embodiment.

Briefly describe the workflow of Figure 6:

The voltage between the gate and the source of all MOS transistors in FIG. 6 is V _GS , the corresponding gate input voltage of the third transistor M3 is VCC-2V _GS , and the gate input voltage of the fourth transistor M4 is 2V _GS , then corresponding to Figure 6, large signal analysis, for point _A , VA = 2V _GS -V _{GS, M4} , for point _B , VB = VCC - 2V _GS +V _{GS, M3} , because the gates of all MOS transistors The voltage between the pole and the source is V _GS , then VA ₌ V _GS , _VB =VCC-V _GS . Therefore, both the third transistor M3 and the fourth transistor M4 work in the saturated constant current source region.

Small signal analysis: when V _B superimposes the voltage small signal Δ>0, the V _GS of the third transistor M3 increases, the current flowing through the third transistor M3 increases, and the current flowing through the fourth transistor M4 decreases, V _A The voltage increases by Δ. So point A and point B are AC short circuited.

The change of the input signal IN is to amplify once through the twelfth transistor M12, and then through the eleventh transistor M11, and then synchronously pass through points A and B, and amplify again on the first transistor M1 and the second transistor M2.

Through the above method, the input signal IN is amplified and output to point B in the eleventh transistor M11 and the twelfth transistor M12, and amplified again in the push-pull circuit, which can improve the gain and amplifying speed of the input signal processing by the amplifier circuit.

In other embodiments, the above transistor may be a CMOS (Complementary Metal Oxide Semiconductor) process or a BJT (Bipolar Junction Transistor, bipolar junction transistor) process, or a bulk silicon BCD process or SOI (Silicon- On-Insulator)-BCD process transistor. Among them, the BCD process refers to the technology that can fabricate bipolar, CMOS and DMOS devices on the same chip.

In some embodiments, referring to FIG. 7 , the transistor is a triode as an example to illustrate:

The amplifier circuit includes transistor Q1, transistor Q2, transistor Q3, transistor Q4, transistor Q5, transistor Q6, transistor Q7, transistor Q8, transistor Q9, transistor Q10, transistor Q11, transistor Q12, transistor Q13, transistor Q14, transistor Q15, transistor Q16 and resistor R1.

Among them, transistor Q1, transistor Q3, transistor Q5, transistor Q8, transistor Q9, transistor Q11, transistor Q12 and transistor Q14 are PNP type transistors, transistor Q2, transistor Q4, transistor Q6, transistor Q7, transistor Q10, transistor Q13, transistor Q15 And the transistor Q16 is an NPN type transistor.

The emitter of the transistor Q1 is connected to the power supply VCC, the collector is connected to the collector of the transistor Q2 and the output terminal OUT, and the base is connected to the collector of the transistor Q5, the emitter of the transistor Q3 and the collector of the transistor Q4. The collector of the transistor Q2 is connected to the output terminal, the emitter is grounded, and the base is connected to the collector of the transistor Q7, the collector of the transistor Q3 and the emitter of the transistor Q4. The base of the transistor Q3 is connected to the base of the transistor Q12. The base of the transistor Q4 is connected to the base of the transistor Q15. The base of the transistor Q7 is connected to the collector of the transistor Q9, and the emitter is connected to the collector of the transistor Q6. The emitter of the transistor Q6 is grounded, and the base is connected to the input signal IN. The emitter of the transistor Q8 is connected to the power supply VCC, the collector is connected to the first end of the resistor R1 and the base, and the base is connected to the base of the transistor Q9. The other end of the resistor R1 is grounded.

The emitter of the transistor Q9 is connected to the power supply VCC, and the collector is connected to the collector of the transistor Q10. The base of the transistor Q10 is connected to the collector of the transistor Q9 and the base of the transistor Q13. The base of the transistor Q11 is connected to the power supply VCC, and the collector is connected to the base and the emitter of the transistor Q12. The collector of the transistor Q12 is connected to the base and the collector of the transistor Q13. The emitter of the transistor Q13 is grounded. The emitter of the transistor Q14 is connected to the power supply VCC, the collector is connected to the collector of the transistor Q15, and the base is connected to the base of the transistor Q8. The collector of the transistor Q15 is connected to the base, the emitter is connected to the collector of the transistor Q16, and the base is connected to the base of the transistor Q4. The emitter of the transistor Q16 is grounded, and the collector is connected to the base.

At this time, the transistor Q8, the transistor Q9, the transistor Q10 and the resistor R1 constitute the bias circuit 13 as in the above embodiment, the transistor Q11, the transistor Q12 and the transistor Q13 constitute the first input voltage circuit 14 as in the above embodiment, the transistor Q14 , the transistor Q15 and the transistor Q16 constitute the second input voltage circuit 15 as in the above embodiment. The transistor Q6 and the transistor Q7 constitute the amplifying circuit 12 in the above embodiment, and the transistor Q1, the transistor Q2, the transistor Q3 and the transistor Q4 constitute the push-pull circuit 11 in the above embodiment. Among them, the transistor Q3 and the transistor Q4 constitute the level shift circuit 111 in the push-pull circuit 11 as in the above embodiment.

In some embodiments, referring to FIG. 8 , the transistor is a triode as an example to illustrate:

The amplifier circuit includes transistor Q1, transistor Q2, transistor Q3, transistor Q4, transistor Q7, transistor Q8, transistor Q9, transistor Q10, transistor Q11, transistor Q12, transistor Q13, transistor Q14, transistor Q15, transistor Q16, transistor Q17, transistor Q18 and resistor R1.

Among them, triode Q1, triode Q3, triode Q8, triode Q9, triode Q11, triode Q12, triode Q14, triode Q17 and triode Q18 are PNP type triodes, triode Q2, triode Q4, triode Q7, triode Q10, triode Q13, triode Q15 And the transistor Q16 is an NPN type transistor.

The emitter of the transistor Q1 is connected to the power supply VCC, the collector is connected to the collector of the transistor Q2 and the output terminal OUT, and the base is connected to the collector of the transistor Q17, the emitter of the transistor Q3 and the collector of the transistor Q4. The collector of the transistor Q2 is connected to the output terminal, the emitter is grounded, and the base is connected to the collector of the transistor Q7, the collector of the transistor Q3 and the emitter of the transistor Q4. The base of the transistor Q3 is connected to the base of the transistor Q12. The base of the transistor Q4 is connected to the base of the transistor Q15. The base of the transistor Q7 is connected to the collector of the transistor Q9, and the emitter is grounded. The emitter of the transistor Q8 is connected to the power supply VCC, the collector is connected to the first end of the resistor R1 and the base, and the base is connected to the base of the transistor Q9. The other end of the resistor R1 is grounded.

The emitter of the transistor Q9 is connected to the power supply VCC, and the collector is connected to the collector of the transistor Q10. The base of the transistor Q10 is connected to the collector of the transistor Q9 and the base of the transistor Q13. The base of the transistor Q11 is connected to the power supply VCC, and the collector is connected to the base and the emitter of the transistor Q12. The collector of the transistor Q12 is connected to the base and the collector of the transistor Q13. The emitter of the transistor Q13 is grounded. The emitter of the transistor Q14 is connected to the power supply VCC, the collector is connected to the collector of the transistor Q15, and the base is connected to the base of the transistor Q8. The collector of the transistor Q15 is connected to the base, the emitter is connected to the collector of the transistor Q16, and the base is connected to the base of the transistor Q4. The emitter of the transistor Q16 is grounded, and the collector is connected to the base. The emitter of the transistor Q17 is connected to the collector of the transistor Q18, the collector is connected to the emitter of the transistor Q3, the collector of the transistor Q4 and the base of the transistor Q1, and the base is connected to the base of the transistor Q8. The emitter of the transistor Q18 is connected to the power supply VCC, and the base is used to receive the input signal IN.

At this time, the transistor Q8, the transistor Q9, the transistor Q10 and the resistor R1 constitute the bias circuit 13 as in the above embodiment, the transistor Q11, the transistor Q12 and the transistor Q13 constitute the first input voltage circuit 14 as in the above embodiment, the transistor Q14 , the transistor Q15 and the transistor Q16 constitute the second input voltage circuit 15 as in the above embodiment. The triode Q17 and the triode Q18 constitute the amplifier circuit 12 in the above embodiment, and the triode Q1, the triode Q2, the triode Q3 and the triode Q4 constitute the push-pull circuit 11 in the above embodiment. Among them, the transistor Q3 and the transistor Q4 constitute the level shift circuit 111 in the push-pull circuit 11 as in the above embodiment.

Through the above method, the input signal IN is amplified and output to point B in the transistors Q18 and Q17, and amplified again in the push-pull circuit, which can improve the gain and amplifying speed of the input signal processing by the amplifier circuit.

Referring to FIG. 9 , FIG. 9 is a schematic structural diagram of an embodiment of an electronic device provided by the present application. The electronic device 90 includes an amplifier circuit 91 and a controller 92 .

Wherein, the amplifier circuit 91 is the amplifier circuit provided in any of the above embodiments. The controller 92 is connected to the amplifier circuit 91 for inputting a signal to the amplifier circuit 91, so that the amplifier circuit 91 amplifies the input signal.

In some examples, amplifier circuit 91 is provided on a circuit board, which is provided on electronic device 90 .

In some embodiments, the electronic device may be a mobile terminal, such as a mobile phone, a household appliance, such as an air conditioner, a refrigerator, a washing machine, a microwave oven, etc., or a wearable device, such as a smart bracelet, a smart watch, or a Computers, printers, fax machines, all-in-one machines and other terminal equipment. It can also be the corresponding electronic production equipment, such as placement machines and automatic welding.

In the above manner, the amplifier circuit in the electronic device can improve the gain and amplifying speed of processing the input signal of the controller, thereby improving the working efficiency and performance of the electronic device.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. An amplifier circuit, comprising:

a push-pull circuit comprising:

a first transistor, a first terminal of which inputs a power supply signal and a second terminal of which is used for output;

a second transistor, wherein a first end of the second transistor is connected to a second end of the first transistor, and a second end of the second transistor is grounded;

a first end of the level shift circuit is connected with the control end of the first transistor, and a second end of the level shift circuit is connected with the control end of the second transistor;

and the amplifying circuit is connected with the control end of the second transistor, and is used for generating an amplifying signal under the action of an input signal and inputting the amplifying signal to the control end of the second transistor.

2. The amplifier circuit of claim 1,

the level shift circuit includes:

a third transistor, wherein a first terminal of the third transistor is connected to the control terminal of the first transistor, and a second terminal of the third transistor is connected to the control terminal of the second transistor;

a first end of the fourth transistor is connected with the control end of the first transistor, and a second end of the fourth transistor is connected with the control end of the second transistor.

3. The amplifier circuit of claim 2,

the amplifier circuit further comprises a constant current source, wherein the first end of the constant current source inputs the power supply signal, and the second end of the constant current source is connected with the control end of the first transistor.

4. The amplifier circuit of claim 3,

the amplification circuit includes a sixth transistor and a seventh transistor:

a first end of the sixth transistor is connected to the second end of the seventh transistor, a second end of the sixth transistor is grounded, and a control end of the sixth transistor is used for inputting a signal;

and the first end of the seventh transistor is connected with the control end of the second transistor.

5. The amplifier circuit of claim 4,

the amplifier circuit further comprises a bias circuit;

the first end of the bias circuit inputs the power supply signal, the second end of the bias circuit is connected with the control end of the fifth transistor, the third end of the bias circuit is connected with the control end of the seventh transistor, and the fourth end of the bias circuit is grounded.

6. The amplifier circuit of claim 5,

the bias circuit comprises an eighth transistor, a ninth transistor, a tenth transistor and a resistor;

a first end of the eighth transistor is used for inputting a power supply signal, and a second end of the eighth transistor is connected with a control end of the eighth transistor and a control end of the ninth transistor;

a first end of the ninth transistor is used for inputting a power supply signal, and a second end of the ninth transistor is connected with the control end of the seventh transistor;

the first end of the resistor is connected with the eighth transistor, and the second end of the resistor is grounded;

a first terminal of the tenth transistor is connected to a second terminal of the ninth transistor; the second end of the tenth transistor is grounded, and the control end of the tenth transistor is connected with the third end of the bias circuit.

7. The amplifier circuit of claim 2,

the amplifying circuit includes an eleventh transistor and a twelfth transistor;

a first end of the twelfth transistor is used for inputting a power supply signal, a second end of the twelfth transistor is connected with a first end of the eleventh transistor, a control end of the twelfth transistor is used for inputting a signal, and a second end of the eleventh transistor is connected with a control end of the first transistor.

8. The amplifier circuit of claim 1,

the amplifier circuit further comprises a first input voltage circuit;

the first input voltage circuit includes:

a thirteenth transistor, wherein a first terminal of the thirteenth transistor is input with a power supply signal, and a second terminal of the thirteenth transistor is connected with a control terminal of the thirteenth transistor;

a fourteenth transistor, a first terminal of the fourteenth transistor is connected to the second terminal of the thirteenth transistor, a second terminal of the fourteenth transistor is connected to the control terminal of the fourteenth transistor and the first control terminal of the level shift circuit, and the fourteenth transistor is configured to provide the first reference voltage to the level shift circuit;

a fifteenth transistor, a first end of the fifteenth transistor being connected to the second end of the fourteenth transistor, a second end of the fifteenth transistor being grounded, and a control end of the fifteenth transistor being configured to receive a control signal.

9. The amplifier circuit of claim 1,

the amplifier circuit further comprises a second input voltage circuit;

the second input voltage circuit includes:

a sixteenth transistor, a first end of the sixteenth transistor inputs a power signal, a second end of the sixteenth transistor is connected to the second control end of the level shift circuit, and is configured to provide a second reference voltage to the level shift circuit;

a seventeenth transistor, wherein a first terminal and a control terminal of the seventeenth transistor are connected to a second terminal of the sixteenth transistor;

and a first end of the eighteenth transistor is connected with the second end of the seventeenth transistor, a second end of the eighteenth transistor is grounded, and a control end of the eighteenth transistor is connected with the second end of the seventeenth transistor.

10. An electronic device, characterized in that the electronic device comprises:

an amplifier circuit as claimed in any one of claims 1 to 9;

and the controller is connected with the amplifier circuit and is used for inputting signals to the amplifier circuit so that the amplifier circuit amplifies the input signals.

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